1  /*
2   * Copyright (c) 2020 The Linux Foundation. All rights reserved.
3   *
4   * Permission to use, copy, modify, and/or distribute this software for
5   * any purpose with or without fee is hereby granted, provided that the
6   * above copyright notice and this permission notice appear in all
7   * copies.
8   *
9   * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10   * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11   * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12   * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13   * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14   * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15   * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16   * PERFORMANCE OF THIS SOFTWARE.
17   */
18  
19  //
20  // DO NOT EDIT!  This file is automatically generated
21  //               These definitions are tied to a particular hardware layout
22  
23  
24  #ifndef _RX_MPDU_DETAILS_H_
25  #define _RX_MPDU_DETAILS_H_
26  #if !defined(__ASSEMBLER__)
27  #endif
28  
29  #include "buffer_addr_info.h"
30  #include "rx_mpdu_desc_info.h"
31  
32  // ################ START SUMMARY #################
33  //
34  //	Dword	Fields
35  //	0-1	struct buffer_addr_info msdu_link_desc_addr_info;
36  //	2-3	struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
37  //
38  // ################ END SUMMARY #################
39  
40  #define NUM_OF_DWORDS_RX_MPDU_DETAILS 4
41  
42  struct rx_mpdu_details {
43      struct            buffer_addr_info                       msdu_link_desc_addr_info;
44      struct            rx_mpdu_desc_info                       rx_mpdu_desc_info_details;
45  };
46  
47  /*
48  
49  struct buffer_addr_info msdu_link_desc_addr_info
50  
51  			Consumer: REO/SW/FW
52  
53  			Producer: RXDMA
54  
55  
56  
57  			Details of the physical address of the MSDU link
58  			descriptor that contains pointers to MSDUs related to this
59  			MPDU
60  
61  struct rx_mpdu_desc_info rx_mpdu_desc_info_details
62  
63  			Consumer: REO/SW/FW
64  
65  			Producer: RXDMA
66  
67  
68  
69  			General information related to the MPDU that should be
70  */
71  
72  
73   /* EXTERNAL REFERENCE : struct buffer_addr_info msdu_link_desc_addr_info */
74  
75  
76  /* Description		RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
77  
78  			Address (lower 32 bits) of the MSDU buffer OR
79  			MSDU_EXTENSION descriptor OR Link Descriptor
80  
81  
82  
83  			In case of 'NULL' pointer, this field is set to 0
84  
85  			<legal all>
86  */
87  #define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
88  #define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
89  #define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
90  
91  /* Description		RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
92  
93  			Address (upper 8 bits) of the MSDU buffer OR
94  			MSDU_EXTENSION descriptor OR Link Descriptor
95  
96  
97  
98  			In case of 'NULL' pointer, this field is set to 0
99  
100  			<legal all>
101  */
102  #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
103  #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
104  #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
105  
106  /* Description		RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
107  
108  			Consumer: WBM
109  
110  			Producer: SW/FW
111  
112  
113  
114  			In case of 'NULL' pointer, this field is set to 0
115  
116  
117  
118  			Indicates to which buffer manager the buffer OR
119  			MSDU_EXTENSION descriptor OR link descriptor that is being
120  			pointed to shall be returned after the frame has been
121  			processed. It is used by WBM for routing purposes.
122  
123  
124  
125  			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
126  			to the WMB buffer idle list
127  
128  			<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
129  			returned to the WMB idle link descriptor idle list
130  
131  			<enum 2 FW_BM> This buffer shall be returned to the FW
132  
133  			<enum 3 SW0_BM> This buffer shall be returned to the SW,
134  			ring 0
135  
136  			<enum 4 SW1_BM> This buffer shall be returned to the SW,
137  			ring 1
138  
139  			<enum 5 SW2_BM> This buffer shall be returned to the SW,
140  			ring 2
141  
142  			<enum 6 SW3_BM> This buffer shall be returned to the SW,
143  			ring 3
144  
145  			<enum 7 SW4_BM> This buffer shall be returned to the SW,
146  			ring 4
147  
148  
149  
150  			<legal all>
151  */
152  #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
153  #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
154  #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
155  
156  /* Description		RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
157  
158  			Cookie field exclusively used by SW.
159  
160  
161  
162  			In case of 'NULL' pointer, this field is set to 0
163  
164  
165  
166  			HW ignores the contents, accept that it passes the
167  			programmed value on to other descriptors together with the
168  			physical address
169  
170  
171  
172  			Field can be used by SW to for example associate the
173  			buffers physical address with the virtual address
174  
175  			The bit definitions as used by SW are within SW HLD
176  			specification
177  
178  
179  
180  			NOTE:
181  
182  			The three most significant bits can have a special
183  			meaning in case this struct is embedded in a TX_MPDU_DETAILS
184  			STRUCT, and field transmit_bw_restriction is set
185  
186  
187  
188  			In case of NON punctured transmission:
189  
190  			Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
191  
192  			Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
193  
194  			Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
195  
196  			Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
197  
198  
199  
200  			In case of punctured transmission:
201  
202  			Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
203  
204  			Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
205  
206  			Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
207  
208  			Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
209  
210  			Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
211  
212  			Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
213  
214  			Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
215  
216  			Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
217  
218  
219  
220  			Note: a punctured transmission is indicated by the
221  			presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
222  			TLV
223  
224  
225  
226  			<legal all>
227  */
228  #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
229  #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
230  #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
231  
232   /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */
233  
234  
235  /* Description		RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT
236  
237  			Consumer: REO/SW/FW
238  
239  			Producer: RXDMA
240  
241  
242  
243  			The number of MSDUs within the MPDU
244  
245  			<legal all>
246  */
247  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
248  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB   0
249  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK  0x000000ff
250  
251  /* Description		RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER
252  
253  			Consumer: REO/SW/FW
254  
255  			Producer: RXDMA
256  
257  
258  
259  			The field can have two different meanings based on the
260  			setting of field 'BAR_frame':
261  
262  
263  
264  			'BAR_frame' is NOT set:
265  
266  			The MPDU sequence number of the received frame.
267  
268  
269  
270  			'BAR_frame' is set.
271  
272  			The MPDU Start sequence number from the BAR frame
273  
274  			<legal all>
275  */
276  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008
277  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8
278  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00
279  
280  /* Description		RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG
281  
282  			Consumer: REO/SW/FW
283  
284  			Producer: RXDMA
285  
286  
287  
288  			When set, this MPDU is a fragment and REO should forward
289  			this fragment MPDU to the REO destination ring without any
290  			reorder checks, pn checks or bitmap update. This implies
291  			that REO is forwarding the pointer to the MSDU link
292  			descriptor. The destination ring is coming from a
293  			programmable register setting in REO
294  
295  
296  
297  			<legal all>
298  */
299  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
300  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20
301  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000
302  
303  /* Description		RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT
304  
305  			Consumer: REO/SW/FW
306  
307  			Producer: RXDMA
308  
309  
310  
311  			The retry bit setting from the MPDU header of the
312  			received frame
313  
314  			<legal all>
315  */
316  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
317  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21
318  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000
319  
320  /* Description		RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG
321  
322  			Consumer: REO/SW/FW
323  
324  			Producer: RXDMA
325  
326  
327  
328  			When set, the MPDU was received as part of an A-MPDU.
329  
330  			<legal all>
331  */
332  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
333  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB   22
334  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK  0x00400000
335  
336  /* Description		RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME
337  
338  			Consumer: REO/SW/FW
339  
340  			Producer: RXDMA
341  
342  
343  
344  			When set, the received frame is a BAR frame. After
345  			processing, this frame shall be pushed to SW or deleted.
346  
347  			<legal all>
348  */
349  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
350  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB    23
351  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK   0x00800000
352  
353  /* Description		RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO
354  
355  			Consumer: REO/SW/FW
356  
357  			Producer: RXDMA
358  
359  
360  
361  			Copied here by RXDMA from RX_MPDU_END
362  
363  			When not set, REO will Not perform a PN sequence number
364  			check
365  */
366  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
367  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24
368  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000
369  
370  /* Description		RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID
371  
372  			When set, OLE found a valid SA entry for all MSDUs in
373  			this MPDU
374  
375  			<legal all>
376  */
377  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
378  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB  25
379  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000
380  
381  /* Description		RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
382  
383  			When set, at least 1 MSDU within the MPDU has an
384  			unsuccessful MAC source address search due to the expiration
385  			of the search timer.
386  
387  			<legal all>
388  */
389  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008
390  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26
391  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000
392  
393  /* Description		RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID
394  
395  			When set, OLE found a valid DA entry for all MSDUs in
396  			this MPDU
397  
398  			<legal all>
399  */
400  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
401  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB  27
402  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000
403  
404  /* Description		RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC
405  
406  			Field Only valid if da_is_valid is set
407  
408  
409  
410  			When set, at least one of the DA addresses is a
411  			Multicast or Broadcast address.
412  
413  			<legal all>
414  */
415  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
416  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB   28
417  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK  0x10000000
418  
419  /* Description		RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
420  
421  			When set, at least 1 MSDU within the MPDU has an
422  			unsuccessful MAC destination address search due to the
423  			expiration of the search timer.
424  
425  			<legal all>
426  */
427  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008
428  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29
429  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000
430  
431  /* Description		RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU
432  
433  			Field only valid when first_msdu_in_mpdu_flag is set.
434  
435  
436  
437  			When set, the contents in the MSDU buffer contains a
438  			'RAW' MPDU. This 'RAW' MPDU might be spread out over
439  			multiple MSDU buffers.
440  
441  			<legal all>
442  */
443  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET  0x00000008
444  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB     30
445  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK    0x40000000
446  
447  /* Description		RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG
448  
449  			The More Fragment bit setting from the MPDU header of
450  			the received frame
451  
452  
453  
454  			<legal all>
455  */
456  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
457  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31
458  #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000
459  
460  /* Description		RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA
461  
462  			Meta data that SW has programmed in the Peer table entry
463  			of the transmitting STA.
464  
465  			<legal all>
466  */
467  #define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
468  #define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
469  #define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
470  
471  
472  #endif // _RX_MPDU_DETAILS_H_
473