1 /* 2 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RXPCU_PPDU_END_INFO_H_ 18 #define _RXPCU_PPDU_END_INFO_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "phyrx_abort_request_info.h" 23 #include "macrx_abort_request_info.h" 24 25 // ################ START SUMMARY ################# 26 // 27 // Dword Fields 28 // 0 wb_timestamp_lower_32[31:0] 29 // 1 wb_timestamp_upper_32[31:0] 30 // 2 rx_antenna[23:0], tx_ht_vht_ack[24], unsupported_mu_nc[25], otp_txbf_disable[26], previous_tlv_corrupted[27], phyrx_abort_request_info_valid[28], macrx_abort_request_info_valid[29], reserved[31:30] 31 // 3 coex_bt_tx_from_start_of_rx[0], coex_bt_tx_after_start_of_rx[1], coex_wan_tx_from_start_of_rx[2], coex_wan_tx_after_start_of_rx[3], coex_wlan_tx_from_start_of_rx[4], coex_wlan_tx_after_start_of_rx[5], mpdu_delimiter_errors_seen[6], ftm_tm[8:7], dialog_token[16:9], follow_up_dialog_token[24:17], bb_captured_channel[25], bb_captured_reason[28:26], bb_captured_timeout[29], reserved_3[31:30] 32 // 4 before_mpdu_count_passing_fcs[9:0], before_mpdu_count_failing_fcs[19:10], after_mpdu_count_passing_fcs[29:20], reserved_4[31:30] 33 // 5 after_mpdu_count_failing_fcs[9:0], reserved_5[31:10] 34 // 6 phy_timestamp_tx_lower_32[31:0] 35 // 7 phy_timestamp_tx_upper_32[31:0] 36 // 8 bb_length[15:0], bb_data[16], reserved_8[19:17], first_bt_broadcast_status_details[31:20] 37 // 9 rx_ppdu_duration[23:0], reserved_9[31:24] 38 // 10 ast_index[15:0], ast_index_valid[16], reserved_10[19:17], second_bt_broadcast_status_details[31:20] 39 // 11 struct phyrx_abort_request_info phyrx_abort_request_info_details; 40 // 12 struct macrx_abort_request_info macrx_abort_request_info_details; 41 // 13 rx_ppdu_end_marker[31:0] 42 // 43 // ################ END SUMMARY ################# 44 45 #define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 14 46 47 struct rxpcu_ppdu_end_info { 48 uint32_t wb_timestamp_lower_32 : 32; //[31:0] 49 uint32_t wb_timestamp_upper_32 : 32; //[31:0] 50 uint32_t rx_antenna : 24, //[23:0] 51 tx_ht_vht_ack : 1, //[24] 52 unsupported_mu_nc : 1, //[25] 53 otp_txbf_disable : 1, //[26] 54 previous_tlv_corrupted : 1, //[27] 55 phyrx_abort_request_info_valid : 1, //[28] 56 macrx_abort_request_info_valid : 1, //[29] 57 reserved : 2; //[31:30] 58 uint32_t coex_bt_tx_from_start_of_rx : 1, //[0] 59 coex_bt_tx_after_start_of_rx : 1, //[1] 60 coex_wan_tx_from_start_of_rx : 1, //[2] 61 coex_wan_tx_after_start_of_rx : 1, //[3] 62 coex_wlan_tx_from_start_of_rx : 1, //[4] 63 coex_wlan_tx_after_start_of_rx : 1, //[5] 64 mpdu_delimiter_errors_seen : 1, //[6] 65 ftm_tm : 2, //[8:7] 66 dialog_token : 8, //[16:9] 67 follow_up_dialog_token : 8, //[24:17] 68 bb_captured_channel : 1, //[25] 69 bb_captured_reason : 3, //[28:26] 70 bb_captured_timeout : 1, //[29] 71 reserved_3 : 2; //[31:30] 72 uint32_t before_mpdu_count_passing_fcs : 10, //[9:0] 73 before_mpdu_count_failing_fcs : 10, //[19:10] 74 after_mpdu_count_passing_fcs : 10, //[29:20] 75 reserved_4 : 2; //[31:30] 76 uint32_t after_mpdu_count_failing_fcs : 10, //[9:0] 77 reserved_5 : 22; //[31:10] 78 uint32_t phy_timestamp_tx_lower_32 : 32; //[31:0] 79 uint32_t phy_timestamp_tx_upper_32 : 32; //[31:0] 80 uint32_t bb_length : 16, //[15:0] 81 bb_data : 1, //[16] 82 reserved_8 : 3, //[19:17] 83 first_bt_broadcast_status_details: 12; //[31:20] 84 uint32_t rx_ppdu_duration : 24, //[23:0] 85 reserved_9 : 8; //[31:24] 86 uint32_t ast_index : 16, //[15:0] 87 ast_index_valid : 1, //[16] 88 reserved_10 : 3, //[19:17] 89 second_bt_broadcast_status_details: 12; //[31:20] 90 struct phyrx_abort_request_info phyrx_abort_request_info_details; 91 struct macrx_abort_request_info macrx_abort_request_info_details; 92 uint16_t pre_bt_broadcast_status_details : 12, //[27:16] 93 reserved_12a : 4; //[31:28] 94 uint32_t rx_ppdu_end_marker : 32; //[31:0] 95 }; 96 97 /* 98 99 wb_timestamp_lower_32 100 101 WLAN/BT timestamp is a 1 usec resolution timestamp which 102 does not get updated based on receive beacon like TSF. The 103 same rules for capturing tsf_timestamp are used to capture 104 the wb_timestamp. This field represents the lower 32 bits of 105 the 64-bit timestamp 106 107 wb_timestamp_upper_32 108 109 WLAN/BT timestamp is a 1 usec resolution timestamp which 110 does not get updated based on receive beacon like TSF. The 111 same rules for capturing tsf_timestamp are used to capture 112 the wb_timestamp. This field represents the upper 32 bits of 113 the 64-bit timestamp 114 115 rx_antenna 116 117 Receive antenna value ??? 118 119 tx_ht_vht_ack 120 121 Indicates that a HT or VHT Ack/BA frame was transmitted 122 in response to this receive packet. 123 124 unsupported_mu_nc 125 126 Set if MU Nc > 2 in received NDPA. 127 128 If this bit is set, even though AID and BSSID are 129 matched, MAC doesn't send tx_expect_ndp to PHY, because MU 130 Nc > 2 is not supported in Helium. 131 132 otp_txbf_disable 133 134 Set if either OTP_SUBFEE_DISABLE or OTP_TXBF_DISABLE is 135 set and if RXPU receives directed NDPA frame. Then, RXPCU 136 should not send TX_EXPECT_NDP TLV to SW but set this bit to 137 inform SW. 138 139 previous_tlv_corrupted 140 141 When set, the TLV preceding this RXPCU_END_INFO TLV 142 within the RX_PPDU_END TLV, is corrupted. Not the entire TLV 143 was received.... Likely due to an abort scenario... If abort 144 is to blame, see the abort data datastructure for details. 145 146 <legal all> 147 148 phyrx_abort_request_info_valid 149 150 When set, the PHY sent an PHYRX_ABORT_REQUEST TLV to 151 RXPCU. The abort fields embedded in this TLV contain valid 152 info. 153 154 <legal all> 155 156 macrx_abort_request_info_valid 157 158 When set, the MAC sent an MACRX_ABORT_REQUEST TLV to 159 PHYRX. The abort fields embedded in this TLV contain valid 160 info. 161 162 <legal all> 163 164 reserved 165 166 <legal 0> 167 168 coex_bt_tx_from_start_of_rx 169 170 Set when BT TX was ongoing when WLAN RX started 171 172 coex_bt_tx_after_start_of_rx 173 174 175 coex_wan_tx_from_start_of_rx 176 177 Set when WAN TX was ongoing when WLAN RX started 178 179 coex_wan_tx_after_start_of_rx 180 181 Set when WAN TX started while WLAN RX was already 182 ongoing 183 184 coex_wlan_tx_from_start_of_rx 185 186 Set when other WLAN TX was ongoing when WLAN RX started 187 188 coex_wlan_tx_after_start_of_rx 189 190 Set when other WLAN TX started while WLAN RX was already 191 ongoing 192 193 mpdu_delimiter_errors_seen 194 195 When set, MPDU delimiter errors have been detected 196 during this PPDU reception 197 198 ftm_tm 199 200 Indicate the timestamp is for the FTM or TM frame 201 202 203 204 0: non TM or FTM frame 205 206 1: FTM frame 207 208 2: TM frame 209 210 3: reserved 211 212 <legal all> 213 214 dialog_token 215 216 The dialog token in the FTM or TM frame. Only valid when 217 the FTM is set. Clear to 254 for a non-FTM frame 218 219 <legal all> 220 221 follow_up_dialog_token 222 223 The follow up dialog token in the FTM or TM frame. Only 224 valid when the FTM is set. Clear to 0 for a non-FTM frame, 225 The follow up dialog token in the FTM frame. Only valid when 226 the FTM is set. Clear to 255 for a non-FTM frame<legal all> 227 228 bb_captured_channel 229 230 Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is 231 sent to PHY, FW check it to correlate current PPDU TLVs with 232 uploaded channel information. 233 234 235 236 <legal all> 237 238 bb_captured_reason 239 240 Copy capture_reason of MACRX_FREEZE_CAPTURE_CHANNEL TLV 241 to here for FW usage. Valid when bb_captured_channel or 242 bb_captured_timeout is set. 243 244 245 246 This field indicates why the MAC asked to capture the 247 channel 248 249 <enum 0 freeze_reason_TM> 250 251 <enum 1 freeze_reason_FTM> 252 253 <enum 2 freeze_reason_ACK_resp_to_TM_FTM> 254 255 <enum 3 freeze_reason_TA_RA_TYPE_FILTER> 256 257 <enum 4 freeze_reason_NDPA_NDP> 258 259 <enum 5 freeze_reason_ALL_PACKET> 260 261 262 263 <legal 0-5> 264 265 bb_captured_timeout 266 267 Set by RxPCU to indicate channel capture condition is 268 meet, but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY 269 due to AST long delay, which means the rx_frame_falling edge 270 to FREEZE TLV ready time exceed the threshold time defined 271 by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH. 272 273 Bb_captured_reason is still valid in this case. 274 275 276 277 <legal all> 278 279 reserved_3 280 281 <legal 0> 282 283 before_mpdu_count_passing_fcs 284 285 Number of MPDUs received in this PPDU that passed the 286 FCS check before the Coex TX started 287 288 289 290 The counter saturates at 0x3FF. 291 292 <legal all> 293 294 before_mpdu_count_failing_fcs 295 296 Number of MPDUs received in this PPDU that failed the 297 FCS check before the Coex TX started 298 299 300 301 The counter saturates at 0x3FF. 302 303 <legal all> 304 305 after_mpdu_count_passing_fcs 306 307 Number of MPDUs received in this PPDU that passed the 308 FCS check after the moment the Coex TX started 309 310 311 312 (Note: The partially received MPDU when the COEX tx 313 start event came in falls in the after category) 314 315 316 317 The counter saturates at 0x3FF. 318 319 <legal all> 320 321 reserved_4 322 323 <legal 0> 324 325 after_mpdu_count_failing_fcs 326 327 Number of MPDUs received in this PPDU that failed the 328 FCS check after the moment the Coex TX started 329 330 331 332 (Note: The partially received MPDU when the COEX tx 333 start event came in falls in the after category) 334 335 336 337 The counter saturates at 0x3FF. 338 339 <legal all> 340 341 reserved_5 342 343 <legal 0> 344 345 phy_timestamp_tx_lower_32 346 347 The PHY timestamp in the AMPI of the most recent rising 348 edge (TODO: of what ???) after the TX_PHY_DESC. This field 349 indicates the lower 32 bits of the timestamp 350 351 phy_timestamp_tx_upper_32 352 353 The PHY timestamp in the AMPI of the most recent rising 354 edge (TODO: of what ???) after the TX_PHY_DESC. This field 355 indicates the upper 32 bits of the timestamp 356 357 bb_length 358 359 Indicates the number of bytes of baseband information 360 for PPDUs where the BB descriptor preamble type is 0x80 to 361 0xFF which indicates that this is not a normal PPDU but 362 rather contains baseband debug information. 363 364 TODO: Is this still needed ??? 365 366 bb_data 367 368 Indicates that BB data associated with this PPDU will 369 exist in the receive buffer. The exact contents of this BB 370 data can be found by decoding the BB TLV in the buffer 371 associated with the BB data. See vector_fragment in the 372 Helium_mac_phy_interface.docx 373 374 reserved_8 375 376 Reserved: HW should fill with 0, FW should ignore. 377 378 first_bt_broadcast_status_details 379 380 Same contents as field bt_broadcast_status_details for 381 the first received COEX_STATUS_BROADCAST tlv during this 382 PPDU reception. 383 384 385 386 If no COEX_STATUS_BROADCAST tlv is received during this 387 PPDU reception, this field will be set to 0 388 389 390 391 392 393 For detailed info see doc: TBD 394 395 <legal all> 396 397 rx_ppdu_duration 398 399 The length of this PPDU reception in us 400 401 reserved_9 402 403 <legal 0> 404 405 ast_index 406 407 The AST index of the receive Ack/BA. This information 408 is provided from the TXPCU to the RXPCU for receive Ack/BA 409 for implicit beamforming. 410 411 <legal all> 412 413 ast_index_valid 414 415 Indicates that ast_index is valid. Should only be set 416 for receive Ack/BA where single stream implicit sounding is 417 captured. 418 419 reserved_10 420 421 <legal 0> 422 423 second_bt_broadcast_status_details 424 425 Same contents as field bt_broadcast_status_details for 426 the second received COEX_STATUS_BROADCAST tlv during this 427 PPDU reception. 428 429 430 431 If no second COEX_STATUS_BROADCAST tlv is received 432 during this PPDU reception, this field will be set to 0 433 434 435 436 437 438 For detailed info see doc: TBD 439 440 <legal all> 441 442 struct phyrx_abort_request_info phyrx_abort_request_info_details 443 444 Field only valid when Phyrx_abort_request_info_valid is 445 set 446 447 The reason why PHY generated an abort request 448 449 struct macrx_abort_request_info macrx_abort_request_info_details 450 451 Field only valid when macrx_abort_request_info_valid is 452 set 453 454 The reason why MACRX generated an abort request 455 456 rx_ppdu_end_marker 457 458 Field used by SW to double check that their structure 459 alignment is in sync with what HW has done. 460 461 <legal 0xAABBCCDD> 462 */ 463 464 465 /* Description RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32 466 467 WLAN/BT timestamp is a 1 usec resolution timestamp which 468 does not get updated based on receive beacon like TSF. The 469 same rules for capturing tsf_timestamp are used to capture 470 the wb_timestamp. This field represents the lower 32 bits of 471 the 64-bit timestamp 472 */ 473 #define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_OFFSET 0x00000000 474 #define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_LSB 0 475 #define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_MASK 0xffffffff 476 477 /* Description RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32 478 479 WLAN/BT timestamp is a 1 usec resolution timestamp which 480 does not get updated based on receive beacon like TSF. The 481 same rules for capturing tsf_timestamp are used to capture 482 the wb_timestamp. This field represents the upper 32 bits of 483 the 64-bit timestamp 484 */ 485 #define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_OFFSET 0x00000004 486 #define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_LSB 0 487 #define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff 488 489 /* Description RXPCU_PPDU_END_INFO_2_RX_ANTENNA 490 491 Receive antenna value ??? 492 */ 493 #define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_OFFSET 0x00000008 494 #define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_LSB 0 495 #define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_MASK 0x00ffffff 496 497 /* Description RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK 498 499 Indicates that a HT or VHT Ack/BA frame was transmitted 500 in response to this receive packet. 501 */ 502 #define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_OFFSET 0x00000008 503 #define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_LSB 24 504 #define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_MASK 0x01000000 505 506 /* Description RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC 507 508 Set if MU Nc > 2 in received NDPA. 509 510 If this bit is set, even though AID and BSSID are 511 matched, MAC doesn't send tx_expect_ndp to PHY, because MU 512 Nc > 2 is not supported in Helium. 513 */ 514 #define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_OFFSET 0x00000008 515 #define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_LSB 25 516 #define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_MASK 0x02000000 517 518 /* Description RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE 519 520 Set if either OTP_SUBFEE_DISABLE or OTP_TXBF_DISABLE is 521 set and if RXPU receives directed NDPA frame. Then, RXPCU 522 should not send TX_EXPECT_NDP TLV to SW but set this bit to 523 inform SW. 524 */ 525 #define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_OFFSET 0x00000008 526 #define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_LSB 26 527 #define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_MASK 0x04000000 528 529 /* Description RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED 530 531 When set, the TLV preceding this RXPCU_END_INFO TLV 532 within the RX_PPDU_END TLV, is corrupted. Not the entire TLV 533 was received.... Likely due to an abort scenario... If abort 534 is to blame, see the abort data datastructure for details. 535 536 <legal all> 537 */ 538 #define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_OFFSET 0x00000008 539 #define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_LSB 27 540 #define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_MASK 0x08000000 541 542 /* Description RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID 543 544 When set, the PHY sent an PHYRX_ABORT_REQUEST TLV to 545 RXPCU. The abort fields embedded in this TLV contain valid 546 info. 547 548 <legal all> 549 */ 550 #define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 551 #define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 552 #define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x10000000 553 554 /* Description RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID 555 556 When set, the MAC sent an MACRX_ABORT_REQUEST TLV to 557 PHYRX. The abort fields embedded in this TLV contain valid 558 info. 559 560 <legal all> 561 */ 562 #define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 563 #define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 564 #define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x20000000 565 566 /* Description RXPCU_PPDU_END_INFO_2_RESERVED 567 568 <legal 0> 569 */ 570 #define RXPCU_PPDU_END_INFO_2_RESERVED_OFFSET 0x00000008 571 #define RXPCU_PPDU_END_INFO_2_RESERVED_LSB 30 572 #define RXPCU_PPDU_END_INFO_2_RESERVED_MASK 0xc0000000 573 574 /* Description RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX 575 576 Set when BT TX was ongoing when WLAN RX started 577 */ 578 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000c 579 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_LSB 0 580 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_MASK 0x00000001 581 582 /* Description RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX 583 584 */ 585 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000c 586 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_LSB 1 587 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x00000002 588 589 /* Description RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX 590 591 Set when WAN TX was ongoing when WLAN RX started 592 */ 593 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c 594 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_LSB 2 595 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x00000004 596 597 /* Description RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX 598 599 Set when WAN TX started while WLAN RX was already 600 ongoing 601 */ 602 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c 603 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_LSB 3 604 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x00000008 605 606 /* Description RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX 607 608 Set when other WLAN TX was ongoing when WLAN RX started 609 */ 610 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c 611 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_LSB 4 612 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x00000010 613 614 /* Description RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX 615 616 Set when other WLAN TX started while WLAN RX was already 617 ongoing 618 */ 619 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c 620 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 5 621 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x00000020 622 623 /* Description RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN 624 625 When set, MPDU delimiter errors have been detected 626 during this PPDU reception 627 */ 628 #define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000c 629 #define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_LSB 6 630 #define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x00000040 631 632 /* Description RXPCU_PPDU_END_INFO_3_FTM_TM 633 634 Indicate the timestamp is for the FTM or TM frame 635 636 637 638 0: non TM or FTM frame 639 640 1: FTM frame 641 642 2: TM frame 643 644 3: reserved 645 646 <legal all> 647 */ 648 #define RXPCU_PPDU_END_INFO_3_FTM_TM_OFFSET 0x0000000c 649 #define RXPCU_PPDU_END_INFO_3_FTM_TM_LSB 7 650 #define RXPCU_PPDU_END_INFO_3_FTM_TM_MASK 0x00000180 651 652 /* Description RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN 653 654 The dialog token in the FTM or TM frame. Only valid when 655 the FTM is set. Clear to 254 for a non-FTM frame 656 657 <legal all> 658 */ 659 #define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_OFFSET 0x0000000c 660 #define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_LSB 9 661 #define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_MASK 0x0001fe00 662 663 /* Description RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN 664 665 The follow up dialog token in the FTM or TM frame. Only 666 valid when the FTM is set. Clear to 0 for a non-FTM frame, 667 The follow up dialog token in the FTM frame. Only valid when 668 the FTM is set. Clear to 255 for a non-FTM frame<legal all> 669 */ 670 #define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000c 671 #define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_LSB 17 672 #define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe0000 673 674 /* Description RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL 675 676 Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is 677 sent to PHY, FW check it to correlate current PPDU TLVs with 678 uploaded channel information. 679 680 681 682 <legal all> 683 */ 684 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_OFFSET 0x0000000c 685 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_LSB 25 686 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_MASK 0x02000000 687 688 /* Description RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON 689 690 Copy capture_reason of MACRX_FREEZE_CAPTURE_CHANNEL TLV 691 to here for FW usage. Valid when bb_captured_channel or 692 bb_captured_timeout is set. 693 694 695 696 This field indicates why the MAC asked to capture the 697 channel 698 699 <enum 0 freeze_reason_TM> 700 701 <enum 1 freeze_reason_FTM> 702 703 <enum 2 freeze_reason_ACK_resp_to_TM_FTM> 704 705 <enum 3 freeze_reason_TA_RA_TYPE_FILTER> 706 707 <enum 4 freeze_reason_NDPA_NDP> 708 709 <enum 5 freeze_reason_ALL_PACKET> 710 711 712 713 <legal 0-5> 714 */ 715 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_OFFSET 0x0000000c 716 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_LSB 26 717 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_MASK 0x1c000000 718 719 /* Description RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT 720 721 Set by RxPCU to indicate channel capture condition is 722 meet, but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY 723 due to AST long delay, which means the rx_frame_falling edge 724 to FREEZE TLV ready time exceed the threshold time defined 725 by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH. 726 727 Bb_captured_reason is still valid in this case. 728 729 730 731 <legal all> 732 */ 733 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000c 734 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_LSB 29 735 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_MASK 0x20000000 736 737 /* Description RXPCU_PPDU_END_INFO_3_RESERVED_3 738 739 <legal 0> 740 */ 741 #define RXPCU_PPDU_END_INFO_3_RESERVED_3_OFFSET 0x0000000c 742 #define RXPCU_PPDU_END_INFO_3_RESERVED_3_LSB 30 743 #define RXPCU_PPDU_END_INFO_3_RESERVED_3_MASK 0xc0000000 744 745 /* Description RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS 746 747 Number of MPDUs received in this PPDU that passed the 748 FCS check before the Coex TX started 749 750 751 752 The counter saturates at 0x3FF. 753 754 <legal all> 755 */ 756 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 757 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 758 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x000003ff 759 760 /* Description RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS 761 762 Number of MPDUs received in this PPDU that failed the 763 FCS check before the Coex TX started 764 765 766 767 The counter saturates at 0x3FF. 768 769 <legal all> 770 */ 771 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000010 772 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 773 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x000ffc00 774 775 /* Description RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS 776 777 Number of MPDUs received in this PPDU that passed the 778 FCS check after the moment the Coex TX started 779 780 781 782 (Note: The partially received MPDU when the COEX tx 783 start event came in falls in the after category) 784 785 786 787 The counter saturates at 0x3FF. 788 789 <legal all> 790 */ 791 #define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 792 #define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 793 #define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x3ff00000 794 795 /* Description RXPCU_PPDU_END_INFO_4_RESERVED_4 796 797 <legal 0> 798 */ 799 #define RXPCU_PPDU_END_INFO_4_RESERVED_4_OFFSET 0x00000010 800 #define RXPCU_PPDU_END_INFO_4_RESERVED_4_LSB 30 801 #define RXPCU_PPDU_END_INFO_4_RESERVED_4_MASK 0xc0000000 802 803 /* Description RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS 804 805 Number of MPDUs received in this PPDU that failed the 806 FCS check after the moment the Coex TX started 807 808 809 810 (Note: The partially received MPDU when the COEX tx 811 start event came in falls in the after category) 812 813 814 815 The counter saturates at 0x3FF. 816 817 <legal all> 818 */ 819 #define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000014 820 #define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_LSB 0 821 #define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff 822 823 /* Description RXPCU_PPDU_END_INFO_5_RESERVED_5 824 825 <legal 0> 826 */ 827 #define RXPCU_PPDU_END_INFO_5_RESERVED_5_OFFSET 0x00000014 828 #define RXPCU_PPDU_END_INFO_5_RESERVED_5_LSB 10 829 #define RXPCU_PPDU_END_INFO_5_RESERVED_5_MASK 0xfffffc00 830 831 /* Description RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32 832 833 The PHY timestamp in the AMPI of the most recent rising 834 edge (TODO: of what ???) after the TX_PHY_DESC. This field 835 indicates the lower 32 bits of the timestamp 836 */ 837 #define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x00000018 838 #define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 839 #define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_MASK 0xffffffff 840 841 /* Description RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32 842 843 The PHY timestamp in the AMPI of the most recent rising 844 edge (TODO: of what ???) after the TX_PHY_DESC. This field 845 indicates the upper 32 bits of the timestamp 846 */ 847 #define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000001c 848 #define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_LSB 0 849 #define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff 850 851 /* Description RXPCU_PPDU_END_INFO_8_BB_LENGTH 852 853 Indicates the number of bytes of baseband information 854 for PPDUs where the BB descriptor preamble type is 0x80 to 855 0xFF which indicates that this is not a normal PPDU but 856 rather contains baseband debug information. 857 858 TODO: Is this still needed ??? 859 */ 860 #define RXPCU_PPDU_END_INFO_8_BB_LENGTH_OFFSET 0x00000020 861 #define RXPCU_PPDU_END_INFO_8_BB_LENGTH_LSB 0 862 #define RXPCU_PPDU_END_INFO_8_BB_LENGTH_MASK 0x0000ffff 863 864 /* Description RXPCU_PPDU_END_INFO_8_BB_DATA 865 866 Indicates that BB data associated with this PPDU will 867 exist in the receive buffer. The exact contents of this BB 868 data can be found by decoding the BB TLV in the buffer 869 associated with the BB data. See vector_fragment in the 870 Helium_mac_phy_interface.docx 871 */ 872 #define RXPCU_PPDU_END_INFO_8_BB_DATA_OFFSET 0x00000020 873 #define RXPCU_PPDU_END_INFO_8_BB_DATA_LSB 16 874 #define RXPCU_PPDU_END_INFO_8_BB_DATA_MASK 0x00010000 875 876 /* Description RXPCU_PPDU_END_INFO_8_RESERVED_8 877 878 Reserved: HW should fill with 0, FW should ignore. 879 */ 880 #define RXPCU_PPDU_END_INFO_8_RESERVED_8_OFFSET 0x00000020 881 #define RXPCU_PPDU_END_INFO_8_RESERVED_8_LSB 17 882 #define RXPCU_PPDU_END_INFO_8_RESERVED_8_MASK 0x000e0000 883 884 /* Description RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS 885 886 Same contents as field bt_broadcast_status_details for 887 the first received COEX_STATUS_BROADCAST tlv during this 888 PPDU reception. 889 890 891 892 If no COEX_STATUS_BROADCAST tlv is received during this 893 PPDU reception, this field will be set to 0 894 895 896 897 898 899 For detailed info see doc: TBD 900 901 <legal all> 902 */ 903 #define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000020 904 #define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 905 #define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 906 907 /* Description RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION 908 909 The length of this PPDU reception in us 910 */ 911 #define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 0x00000024 912 #define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 0 913 #define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 0x00ffffff 914 915 /* Description RXPCU_PPDU_END_INFO_9_RESERVED_9 916 917 <legal 0> 918 */ 919 #define RXPCU_PPDU_END_INFO_9_RESERVED_9_OFFSET 0x00000024 920 #define RXPCU_PPDU_END_INFO_9_RESERVED_9_LSB 24 921 #define RXPCU_PPDU_END_INFO_9_RESERVED_9_MASK 0xff000000 922 923 /* Description RXPCU_PPDU_END_INFO_10_AST_INDEX 924 925 The AST index of the receive Ack/BA. This information 926 is provided from the TXPCU to the RXPCU for receive Ack/BA 927 for implicit beamforming. 928 929 <legal all> 930 */ 931 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_OFFSET 0x00000028 932 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_LSB 0 933 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_MASK 0x0000ffff 934 935 /* Description RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID 936 937 Indicates that ast_index is valid. Should only be set 938 for receive Ack/BA where single stream implicit sounding is 939 captured. 940 */ 941 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_OFFSET 0x00000028 942 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_LSB 16 943 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_MASK 0x00010000 944 945 /* Description RXPCU_PPDU_END_INFO_10_RESERVED_10 946 947 <legal 0> 948 */ 949 #define RXPCU_PPDU_END_INFO_10_RESERVED_10_OFFSET 0x00000028 950 #define RXPCU_PPDU_END_INFO_10_RESERVED_10_LSB 17 951 #define RXPCU_PPDU_END_INFO_10_RESERVED_10_MASK 0x000e0000 952 953 /* Description RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS 954 955 Same contents as field bt_broadcast_status_details for 956 the second received COEX_STATUS_BROADCAST tlv during this 957 PPDU reception. 958 959 960 961 If no second COEX_STATUS_BROADCAST tlv is received 962 during this PPDU reception, this field will be set to 0 963 964 965 966 967 968 For detailed info see doc: TBD 969 970 <legal all> 971 */ 972 #define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000028 973 #define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 974 #define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 975 976 /* EXTERNAL REFERENCE : struct phyrx_abort_request_info phyrx_abort_request_info_details */ 977 978 979 /* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON 980 981 <enum 0 phyrx_err_phy_off> Reception aborted due to 982 receiving a PHY_OFF TLV 983 984 <enum 1 phyrx_err_synth_off> 985 986 <enum 2 phyrx_err_ofdma_timing> 987 988 <enum 3 phyrx_err_ofdma_signal_parity> 989 990 <enum 4 phyrx_err_ofdma_rate_illegal> 991 992 <enum 5 phyrx_err_ofdma_length_illegal> 993 994 <enum 6 phyrx_err_ofdma_restart> 995 996 <enum 7 phyrx_err_ofdma_service> 997 998 <enum 8 phyrx_err_ppdu_ofdma_power_drop> 999 1000 1001 1002 <enum 9 phyrx_err_cck_blokker> 1003 1004 <enum 10 phyrx_err_cck_timing> 1005 1006 <enum 11 phyrx_err_cck_header_crc> 1007 1008 <enum 12 phyrx_err_cck_rate_illegal> 1009 1010 <enum 13 phyrx_err_cck_length_illegal> 1011 1012 <enum 14 phyrx_err_cck_restart> 1013 1014 <enum 15 phyrx_err_cck_service> 1015 1016 <enum 16 phyrx_err_cck_power_drop> 1017 1018 1019 1020 <enum 17 phyrx_err_ht_crc_err> 1021 1022 <enum 18 phyrx_err_ht_length_illegal> 1023 1024 <enum 19 phyrx_err_ht_rate_illegal> 1025 1026 <enum 20 phyrx_err_ht_zlf> 1027 1028 <enum 21 phyrx_err_false_radar_ext> 1029 1030 1031 1032 <enum 22 phyrx_err_green_field> 1033 1034 1035 1036 <enum 23 phyrx_err_bw_gt_dyn_bw> 1037 1038 <enum 24 phyrx_err_leg_ht_mismatch> 1039 1040 <enum 25 phyrx_err_vht_crc_error> 1041 1042 <enum 26 phyrx_err_vht_siga_unsupported> 1043 1044 <enum 27 phyrx_err_vht_lsig_len_invalid> 1045 1046 <enum 28 phyrx_err_vht_ndp_or_zlf> 1047 1048 <enum 29 phyrx_err_vht_nsym_lt_zero> 1049 1050 <enum 30 phyrx_err_vht_rx_extra_symbol_mismatch> 1051 1052 <enum 31 phyrx_err_vht_rx_skip_group_id0> 1053 1054 <enum 32 phyrx_err_vht_rx_skip_group_id1to62> 1055 1056 <enum 33 phyrx_err_vht_rx_skip_group_id63> 1057 1058 <enum 34 phyrx_err_ofdm_ldpc_decoder_disabled> 1059 1060 <enum 35 phyrx_err_defer_nap> 1061 1062 <enum 36 phyrx_err_fdomain_timeout> 1063 1064 <enum 37 phyrx_err_lsig_rel_check> 1065 1066 <enum 38 phyrx_err_bt_collision> 1067 1068 <enum 39 phyrx_err_unsupported_mu_feedback> 1069 1070 <enum 40 phyrx_err_ppdu_tx_interrupt_rx> 1071 1072 <enum 41 phyrx_err_unsupported_cbf> 1073 1074 1075 1076 <enum 42 phyrx_err_other> Should not really be used. If 1077 needed, ask for documentation update 1078 1079 1080 1081 <enum 43 phyrx_err_he_siga_unsupported > <enum 44 1082 phyrx_err_he_crc_error > <enum 45 1083 phyrx_err_he_sigb_unsupported > <enum 46 1084 phyrx_err_he_mu_mode_unsupported > <enum 47 1085 phyrx_err_he_ndp_or_zlf > <enum 48 phyrx_err_he_nsym_lt_zero 1086 > <enum 49 phyrx_err_he_ru_params_unsupported > <enum 50 1087 phyrx_err_he_num_users_unsupported ><enum 51 1088 phyrx_err_he_sounding_params_unsupported > 1089 1090 1091 1092 <enum 52 phyrx_err_MU_UL_no_power_detected> 1093 1094 <enum 53 phyrx_err_MU_UL_not_for_me> 1095 1096 1097 1098 <legal 0 - 53> 1099 */ 1100 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000002c 1101 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 0 1102 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff 1103 1104 /* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE 1105 1106 When set, PHY enters PHY NAP state after sending this 1107 abort 1108 1109 1110 1111 Note that nap and defer state are mutually exclusive. 1112 1113 1114 1115 Field put pro-actively in place....usage still to be 1116 agreed upon. 1117 1118 <legal all> 1119 */ 1120 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000002c 1121 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 8 1122 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x00000100 1123 1124 /* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE 1125 1126 When set, PHY enters PHY defer state after sending this 1127 abort 1128 1129 1130 1131 Note that nap and defer state are mutually exclusive. 1132 1133 1134 1135 Field put pro-actively in place....usage still to be 1136 agreed upon. 1137 1138 <legal all> 1139 */ 1140 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000002c 1141 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 9 1142 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 1143 1144 /* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0 1145 1146 <legal 0> 1147 */ 1148 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000002c 1149 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 10 1150 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000fc00 1151 1152 /* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION 1153 1154 The remaining receive duration of this PPDU in the 1155 medium (in us). When PHY does not know this duration when 1156 this TLV is generated, the field will be set to 0. 1157 1158 The timing reference point is the reception by the MAC 1159 of this TLV. The value shall be accurate to within 2us. 1160 1161 1162 1163 In case Phy_enters_nap_state and/or 1164 Phy_enters_defer_state is set, there is a possibility that 1165 MAC PMM can also decide to go into a low(er) power state. 1166 1167 <legal all> 1168 */ 1169 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000002c 1170 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 16 1171 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff0000 1172 1173 /* EXTERNAL REFERENCE : struct macrx_abort_request_info macrx_abort_request_info_details */ 1174 1175 1176 /* Description RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON 1177 1178 <enum 0 macrx_abort_sw_initiated> 1179 1180 <enum 1 macrx_abort_obss_reception> Upon receiving this 1181 abort reason, PHY should stop reception of the current frame 1182 and go back into a search mode 1183 1184 <enum 2 macrx_abort_other> 1185 1186 <enum 3 macrx_abort_sw_initiated_channel_switch > MAC FW 1187 issued an abort for channel switch reasons 1188 1189 <enum 4 macrx_abort_sw_initiated_power_save > MAC FW 1190 issued an abort power save reasons 1191 1192 <enum 5 macrx_abort_too_much_bad_data > RXPCU is 1193 terminating the current ongoing reception, as the data that 1194 MAC is receiving seems to be all garbage... The PER is too 1195 high, or in case of MU UL, Likely the trigger frame never 1196 got properly received by any of the targeted MU UL devices. 1197 After the abort, PHYRX can resume a normal search mode. 1198 1199 1200 1201 <legal 0-5> 1202 */ 1203 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x00000030 1204 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 1205 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x000000ff 1206 1207 /* Description RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0 1208 1209 <legal 0> 1210 */ 1211 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x00000030 1212 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 1213 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000ff00 1214 1215 /* Description RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER 1216 1217 Field used by SW to double check that their structure 1218 alignment is in sync with what HW has done. 1219 1220 <legal 0xAABBCCDD> 1221 */ 1222 #define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_OFFSET 0x00000034 1223 #define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_LSB 0 1224 #define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_MASK 0xffffffff 1225 1226 1227 #endif // _RXPCU_PPDU_END_INFO_H_ 1228