1 /* 2 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_REO_QUEUE_H_ 18 #define _RX_REO_QUEUE_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "uniform_descriptor_header.h" 23 24 // ################ START SUMMARY ################# 25 // 26 // Dword Fields 27 // 0 struct uniform_descriptor_header descriptor_header; 28 // 1 receive_queue_number[15:0], reserved_1b[31:16] 29 // 2 vld[0], associated_link_descriptor_counter[2:1], disable_duplicate_detection[3], soft_reorder_enable[4], ac[6:5], bar[7], rty[8], chk_2k_mode[9], oor_mode[10], ba_window_size[18:11], pn_check_needed[19], pn_shall_be_even[20], pn_shall_be_uneven[21], pn_handling_enable[22], pn_size[24:23], ignore_ampdu_flag[25], reserved_2b[31:26] 30 // 3 svld[0], ssn[12:1], current_index[20:13], seq_2k_error_detected_flag[21], pn_error_detected_flag[22], reserved_3a[30:23], pn_valid[31] 31 // 4 pn_31_0[31:0] 32 // 5 pn_63_32[31:0] 33 // 6 pn_95_64[31:0] 34 // 7 pn_127_96[31:0] 35 // 8 last_rx_enqueue_timestamp[31:0] 36 // 9 last_rx_dequeue_timestamp[31:0] 37 // 10 ptr_to_next_aging_queue_31_0[31:0] 38 // 11 ptr_to_next_aging_queue_39_32[7:0], reserved_11a[31:8] 39 // 12 ptr_to_previous_aging_queue_31_0[31:0] 40 // 13 ptr_to_previous_aging_queue_39_32[7:0], reserved_13a[31:8] 41 // 14 rx_bitmap_31_0[31:0] 42 // 15 rx_bitmap_63_32[31:0] 43 // 16 rx_bitmap_95_64[31:0] 44 // 17 rx_bitmap_127_96[31:0] 45 // 18 rx_bitmap_159_128[31:0] 46 // 19 rx_bitmap_191_160[31:0] 47 // 20 rx_bitmap_223_192[31:0] 48 // 21 rx_bitmap_255_224[31:0] 49 // 22 current_mpdu_count[6:0], current_msdu_count[31:7] 50 // 23 reserved_23[3:0], timeout_count[9:4], forward_due_to_bar_count[15:10], duplicate_count[31:16] 51 // 24 frames_in_order_count[23:0], bar_received_count[31:24] 52 // 25 mpdu_frames_processed_count[31:0] 53 // 26 msdu_frames_processed_count[31:0] 54 // 27 total_processed_byte_count[31:0] 55 // 28 late_receive_mpdu_count[11:0], window_jump_2k[15:12], hole_count[31:16] 56 // 29 reserved_29[31:0] 57 // 30 reserved_30[31:0] 58 // 31 reserved_31[31:0] 59 // 60 // ################ END SUMMARY ################# 61 62 #define NUM_OF_DWORDS_RX_REO_QUEUE 32 63 64 struct rx_reo_queue { 65 struct uniform_descriptor_header descriptor_header; 66 uint32_t receive_queue_number : 16, //[15:0] 67 reserved_1b : 16; //[31:16] 68 uint32_t vld : 1, //[0] 69 associated_link_descriptor_counter: 2, //[2:1] 70 disable_duplicate_detection : 1, //[3] 71 soft_reorder_enable : 1, //[4] 72 ac : 2, //[6:5] 73 bar : 1, //[7] 74 rty : 1, //[8] 75 chk_2k_mode : 1, //[9] 76 oor_mode : 1, //[10] 77 ba_window_size : 8, //[18:11] 78 pn_check_needed : 1, //[19] 79 pn_shall_be_even : 1, //[20] 80 pn_shall_be_uneven : 1, //[21] 81 pn_handling_enable : 1, //[22] 82 pn_size : 2, //[24:23] 83 ignore_ampdu_flag : 1, //[25] 84 reserved_2b : 6; //[31:26] 85 uint32_t svld : 1, //[0] 86 ssn : 12, //[12:1] 87 current_index : 8, //[20:13] 88 seq_2k_error_detected_flag : 1, //[21] 89 pn_error_detected_flag : 1, //[22] 90 reserved_3a : 8, //[30:23] 91 pn_valid : 1; //[31] 92 uint32_t pn_31_0 : 32; //[31:0] 93 uint32_t pn_63_32 : 32; //[31:0] 94 uint32_t pn_95_64 : 32; //[31:0] 95 uint32_t pn_127_96 : 32; //[31:0] 96 uint32_t last_rx_enqueue_timestamp : 32; //[31:0] 97 uint32_t last_rx_dequeue_timestamp : 32; //[31:0] 98 uint32_t ptr_to_next_aging_queue_31_0 : 32; //[31:0] 99 uint32_t ptr_to_next_aging_queue_39_32 : 8, //[7:0] 100 reserved_11a : 24; //[31:8] 101 uint32_t ptr_to_previous_aging_queue_31_0: 32; //[31:0] 102 uint32_t ptr_to_previous_aging_queue_39_32: 8, //[7:0] 103 reserved_13a : 24; //[31:8] 104 uint32_t rx_bitmap_31_0 : 32; //[31:0] 105 uint32_t rx_bitmap_63_32 : 32; //[31:0] 106 uint32_t rx_bitmap_95_64 : 32; //[31:0] 107 uint32_t rx_bitmap_127_96 : 32; //[31:0] 108 uint32_t rx_bitmap_159_128 : 32; //[31:0] 109 uint32_t rx_bitmap_191_160 : 32; //[31:0] 110 uint32_t rx_bitmap_223_192 : 32; //[31:0] 111 uint32_t rx_bitmap_255_224 : 32; //[31:0] 112 uint32_t current_mpdu_count : 7, //[6:0] 113 current_msdu_count : 25; //[31:7] 114 uint32_t reserved_23 : 4, //[3:0] 115 timeout_count : 6, //[9:4] 116 forward_due_to_bar_count : 6, //[15:10] 117 duplicate_count : 16; //[31:16] 118 uint32_t frames_in_order_count : 24, //[23:0] 119 bar_received_count : 8; //[31:24] 120 uint32_t mpdu_frames_processed_count : 32; //[31:0] 121 uint32_t msdu_frames_processed_count : 32; //[31:0] 122 uint32_t total_processed_byte_count : 32; //[31:0] 123 uint32_t late_receive_mpdu_count : 12, //[11:0] 124 window_jump_2k : 4, //[15:12] 125 hole_count : 16; //[31:16] 126 uint32_t reserved_29 : 32; //[31:0] 127 uint32_t reserved_30 : 32; //[31:0] 128 uint32_t reserved_31 : 32; //[31:0] 129 }; 130 131 /* 132 133 struct uniform_descriptor_header descriptor_header 134 135 Details about which module owns this struct. 136 137 Note that sub field Buffer_type shall be set to 138 Receive_REO_queue_descriptor 139 140 receive_queue_number 141 142 Indicates the MPDU queue ID to which this MPDU link 143 descriptor belongs 144 145 Used for tracking and debugging 146 147 <legal all> 148 149 reserved_1b 150 151 <legal 0> 152 153 vld 154 155 Valid bit indicating a session is established and the 156 queue descriptor is valid(Filled by SW) 157 158 <legal all> 159 160 associated_link_descriptor_counter 161 162 Indicates which of the 3 link descriptor counters shall 163 be incremented or decremented when link descriptors are 164 added or removed from this flow queue. 165 166 MSDU link descriptors related with MPDUs stored in the 167 re-order buffer shall also be included in this count. 168 169 170 171 <legal 0-2> 172 173 disable_duplicate_detection 174 175 When set, do not perform any duplicate detection. 176 177 178 179 <legal all> 180 181 soft_reorder_enable 182 183 When set, REO has been instructed to not perform the 184 actual re-ordering of frames for this queue, but just to 185 insert the reorder opcodes. 186 187 188 189 Note that this implies that REO is also not going to 190 perform any MSDU level operations, and the entire MPDU (and 191 thus pointer to the MSDU link descriptor) will be pushed to 192 a destination ring that SW has programmed in a SW 193 programmable configuration register in REO 194 195 196 197 <legal all> 198 199 ac 200 201 Indicates which access category the queue descriptor 202 belongs to(filled by SW) 203 204 <legal all> 205 206 bar 207 208 Indicates if BAR has been received (mostly used for 209 debug purpose and this is filled by REO) 210 211 <legal all> 212 213 rty 214 215 Retry bit is checked if this bit is set. 216 217 <legal all> 218 219 chk_2k_mode 220 221 Indicates what type of operation is expected from Reo 222 when the received frame SN falls within the 2K window 223 224 225 226 See REO MLD document for programming details. 227 228 <legal all> 229 230 oor_mode 231 232 Out of Order mode: 233 234 Indicates what type of operation is expected when the 235 received frame falls within the OOR window. 236 237 238 239 See REO MLD document for programming details. 240 241 <legal all> 242 243 ba_window_size 244 245 Indicates the negotiated (window size + 1). 246 247 It can go up to Max of 256bits. 248 249 250 251 A value 255 means 256 bitmap, 63 means 64 bitmap, 0 252 (means non-BA session, with window size of 0). The 3 values 253 here are the main values validated, but other values should 254 work as well. 255 256 257 258 A BA window size of 0 (=> one frame entry bitmat), means 259 that there is NO RX_REO_QUEUE_EXT descriptor following this 260 RX_REO_QUEUE STRUCT in memory 261 262 263 264 A BA window size of 1 - 105, means that there is 1 265 RX_REO_QUEUE_EXT descriptor directly following this 266 RX_REO_QUEUE STRUCT in memory. 267 268 269 270 A BA window size of 106 - 210, means that there are 2 271 RX_REO_QUEUE_EXT descriptors directly following this 272 RX_REO_QUEUE STRUCT in memory 273 274 275 276 A BA window size of 211 - 256, means that there are 3 277 RX_REO_QUEUE_EXT descriptors directly following this 278 RX_REO_QUEUE STRUCT in memory 279 280 281 282 <legal 0 - 255> 283 284 pn_check_needed 285 286 When set, REO shall perform the PN increment check 287 288 <legal all> 289 290 pn_shall_be_even 291 292 Field only valid when 'pn_check_needed' is set. 293 294 295 296 When set, REO shall confirm that the received PN number 297 is not only incremented, but also always an even number 298 299 <legal all> 300 301 pn_shall_be_uneven 302 303 Field only valid when 'pn_check_needed' is set. 304 305 306 307 When set, REO shall confirm that the received PN number 308 is not only incremented, but also always an uneven number 309 310 <legal all> 311 312 pn_handling_enable 313 314 Field only valid when 'pn_check_needed' is set. 315 316 317 318 When set, and REO detected a PN error, HW shall set the 319 'pn_error_detected_flag'. 320 321 <legal all> 322 323 pn_size 324 325 Size of the PN field check. 326 327 Needed for wrap around handling... 328 329 330 331 <enum 0 pn_size_24> 332 333 <enum 1 pn_size_48> 334 335 <enum 2 pn_size_128> 336 337 338 339 <legal 0-2> 340 341 ignore_ampdu_flag 342 343 When set, REO shall ignore the ampdu_flag on the 344 entrance descriptor for this queue. 345 346 <legal all> 347 348 reserved_2b 349 350 <legal 0> 351 352 svld 353 354 Sequence number in next field is valid one. It can be 355 filled by SW if the want to fill in the any negotiated SSN, 356 otherwise REO will fill the sequence number of first 357 received packet and set this bit to 1. 358 359 <legal all> 360 361 ssn 362 363 Starting Sequence number of the session, this changes 364 whenever window moves. (can be filled by SW then maintained 365 by REO) 366 367 <legal all> 368 369 current_index 370 371 Points to last forwarded packet 372 373 <legal all> 374 375 seq_2k_error_detected_flag 376 377 Set by REO, can only be cleared by SW 378 379 380 381 When set, REO has detected a 2k error jump in the 382 sequence number and from that moment forward, all new frames 383 are forwarded directly to FW, without duplicate detect, 384 reordering, etc. 385 386 <legal all> 387 388 pn_error_detected_flag 389 390 Set by REO, can only be cleared by SW 391 392 393 394 When set, REO has detected a PN error and from that 395 moment forward, all new frames are forwarded directly to FW, 396 without duplicate detect, reordering, etc. 397 398 <legal all> 399 400 reserved_3a 401 402 <legal 0> 403 404 pn_valid 405 406 PN number in next fields are valid. It can be filled by 407 SW if it wants to fill in the any negotiated SSN, otherwise 408 REO will fill the pn based on the first received packet and 409 set this bit to 1. 410 411 <legal all> 412 413 pn_31_0 414 415 416 <legal all> 417 418 pn_63_32 419 420 Bits [63:32] of the PN number. 421 422 <legal all> 423 424 pn_95_64 425 426 Bits [95:64] of the PN number. 427 428 <legal all> 429 430 pn_127_96 431 432 Bits [127:96] of the PN number. 433 434 <legal all> 435 436 last_rx_enqueue_timestamp 437 438 This timestamp is updated when an MPDU is received and 439 accesses this Queue Descriptor. It does not include the 440 access due to Command TLVs or Aging (which will be updated 441 in Last_rx_dequeue_timestamp). 442 443 <legal all> 444 445 last_rx_dequeue_timestamp 446 447 This timestamp is used for Aging. When an MPDU or 448 multiple MPDUs are forwarded, either due to window movement, 449 bar, aging or command flush, this timestamp is updated. Also 450 when the bitmap is all zero and the first time an MPDU is 451 queued (opcode=QCUR), this timestamp is updated for aging. 452 453 <legal all> 454 455 ptr_to_next_aging_queue_31_0 456 457 Address (address bits 31-0)of next RX_REO_QUEUE 458 descriptor in the 'receive timestamp' ordered list. 459 460 From it the Position of this queue descriptor in the per 461 AC aging waitlist can be derived. 462 463 Value 0x0 indicates the 'NULL' pointer which implies 464 that this is the last entry in the list. 465 466 <legal all> 467 468 ptr_to_next_aging_queue_39_32 469 470 Address (address bits 39-32)of next RX_REO_QUEUE 471 descriptor in the 'receive timestamp' ordered list. 472 473 From it the Position of this queue descriptor in the per 474 AC aging waitlist can be derived. 475 476 Value 0x0 indicates the 'NULL' pointer which implies 477 that this is the last entry in the list. 478 479 <legal all> 480 481 reserved_11a 482 483 <legal 0> 484 485 ptr_to_previous_aging_queue_31_0 486 487 Address (address bits 31-0)of next RX_REO_QUEUE 488 descriptor in the 'receive timestamp' ordered list. 489 490 From it the Position of this queue descriptor in the per 491 AC aging waitlist can be derived. 492 493 Value 0x0 indicates the 'NULL' pointer which implies 494 that this is the first entry in the list. 495 496 <legal all> 497 498 ptr_to_previous_aging_queue_39_32 499 500 Address (address bits 39-32)of next RX_REO_QUEUE 501 descriptor in the 'receive timestamp' ordered list. 502 503 From it the Position of this queue descriptor in the per 504 AC aging waitlist can be derived. 505 506 Value 0x0 indicates the 'NULL' pointer which implies 507 that this is the first entry in the list. 508 509 <legal all> 510 511 reserved_13a 512 513 <legal 0> 514 515 rx_bitmap_31_0 516 517 When a bit is set, the corresponding frame is currently 518 held in the re-order queue. 519 520 The bitmap is Fully managed by HW. 521 522 SW shall init this to 0, and then never ever change it 523 524 <legal all> 525 526 rx_bitmap_63_32 527 528 See Rx_bitmap_31_0 description 529 530 <legal all> 531 532 rx_bitmap_95_64 533 534 See Rx_bitmap_31_0 description 535 536 <legal all> 537 538 rx_bitmap_127_96 539 540 See Rx_bitmap_31_0 description 541 542 <legal all> 543 544 rx_bitmap_159_128 545 546 See Rx_bitmap_31_0 description 547 548 <legal all> 549 550 rx_bitmap_191_160 551 552 See Rx_bitmap_31_0 description 553 554 <legal all> 555 556 rx_bitmap_223_192 557 558 See Rx_bitmap_31_0 description 559 560 <legal all> 561 562 rx_bitmap_255_224 563 564 See Rx_bitmap_31_0 description 565 566 <legal all> 567 568 current_mpdu_count 569 570 The number of MPDUs in the queue. 571 572 573 574 <legal all> 575 576 current_msdu_count 577 578 The number of MSDUs in the queue. 579 580 <legal all> 581 582 reserved_23 583 584 <legal 0> 585 586 timeout_count 587 588 The number of times that REO started forwarding frames 589 even though there is a hole in the bitmap. Forwarding reason 590 is Timeout 591 592 593 594 The counter saturates and freezes at 0x3F 595 596 597 598 <legal all> 599 600 forward_due_to_bar_count 601 602 The number of times that REO started forwarding frames 603 even though there is a hole in the bitmap. Forwarding reason 604 is reception of BAR frame. 605 606 607 608 The counter saturates and freezes at 0x3F 609 610 611 612 <legal all> 613 614 duplicate_count 615 616 The number of duplicate frames that have been detected 617 618 <legal all> 619 620 frames_in_order_count 621 622 The number of frames that have been received in order 623 (without a hole that prevented them from being forwarded 624 immediately) 625 626 627 628 This corresponds to the Reorder opcodes: 629 630 'FWDCUR' and 'FWD BUF' 631 632 633 634 <legal all> 635 636 bar_received_count 637 638 The number of times a BAR frame is received. 639 640 641 642 This corresponds to the Reorder opcodes with 'DROP' 643 644 645 646 The counter saturates and freezes at 0xFF 647 648 <legal all> 649 650 mpdu_frames_processed_count 651 652 The total number of MPDU frames that have been processed 653 by REO. 'Processing' here means that REO has received them 654 out of the entrance ring, and retrieved the corresponding 655 RX_REO_QUEUE Descriptor. 656 657 658 659 Note that this count includes duplicates, frames that 660 later had errors, etc. 661 662 663 664 Note that field 'Duplicate_count' indicates how many of 665 these MPDUs were duplicates. 666 667 668 669 <legal all> 670 671 msdu_frames_processed_count 672 673 The total number of MSDU frames that have been processed 674 by REO. 'Processing' here means that REO has received them 675 out of the entrance ring, and retrieved the corresponding 676 RX_REO_QUEUE Descriptor. 677 678 679 680 Note that this count includes duplicates, frames that 681 later had errors, etc. 682 683 684 685 <legal all> 686 687 total_processed_byte_count 688 689 An approximation of the number of bytes processed for 690 this queue. 691 692 'Processing' here means that REO has received them out 693 of the entrance ring, and retrieved the corresponding 694 RX_REO_QUEUE Descriptor. 695 696 697 698 Note that this count includes duplicates, frames that 699 later had errors, etc. 700 701 702 703 In 64 byte units 704 705 <legal all> 706 707 late_receive_mpdu_count 708 709 The number of MPDUs received after the window had 710 already moved on. The 'late' sequence window is defined as 711 (Window SSN - 256) - (Window SSN - 1) 712 713 714 715 This corresponds with Out of order detection in 716 duplicate detect FSM 717 718 719 720 The counter saturates and freezes at 0xFFF 721 722 723 724 <legal all> 725 726 window_jump_2k 727 728 The number of times the window moved more then 2K 729 730 731 732 The counter saturates and freezes at 0xF 733 734 735 736 (Note: field name can not start with number: previous 737 2k_window_jump) 738 739 740 741 <legal all> 742 743 hole_count 744 745 The number of times a hole was created in the receive 746 bitmap. 747 748 749 750 This corresponds to the Reorder opcodes with 'QCUR' 751 752 753 754 <legal all> 755 756 reserved_29 757 758 <legal 0> 759 760 reserved_30 761 762 <legal 0> 763 764 reserved_31 765 766 <legal 0> 767 */ 768 769 770 /* EXTERNAL REFERENCE : struct uniform_descriptor_header descriptor_header */ 771 772 773 /* Description RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER 774 775 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 776 777 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 778 779 780 781 The owner of this data structure: 782 783 <enum 0 WBM_owned> Buffer Manager currently owns this 784 data structure. 785 786 <enum 1 SW_OR_FW_owned> Software of FW currently owns 787 this data structure. 788 789 <enum 2 TQM_owned> Transmit Queue Manager currently owns 790 this data structure. 791 792 <enum 3 RXDMA_owned> Receive DMA currently owns this 793 data structure. 794 795 <enum 4 REO_owned> Reorder currently owns this data 796 structure. 797 798 <enum 5 SWITCH_owned> SWITCH currently owns this data 799 structure. 800 801 802 803 <legal 0-5> 804 */ 805 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 806 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_LSB 0 807 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 808 809 /* Description RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE 810 811 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 812 813 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 814 815 816 817 Field describing what contents format is of this 818 descriptor 819 820 821 822 <enum 0 Transmit_MSDU_Link_descriptor > 823 824 <enum 1 Transmit_MPDU_Link_descriptor > 825 826 <enum 2 Transmit_MPDU_Queue_head_descriptor> 827 828 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 829 830 <enum 4 Transmit_flow_descriptor> 831 832 <enum 5 Transmit_buffer > NOT TO BE USED: 833 834 835 836 <enum 6 Receive_MSDU_Link_descriptor > 837 838 <enum 7 Receive_MPDU_Link_descriptor > 839 840 <enum 8 Receive_REO_queue_descriptor > 841 842 <enum 9 Receive_REO_queue_ext_descriptor > 843 844 845 846 <enum 10 Receive_buffer > 847 848 849 850 <enum 11 Idle_link_list_entry> 851 852 853 854 <legal 0-11> 855 */ 856 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 857 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 858 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 859 860 /* Description RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A 861 862 <legal 0> 863 */ 864 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 865 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 866 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 867 868 /* Description RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER 869 870 Indicates the MPDU queue ID to which this MPDU link 871 descriptor belongs 872 873 Used for tracking and debugging 874 875 <legal all> 876 */ 877 #define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 878 #define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_LSB 0 879 #define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff 880 881 /* Description RX_REO_QUEUE_1_RESERVED_1B 882 883 <legal 0> 884 */ 885 #define RX_REO_QUEUE_1_RESERVED_1B_OFFSET 0x00000004 886 #define RX_REO_QUEUE_1_RESERVED_1B_LSB 16 887 #define RX_REO_QUEUE_1_RESERVED_1B_MASK 0xffff0000 888 889 /* Description RX_REO_QUEUE_2_VLD 890 891 Valid bit indicating a session is established and the 892 queue descriptor is valid(Filled by SW) 893 894 <legal all> 895 */ 896 #define RX_REO_QUEUE_2_VLD_OFFSET 0x00000008 897 #define RX_REO_QUEUE_2_VLD_LSB 0 898 #define RX_REO_QUEUE_2_VLD_MASK 0x00000001 899 900 /* Description RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER 901 902 Indicates which of the 3 link descriptor counters shall 903 be incremented or decremented when link descriptors are 904 added or removed from this flow queue. 905 906 MSDU link descriptors related with MPDUs stored in the 907 re-order buffer shall also be included in this count. 908 909 910 911 <legal 0-2> 912 */ 913 #define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 914 #define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 915 #define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 916 917 /* Description RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION 918 919 When set, do not perform any duplicate detection. 920 921 922 923 <legal all> 924 */ 925 #define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 926 #define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_LSB 3 927 #define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 928 929 /* Description RX_REO_QUEUE_2_SOFT_REORDER_ENABLE 930 931 When set, REO has been instructed to not perform the 932 actual re-ordering of frames for this queue, but just to 933 insert the reorder opcodes. 934 935 936 937 Note that this implies that REO is also not going to 938 perform any MSDU level operations, and the entire MPDU (and 939 thus pointer to the MSDU link descriptor) will be pushed to 940 a destination ring that SW has programmed in a SW 941 programmable configuration register in REO 942 943 944 945 <legal all> 946 */ 947 #define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_OFFSET 0x00000008 948 #define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_LSB 4 949 #define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_MASK 0x00000010 950 951 /* Description RX_REO_QUEUE_2_AC 952 953 Indicates which access category the queue descriptor 954 belongs to(filled by SW) 955 956 <legal all> 957 */ 958 #define RX_REO_QUEUE_2_AC_OFFSET 0x00000008 959 #define RX_REO_QUEUE_2_AC_LSB 5 960 #define RX_REO_QUEUE_2_AC_MASK 0x00000060 961 962 /* Description RX_REO_QUEUE_2_BAR 963 964 Indicates if BAR has been received (mostly used for 965 debug purpose and this is filled by REO) 966 967 <legal all> 968 */ 969 #define RX_REO_QUEUE_2_BAR_OFFSET 0x00000008 970 #define RX_REO_QUEUE_2_BAR_LSB 7 971 #define RX_REO_QUEUE_2_BAR_MASK 0x00000080 972 973 /* Description RX_REO_QUEUE_2_RTY 974 975 Retry bit is checked if this bit is set. 976 977 <legal all> 978 */ 979 #define RX_REO_QUEUE_2_RTY_OFFSET 0x00000008 980 #define RX_REO_QUEUE_2_RTY_LSB 8 981 #define RX_REO_QUEUE_2_RTY_MASK 0x00000100 982 983 /* Description RX_REO_QUEUE_2_CHK_2K_MODE 984 985 Indicates what type of operation is expected from Reo 986 when the received frame SN falls within the 2K window 987 988 989 990 See REO MLD document for programming details. 991 992 <legal all> 993 */ 994 #define RX_REO_QUEUE_2_CHK_2K_MODE_OFFSET 0x00000008 995 #define RX_REO_QUEUE_2_CHK_2K_MODE_LSB 9 996 #define RX_REO_QUEUE_2_CHK_2K_MODE_MASK 0x00000200 997 998 /* Description RX_REO_QUEUE_2_OOR_MODE 999 1000 Out of Order mode: 1001 1002 Indicates what type of operation is expected when the 1003 received frame falls within the OOR window. 1004 1005 1006 1007 See REO MLD document for programming details. 1008 1009 <legal all> 1010 */ 1011 #define RX_REO_QUEUE_2_OOR_MODE_OFFSET 0x00000008 1012 #define RX_REO_QUEUE_2_OOR_MODE_LSB 10 1013 #define RX_REO_QUEUE_2_OOR_MODE_MASK 0x00000400 1014 1015 /* Description RX_REO_QUEUE_2_BA_WINDOW_SIZE 1016 1017 Indicates the negotiated (window size + 1). 1018 1019 It can go up to Max of 256bits. 1020 1021 1022 1023 A value 255 means 256 bitmap, 63 means 64 bitmap, 0 1024 (means non-BA session, with window size of 0). The 3 values 1025 here are the main values validated, but other values should 1026 work as well. 1027 1028 1029 1030 A BA window size of 0 (=> one frame entry bitmat), means 1031 that there is NO RX_REO_QUEUE_EXT descriptor following this 1032 RX_REO_QUEUE STRUCT in memory 1033 1034 1035 1036 A BA window size of 1 - 105, means that there is 1 1037 RX_REO_QUEUE_EXT descriptor directly following this 1038 RX_REO_QUEUE STRUCT in memory. 1039 1040 1041 1042 A BA window size of 106 - 210, means that there are 2 1043 RX_REO_QUEUE_EXT descriptors directly following this 1044 RX_REO_QUEUE STRUCT in memory 1045 1046 1047 1048 A BA window size of 211 - 256, means that there are 3 1049 RX_REO_QUEUE_EXT descriptors directly following this 1050 RX_REO_QUEUE STRUCT in memory 1051 1052 1053 1054 <legal 0 - 255> 1055 */ 1056 #define RX_REO_QUEUE_2_BA_WINDOW_SIZE_OFFSET 0x00000008 1057 #define RX_REO_QUEUE_2_BA_WINDOW_SIZE_LSB 11 1058 #define RX_REO_QUEUE_2_BA_WINDOW_SIZE_MASK 0x0007f800 1059 1060 /* Description RX_REO_QUEUE_2_PN_CHECK_NEEDED 1061 1062 When set, REO shall perform the PN increment check 1063 1064 <legal all> 1065 */ 1066 #define RX_REO_QUEUE_2_PN_CHECK_NEEDED_OFFSET 0x00000008 1067 #define RX_REO_QUEUE_2_PN_CHECK_NEEDED_LSB 19 1068 #define RX_REO_QUEUE_2_PN_CHECK_NEEDED_MASK 0x00080000 1069 1070 /* Description RX_REO_QUEUE_2_PN_SHALL_BE_EVEN 1071 1072 Field only valid when 'pn_check_needed' is set. 1073 1074 1075 1076 When set, REO shall confirm that the received PN number 1077 is not only incremented, but also always an even number 1078 1079 <legal all> 1080 */ 1081 #define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_OFFSET 0x00000008 1082 #define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_LSB 20 1083 #define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_MASK 0x00100000 1084 1085 /* Description RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN 1086 1087 Field only valid when 'pn_check_needed' is set. 1088 1089 1090 1091 When set, REO shall confirm that the received PN number 1092 is not only incremented, but also always an uneven number 1093 1094 <legal all> 1095 */ 1096 #define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 1097 #define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_LSB 21 1098 #define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_MASK 0x00200000 1099 1100 /* Description RX_REO_QUEUE_2_PN_HANDLING_ENABLE 1101 1102 Field only valid when 'pn_check_needed' is set. 1103 1104 1105 1106 When set, and REO detected a PN error, HW shall set the 1107 'pn_error_detected_flag'. 1108 1109 <legal all> 1110 */ 1111 #define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_OFFSET 0x00000008 1112 #define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_LSB 22 1113 #define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_MASK 0x00400000 1114 1115 /* Description RX_REO_QUEUE_2_PN_SIZE 1116 1117 Size of the PN field check. 1118 1119 Needed for wrap around handling... 1120 1121 1122 1123 <enum 0 pn_size_24> 1124 1125 <enum 1 pn_size_48> 1126 1127 <enum 2 pn_size_128> 1128 1129 1130 1131 <legal 0-2> 1132 */ 1133 #define RX_REO_QUEUE_2_PN_SIZE_OFFSET 0x00000008 1134 #define RX_REO_QUEUE_2_PN_SIZE_LSB 23 1135 #define RX_REO_QUEUE_2_PN_SIZE_MASK 0x01800000 1136 1137 /* Description RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG 1138 1139 When set, REO shall ignore the ampdu_flag on the 1140 entrance descriptor for this queue. 1141 1142 <legal all> 1143 */ 1144 #define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 1145 #define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_LSB 25 1146 #define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_MASK 0x02000000 1147 1148 /* Description RX_REO_QUEUE_2_RESERVED_2B 1149 1150 <legal 0> 1151 */ 1152 #define RX_REO_QUEUE_2_RESERVED_2B_OFFSET 0x00000008 1153 #define RX_REO_QUEUE_2_RESERVED_2B_LSB 26 1154 #define RX_REO_QUEUE_2_RESERVED_2B_MASK 0xfc000000 1155 1156 /* Description RX_REO_QUEUE_3_SVLD 1157 1158 Sequence number in next field is valid one. It can be 1159 filled by SW if the want to fill in the any negotiated SSN, 1160 otherwise REO will fill the sequence number of first 1161 received packet and set this bit to 1. 1162 1163 <legal all> 1164 */ 1165 #define RX_REO_QUEUE_3_SVLD_OFFSET 0x0000000c 1166 #define RX_REO_QUEUE_3_SVLD_LSB 0 1167 #define RX_REO_QUEUE_3_SVLD_MASK 0x00000001 1168 1169 /* Description RX_REO_QUEUE_3_SSN 1170 1171 Starting Sequence number of the session, this changes 1172 whenever window moves. (can be filled by SW then maintained 1173 by REO) 1174 1175 <legal all> 1176 */ 1177 #define RX_REO_QUEUE_3_SSN_OFFSET 0x0000000c 1178 #define RX_REO_QUEUE_3_SSN_LSB 1 1179 #define RX_REO_QUEUE_3_SSN_MASK 0x00001ffe 1180 1181 /* Description RX_REO_QUEUE_3_CURRENT_INDEX 1182 1183 Points to last forwarded packet 1184 1185 <legal all> 1186 */ 1187 #define RX_REO_QUEUE_3_CURRENT_INDEX_OFFSET 0x0000000c 1188 #define RX_REO_QUEUE_3_CURRENT_INDEX_LSB 13 1189 #define RX_REO_QUEUE_3_CURRENT_INDEX_MASK 0x001fe000 1190 1191 /* Description RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG 1192 1193 Set by REO, can only be cleared by SW 1194 1195 1196 1197 When set, REO has detected a 2k error jump in the 1198 sequence number and from that moment forward, all new frames 1199 are forwarded directly to FW, without duplicate detect, 1200 reordering, etc. 1201 1202 <legal all> 1203 */ 1204 #define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 1205 #define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_LSB 21 1206 #define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00200000 1207 1208 /* Description RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG 1209 1210 Set by REO, can only be cleared by SW 1211 1212 1213 1214 When set, REO has detected a PN error and from that 1215 moment forward, all new frames are forwarded directly to FW, 1216 without duplicate detect, reordering, etc. 1217 1218 <legal all> 1219 */ 1220 #define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 1221 #define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_LSB 22 1222 #define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_MASK 0x00400000 1223 1224 /* Description RX_REO_QUEUE_3_RESERVED_3A 1225 1226 <legal 0> 1227 */ 1228 #define RX_REO_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c 1229 #define RX_REO_QUEUE_3_RESERVED_3A_LSB 23 1230 #define RX_REO_QUEUE_3_RESERVED_3A_MASK 0x7f800000 1231 1232 /* Description RX_REO_QUEUE_3_PN_VALID 1233 1234 PN number in next fields are valid. It can be filled by 1235 SW if it wants to fill in the any negotiated SSN, otherwise 1236 REO will fill the pn based on the first received packet and 1237 set this bit to 1. 1238 1239 <legal all> 1240 */ 1241 #define RX_REO_QUEUE_3_PN_VALID_OFFSET 0x0000000c 1242 #define RX_REO_QUEUE_3_PN_VALID_LSB 31 1243 #define RX_REO_QUEUE_3_PN_VALID_MASK 0x80000000 1244 1245 /* Description RX_REO_QUEUE_4_PN_31_0 1246 1247 1248 <legal all> 1249 */ 1250 #define RX_REO_QUEUE_4_PN_31_0_OFFSET 0x00000010 1251 #define RX_REO_QUEUE_4_PN_31_0_LSB 0 1252 #define RX_REO_QUEUE_4_PN_31_0_MASK 0xffffffff 1253 1254 /* Description RX_REO_QUEUE_5_PN_63_32 1255 1256 Bits [63:32] of the PN number. 1257 1258 <legal all> 1259 */ 1260 #define RX_REO_QUEUE_5_PN_63_32_OFFSET 0x00000014 1261 #define RX_REO_QUEUE_5_PN_63_32_LSB 0 1262 #define RX_REO_QUEUE_5_PN_63_32_MASK 0xffffffff 1263 1264 /* Description RX_REO_QUEUE_6_PN_95_64 1265 1266 Bits [95:64] of the PN number. 1267 1268 <legal all> 1269 */ 1270 #define RX_REO_QUEUE_6_PN_95_64_OFFSET 0x00000018 1271 #define RX_REO_QUEUE_6_PN_95_64_LSB 0 1272 #define RX_REO_QUEUE_6_PN_95_64_MASK 0xffffffff 1273 1274 /* Description RX_REO_QUEUE_7_PN_127_96 1275 1276 Bits [127:96] of the PN number. 1277 1278 <legal all> 1279 */ 1280 #define RX_REO_QUEUE_7_PN_127_96_OFFSET 0x0000001c 1281 #define RX_REO_QUEUE_7_PN_127_96_LSB 0 1282 #define RX_REO_QUEUE_7_PN_127_96_MASK 0xffffffff 1283 1284 /* Description RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP 1285 1286 This timestamp is updated when an MPDU is received and 1287 accesses this Queue Descriptor. It does not include the 1288 access due to Command TLVs or Aging (which will be updated 1289 in Last_rx_dequeue_timestamp). 1290 1291 <legal all> 1292 */ 1293 #define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 1294 #define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 1295 #define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff 1296 1297 /* Description RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP 1298 1299 This timestamp is used for Aging. When an MPDU or 1300 multiple MPDUs are forwarded, either due to window movement, 1301 bar, aging or command flush, this timestamp is updated. Also 1302 when the bitmap is all zero and the first time an MPDU is 1303 queued (opcode=QCUR), this timestamp is updated for aging. 1304 1305 <legal all> 1306 */ 1307 #define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 1308 #define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 1309 #define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff 1310 1311 /* Description RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0 1312 1313 Address (address bits 31-0)of next RX_REO_QUEUE 1314 descriptor in the 'receive timestamp' ordered list. 1315 1316 From it the Position of this queue descriptor in the per 1317 AC aging waitlist can be derived. 1318 1319 Value 0x0 indicates the 'NULL' pointer which implies 1320 that this is the last entry in the list. 1321 1322 <legal all> 1323 */ 1324 #define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 1325 #define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 1326 #define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff 1327 1328 /* Description RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32 1329 1330 Address (address bits 39-32)of next RX_REO_QUEUE 1331 descriptor in the 'receive timestamp' ordered list. 1332 1333 From it the Position of this queue descriptor in the per 1334 AC aging waitlist can be derived. 1335 1336 Value 0x0 indicates the 'NULL' pointer which implies 1337 that this is the last entry in the list. 1338 1339 <legal all> 1340 */ 1341 #define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c 1342 #define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 1343 #define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff 1344 1345 /* Description RX_REO_QUEUE_11_RESERVED_11A 1346 1347 <legal 0> 1348 */ 1349 #define RX_REO_QUEUE_11_RESERVED_11A_OFFSET 0x0000002c 1350 #define RX_REO_QUEUE_11_RESERVED_11A_LSB 8 1351 #define RX_REO_QUEUE_11_RESERVED_11A_MASK 0xffffff00 1352 1353 /* Description RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0 1354 1355 Address (address bits 31-0)of next RX_REO_QUEUE 1356 descriptor in the 'receive timestamp' ordered list. 1357 1358 From it the Position of this queue descriptor in the per 1359 AC aging waitlist can be derived. 1360 1361 Value 0x0 indicates the 'NULL' pointer which implies 1362 that this is the first entry in the list. 1363 1364 <legal all> 1365 */ 1366 #define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 1367 #define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 1368 #define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff 1369 1370 /* Description RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32 1371 1372 Address (address bits 39-32)of next RX_REO_QUEUE 1373 descriptor in the 'receive timestamp' ordered list. 1374 1375 From it the Position of this queue descriptor in the per 1376 AC aging waitlist can be derived. 1377 1378 Value 0x0 indicates the 'NULL' pointer which implies 1379 that this is the first entry in the list. 1380 1381 <legal all> 1382 */ 1383 #define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 1384 #define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 1385 #define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff 1386 1387 /* Description RX_REO_QUEUE_13_RESERVED_13A 1388 1389 <legal 0> 1390 */ 1391 #define RX_REO_QUEUE_13_RESERVED_13A_OFFSET 0x00000034 1392 #define RX_REO_QUEUE_13_RESERVED_13A_LSB 8 1393 #define RX_REO_QUEUE_13_RESERVED_13A_MASK 0xffffff00 1394 1395 /* Description RX_REO_QUEUE_14_RX_BITMAP_31_0 1396 1397 When a bit is set, the corresponding frame is currently 1398 held in the re-order queue. 1399 1400 The bitmap is Fully managed by HW. 1401 1402 SW shall init this to 0, and then never ever change it 1403 1404 <legal all> 1405 */ 1406 #define RX_REO_QUEUE_14_RX_BITMAP_31_0_OFFSET 0x00000038 1407 #define RX_REO_QUEUE_14_RX_BITMAP_31_0_LSB 0 1408 #define RX_REO_QUEUE_14_RX_BITMAP_31_0_MASK 0xffffffff 1409 1410 /* Description RX_REO_QUEUE_15_RX_BITMAP_63_32 1411 1412 See Rx_bitmap_31_0 description 1413 1414 <legal all> 1415 */ 1416 #define RX_REO_QUEUE_15_RX_BITMAP_63_32_OFFSET 0x0000003c 1417 #define RX_REO_QUEUE_15_RX_BITMAP_63_32_LSB 0 1418 #define RX_REO_QUEUE_15_RX_BITMAP_63_32_MASK 0xffffffff 1419 1420 /* Description RX_REO_QUEUE_16_RX_BITMAP_95_64 1421 1422 See Rx_bitmap_31_0 description 1423 1424 <legal all> 1425 */ 1426 #define RX_REO_QUEUE_16_RX_BITMAP_95_64_OFFSET 0x00000040 1427 #define RX_REO_QUEUE_16_RX_BITMAP_95_64_LSB 0 1428 #define RX_REO_QUEUE_16_RX_BITMAP_95_64_MASK 0xffffffff 1429 1430 /* Description RX_REO_QUEUE_17_RX_BITMAP_127_96 1431 1432 See Rx_bitmap_31_0 description 1433 1434 <legal all> 1435 */ 1436 #define RX_REO_QUEUE_17_RX_BITMAP_127_96_OFFSET 0x00000044 1437 #define RX_REO_QUEUE_17_RX_BITMAP_127_96_LSB 0 1438 #define RX_REO_QUEUE_17_RX_BITMAP_127_96_MASK 0xffffffff 1439 1440 /* Description RX_REO_QUEUE_18_RX_BITMAP_159_128 1441 1442 See Rx_bitmap_31_0 description 1443 1444 <legal all> 1445 */ 1446 #define RX_REO_QUEUE_18_RX_BITMAP_159_128_OFFSET 0x00000048 1447 #define RX_REO_QUEUE_18_RX_BITMAP_159_128_LSB 0 1448 #define RX_REO_QUEUE_18_RX_BITMAP_159_128_MASK 0xffffffff 1449 1450 /* Description RX_REO_QUEUE_19_RX_BITMAP_191_160 1451 1452 See Rx_bitmap_31_0 description 1453 1454 <legal all> 1455 */ 1456 #define RX_REO_QUEUE_19_RX_BITMAP_191_160_OFFSET 0x0000004c 1457 #define RX_REO_QUEUE_19_RX_BITMAP_191_160_LSB 0 1458 #define RX_REO_QUEUE_19_RX_BITMAP_191_160_MASK 0xffffffff 1459 1460 /* Description RX_REO_QUEUE_20_RX_BITMAP_223_192 1461 1462 See Rx_bitmap_31_0 description 1463 1464 <legal all> 1465 */ 1466 #define RX_REO_QUEUE_20_RX_BITMAP_223_192_OFFSET 0x00000050 1467 #define RX_REO_QUEUE_20_RX_BITMAP_223_192_LSB 0 1468 #define RX_REO_QUEUE_20_RX_BITMAP_223_192_MASK 0xffffffff 1469 1470 /* Description RX_REO_QUEUE_21_RX_BITMAP_255_224 1471 1472 See Rx_bitmap_31_0 description 1473 1474 <legal all> 1475 */ 1476 #define RX_REO_QUEUE_21_RX_BITMAP_255_224_OFFSET 0x00000054 1477 #define RX_REO_QUEUE_21_RX_BITMAP_255_224_LSB 0 1478 #define RX_REO_QUEUE_21_RX_BITMAP_255_224_MASK 0xffffffff 1479 1480 /* Description RX_REO_QUEUE_22_CURRENT_MPDU_COUNT 1481 1482 The number of MPDUs in the queue. 1483 1484 1485 1486 <legal all> 1487 */ 1488 #define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_OFFSET 0x00000058 1489 #define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_LSB 0 1490 #define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_MASK 0x0000007f 1491 1492 /* Description RX_REO_QUEUE_22_CURRENT_MSDU_COUNT 1493 1494 The number of MSDUs in the queue. 1495 1496 <legal all> 1497 */ 1498 #define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_OFFSET 0x00000058 1499 #define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_LSB 7 1500 #define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_MASK 0xffffff80 1501 1502 /* Description RX_REO_QUEUE_23_RESERVED_23 1503 1504 <legal 0> 1505 */ 1506 #define RX_REO_QUEUE_23_RESERVED_23_OFFSET 0x0000005c 1507 #define RX_REO_QUEUE_23_RESERVED_23_LSB 0 1508 #define RX_REO_QUEUE_23_RESERVED_23_MASK 0x0000000f 1509 1510 /* Description RX_REO_QUEUE_23_TIMEOUT_COUNT 1511 1512 The number of times that REO started forwarding frames 1513 even though there is a hole in the bitmap. Forwarding reason 1514 is Timeout 1515 1516 1517 1518 The counter saturates and freezes at 0x3F 1519 1520 1521 1522 <legal all> 1523 */ 1524 #define RX_REO_QUEUE_23_TIMEOUT_COUNT_OFFSET 0x0000005c 1525 #define RX_REO_QUEUE_23_TIMEOUT_COUNT_LSB 4 1526 #define RX_REO_QUEUE_23_TIMEOUT_COUNT_MASK 0x000003f0 1527 1528 /* Description RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT 1529 1530 The number of times that REO started forwarding frames 1531 even though there is a hole in the bitmap. Forwarding reason 1532 is reception of BAR frame. 1533 1534 1535 1536 The counter saturates and freezes at 0x3F 1537 1538 1539 1540 <legal all> 1541 */ 1542 #define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x0000005c 1543 #define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_LSB 10 1544 #define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 1545 1546 /* Description RX_REO_QUEUE_23_DUPLICATE_COUNT 1547 1548 The number of duplicate frames that have been detected 1549 1550 <legal all> 1551 */ 1552 #define RX_REO_QUEUE_23_DUPLICATE_COUNT_OFFSET 0x0000005c 1553 #define RX_REO_QUEUE_23_DUPLICATE_COUNT_LSB 16 1554 #define RX_REO_QUEUE_23_DUPLICATE_COUNT_MASK 0xffff0000 1555 1556 /* Description RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT 1557 1558 The number of frames that have been received in order 1559 (without a hole that prevented them from being forwarded 1560 immediately) 1561 1562 1563 1564 This corresponds to the Reorder opcodes: 1565 1566 'FWDCUR' and 'FWD BUF' 1567 1568 1569 1570 <legal all> 1571 */ 1572 #define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000060 1573 #define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_LSB 0 1574 #define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff 1575 1576 /* Description RX_REO_QUEUE_24_BAR_RECEIVED_COUNT 1577 1578 The number of times a BAR frame is received. 1579 1580 1581 1582 This corresponds to the Reorder opcodes with 'DROP' 1583 1584 1585 1586 The counter saturates and freezes at 0xFF 1587 1588 <legal all> 1589 */ 1590 #define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_OFFSET 0x00000060 1591 #define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_LSB 24 1592 #define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_MASK 0xff000000 1593 1594 /* Description RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT 1595 1596 The total number of MPDU frames that have been processed 1597 by REO. 'Processing' here means that REO has received them 1598 out of the entrance ring, and retrieved the corresponding 1599 RX_REO_QUEUE Descriptor. 1600 1601 1602 1603 Note that this count includes duplicates, frames that 1604 later had errors, etc. 1605 1606 1607 1608 Note that field 'Duplicate_count' indicates how many of 1609 these MPDUs were duplicates. 1610 1611 1612 1613 <legal all> 1614 */ 1615 #define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000064 1616 #define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 1617 #define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 1618 1619 /* Description RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT 1620 1621 The total number of MSDU frames that have been processed 1622 by REO. 'Processing' here means that REO has received them 1623 out of the entrance ring, and retrieved the corresponding 1624 RX_REO_QUEUE Descriptor. 1625 1626 1627 1628 Note that this count includes duplicates, frames that 1629 later had errors, etc. 1630 1631 1632 1633 <legal all> 1634 */ 1635 #define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 1636 #define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 1637 #define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 1638 1639 /* Description RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT 1640 1641 An approximation of the number of bytes processed for 1642 this queue. 1643 1644 'Processing' here means that REO has received them out 1645 of the entrance ring, and retrieved the corresponding 1646 RX_REO_QUEUE Descriptor. 1647 1648 1649 1650 Note that this count includes duplicates, frames that 1651 later had errors, etc. 1652 1653 1654 1655 In 64 byte units 1656 1657 <legal all> 1658 */ 1659 #define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x0000006c 1660 #define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 1661 #define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff 1662 1663 /* Description RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT 1664 1665 The number of MPDUs received after the window had 1666 already moved on. The 'late' sequence window is defined as 1667 (Window SSN - 256) - (Window SSN - 1) 1668 1669 1670 1671 This corresponds with Out of order detection in 1672 duplicate detect FSM 1673 1674 1675 1676 The counter saturates and freezes at 0xFFF 1677 1678 1679 1680 <legal all> 1681 */ 1682 #define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000070 1683 #define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_LSB 0 1684 #define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff 1685 1686 /* Description RX_REO_QUEUE_28_WINDOW_JUMP_2K 1687 1688 The number of times the window moved more then 2K 1689 1690 1691 1692 The counter saturates and freezes at 0xF 1693 1694 1695 1696 (Note: field name can not start with number: previous 1697 2k_window_jump) 1698 1699 1700 1701 <legal all> 1702 */ 1703 #define RX_REO_QUEUE_28_WINDOW_JUMP_2K_OFFSET 0x00000070 1704 #define RX_REO_QUEUE_28_WINDOW_JUMP_2K_LSB 12 1705 #define RX_REO_QUEUE_28_WINDOW_JUMP_2K_MASK 0x0000f000 1706 1707 /* Description RX_REO_QUEUE_28_HOLE_COUNT 1708 1709 The number of times a hole was created in the receive 1710 bitmap. 1711 1712 1713 1714 This corresponds to the Reorder opcodes with 'QCUR' 1715 1716 1717 1718 <legal all> 1719 */ 1720 #define RX_REO_QUEUE_28_HOLE_COUNT_OFFSET 0x00000070 1721 #define RX_REO_QUEUE_28_HOLE_COUNT_LSB 16 1722 #define RX_REO_QUEUE_28_HOLE_COUNT_MASK 0xffff0000 1723 1724 /* Description RX_REO_QUEUE_29_RESERVED_29 1725 1726 <legal 0> 1727 */ 1728 #define RX_REO_QUEUE_29_RESERVED_29_OFFSET 0x00000074 1729 #define RX_REO_QUEUE_29_RESERVED_29_LSB 0 1730 #define RX_REO_QUEUE_29_RESERVED_29_MASK 0xffffffff 1731 1732 /* Description RX_REO_QUEUE_30_RESERVED_30 1733 1734 <legal 0> 1735 */ 1736 #define RX_REO_QUEUE_30_RESERVED_30_OFFSET 0x00000078 1737 #define RX_REO_QUEUE_30_RESERVED_30_LSB 0 1738 #define RX_REO_QUEUE_30_RESERVED_30_MASK 0xffffffff 1739 1740 /* Description RX_REO_QUEUE_31_RESERVED_31 1741 1742 <legal 0> 1743 */ 1744 #define RX_REO_QUEUE_31_RESERVED_31_OFFSET 0x0000007c 1745 #define RX_REO_QUEUE_31_RESERVED_31_LSB 0 1746 #define RX_REO_QUEUE_31_RESERVED_31_MASK 0xffffffff 1747 1748 1749 #endif // _RX_REO_QUEUE_H_ 1750