1 /* 2 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_MPDU_INFO_H_ 18 #define _RX_MPDU_INFO_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "rxpt_classify_info.h" 23 24 // ################ START SUMMARY ################# 25 // 26 // Dword Fields 27 // 0 struct rxpt_classify_info rxpt_classify_info_details; 28 // 1 rx_reo_queue_desc_addr_31_0[31:0] 29 // 2 rx_reo_queue_desc_addr_39_32[7:0], receive_queue_number[23:8], pre_delim_err_warning[24], first_delim_err[25], reserved_2a[31:26] 30 // 3 pn_31_0[31:0] 31 // 4 pn_63_32[31:0] 32 // 5 pn_95_64[31:0] 33 // 6 pn_127_96[31:0] 34 // 7 epd_en[0], all_frames_shall_be_encrypted[1], encrypt_type[5:2], wep_key_width_for_variable_key[7:6], mesh_sta[9:8], bssid_hit[10], bssid_number[14:11], tid[18:15], reserved_7a[31:19] 35 // 8 peer_meta_data[31:0] 36 // 9 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], ndp_frame[9], phy_err[10], phy_err_during_mpdu_header[11], protocol_version_err[12], ast_based_lookup_valid[13], reserved_9a[15:14], phy_ppdu_id[31:16] 37 // 10 ast_index[15:0], sw_peer_id[31:16] 38 // 11 mpdu_frame_control_valid[0], mpdu_duration_valid[1], mac_addr_ad1_valid[2], mac_addr_ad2_valid[3], mac_addr_ad3_valid[4], mac_addr_ad4_valid[5], mpdu_sequence_control_valid[6], mpdu_qos_control_valid[7], mpdu_ht_control_valid[8], frame_encryption_info_valid[9], mpdu_fragment_number[13:10], more_fragment_flag[14], reserved_11a[15], fr_ds[16], to_ds[17], encrypted[18], mpdu_retry[19], mpdu_sequence_number[31:20] 39 // 12 key_id_octet[7:0], new_peer_entry[8], decrypt_needed[9], decap_type[11:10], rx_insert_vlan_c_tag_padding[12], rx_insert_vlan_s_tag_padding[13], strip_vlan_c_tag_decap[14], strip_vlan_s_tag_decap[15], pre_delim_count[27:16], ampdu_flag[28], bar_frame[29], raw_mpdu[30], reserved_12[31] 40 // 13 mpdu_length[13:0], first_mpdu[14], mcast_bcast[15], ast_index_not_found[16], ast_index_timeout[17], power_mgmt[18], non_qos[19], null_data[20], mgmt_type[21], ctrl_type[22], more_data[23], eosp[24], fragment_flag[25], order[26], u_apsd_trigger[27], encrypt_required[28], directed[29], amsdu_present[30], reserved_13[31] 41 // 14 mpdu_frame_control_field[15:0], mpdu_duration_field[31:16] 42 // 15 mac_addr_ad1_31_0[31:0] 43 // 16 mac_addr_ad1_47_32[15:0], mac_addr_ad2_15_0[31:16] 44 // 17 mac_addr_ad2_47_16[31:0] 45 // 18 mac_addr_ad3_31_0[31:0] 46 // 19 mac_addr_ad3_47_32[15:0], mpdu_sequence_control_field[31:16] 47 // 20 mac_addr_ad4_31_0[31:0] 48 // 21 mac_addr_ad4_47_32[15:0], mpdu_qos_control_field[31:16] 49 // 22 mpdu_ht_control_field[31:0] 50 // 51 // ################ END SUMMARY ################# 52 53 #define NUM_OF_DWORDS_RX_MPDU_INFO 23 54 55 struct rx_mpdu_info { 56 struct rxpt_classify_info rxpt_classify_info_details; 57 uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] 58 uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] 59 receive_queue_number : 16, //[23:8] 60 pre_delim_err_warning : 1, //[24] 61 first_delim_err : 1, //[25] 62 reserved_2a : 6; //[31:26] 63 uint32_t pn_31_0 : 32; //[31:0] 64 uint32_t pn_63_32 : 32; //[31:0] 65 uint32_t pn_95_64 : 32; //[31:0] 66 uint32_t pn_127_96 : 32; //[31:0] 67 uint32_t epd_en : 1, //[0] 68 all_frames_shall_be_encrypted : 1, //[1] 69 encrypt_type : 4, //[5:2] 70 wep_key_width_for_variable_key : 2, //[7:6] 71 mesh_sta : 2, //[9:8] 72 bssid_hit : 1, //[10] 73 bssid_number : 4, //[14:11] 74 tid : 4, //[18:15] 75 reserved_7a : 13; //[31:19] 76 uint32_t peer_meta_data : 32; //[31:0] 77 uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] 78 sw_frame_group_id : 7, //[8:2] 79 ndp_frame : 1, //[9] 80 phy_err : 1, //[10] 81 phy_err_during_mpdu_header : 1, //[11] 82 protocol_version_err : 1, //[12] 83 ast_based_lookup_valid : 1, //[13] 84 reserved_9a : 2, //[15:14] 85 phy_ppdu_id : 16; //[31:16] 86 uint32_t ast_index : 16, //[15:0] 87 sw_peer_id : 16; //[31:16] 88 uint32_t mpdu_frame_control_valid : 1, //[0] 89 mpdu_duration_valid : 1, //[1] 90 mac_addr_ad1_valid : 1, //[2] 91 mac_addr_ad2_valid : 1, //[3] 92 mac_addr_ad3_valid : 1, //[4] 93 mac_addr_ad4_valid : 1, //[5] 94 mpdu_sequence_control_valid : 1, //[6] 95 mpdu_qos_control_valid : 1, //[7] 96 mpdu_ht_control_valid : 1, //[8] 97 frame_encryption_info_valid : 1, //[9] 98 mpdu_fragment_number : 4, //[13:10] 99 more_fragment_flag : 1, //[14] 100 reserved_11a : 1, //[15] 101 fr_ds : 1, //[16] 102 to_ds : 1, //[17] 103 encrypted : 1, //[18] 104 mpdu_retry : 1, //[19] 105 mpdu_sequence_number : 12; //[31:20] 106 uint32_t key_id_octet : 8, //[7:0] 107 new_peer_entry : 1, //[8] 108 decrypt_needed : 1, //[9] 109 decap_type : 2, //[11:10] 110 rx_insert_vlan_c_tag_padding : 1, //[12] 111 rx_insert_vlan_s_tag_padding : 1, //[13] 112 strip_vlan_c_tag_decap : 1, //[14] 113 strip_vlan_s_tag_decap : 1, //[15] 114 pre_delim_count : 12, //[27:16] 115 ampdu_flag : 1, //[28] 116 bar_frame : 1, //[29] 117 raw_mpdu : 1, //[30] 118 reserved_12 : 1; //[31] 119 uint32_t mpdu_length : 14, //[13:0] 120 first_mpdu : 1, //[14] 121 mcast_bcast : 1, //[15] 122 ast_index_not_found : 1, //[16] 123 ast_index_timeout : 1, //[17] 124 power_mgmt : 1, //[18] 125 non_qos : 1, //[19] 126 null_data : 1, //[20] 127 mgmt_type : 1, //[21] 128 ctrl_type : 1, //[22] 129 more_data : 1, //[23] 130 eosp : 1, //[24] 131 fragment_flag : 1, //[25] 132 order : 1, //[26] 133 u_apsd_trigger : 1, //[27] 134 encrypt_required : 1, //[28] 135 directed : 1, //[29] 136 amsdu_present : 1, //[30] 137 reserved_13 : 1; //[31] 138 uint32_t mpdu_frame_control_field : 16, //[15:0] 139 mpdu_duration_field : 16; //[31:16] 140 uint32_t mac_addr_ad1_31_0 : 32; //[31:0] 141 uint32_t mac_addr_ad1_47_32 : 16, //[15:0] 142 mac_addr_ad2_15_0 : 16; //[31:16] 143 uint32_t mac_addr_ad2_47_16 : 32; //[31:0] 144 uint32_t mac_addr_ad3_31_0 : 32; //[31:0] 145 uint32_t mac_addr_ad3_47_32 : 16, //[15:0] 146 mpdu_sequence_control_field : 16; //[31:16] 147 uint32_t mac_addr_ad4_31_0 : 32; //[31:0] 148 uint32_t mac_addr_ad4_47_32 : 16, //[15:0] 149 mpdu_qos_control_field : 16; //[31:16] 150 uint32_t mpdu_ht_control_field : 32; //[31:0] 151 }; 152 153 /* 154 155 struct rxpt_classify_info rxpt_classify_info_details 156 157 In case of ndp or phy_err or AST_based_lookup_valid == 158 0, this field will be set to 0 159 160 161 162 RXOLE related classification info 163 164 <legal all 165 166 rx_reo_queue_desc_addr_31_0 167 168 In case of ndp or phy_err or AST_based_lookup_valid == 169 0, this field will be set to 0 170 171 172 173 Address (lower 32 bits) of the REO queue descriptor. 174 175 176 177 If no Peer entry lookup happened for this frame, the 178 value wil be set to 0, and the frame shall never be pushed 179 to REO entrance ring. 180 181 <legal all> 182 183 rx_reo_queue_desc_addr_39_32 184 185 In case of ndp or phy_err or AST_based_lookup_valid == 186 0, this field will be set to 0 187 188 189 190 Address (upper 8 bits) of the REO queue descriptor. 191 192 193 194 If no Peer entry lookup happened for this frame, the 195 value wil be set to 0, and the frame shall never be pushed 196 to REO entrance ring. 197 198 <legal all> 199 200 receive_queue_number 201 202 In case of ndp or phy_err or AST_based_lookup_valid == 203 0, this field will be set to 0 204 205 206 207 Indicates the MPDU queue ID to which this MPDU link 208 descriptor belongs 209 210 Used for tracking and debugging 211 212 <legal all> 213 214 pre_delim_err_warning 215 216 Indicates that a delimiter FCS error was found in 217 between the Previous MPDU and this MPDU. 218 219 220 221 Note that this is just a warning, and does not mean that 222 this MPDU is corrupted in any way. If it is, there will be 223 other errors indicated such as FCS or decrypt errors 224 225 226 227 In case of ndp or phy_err, this field will indicate at 228 least one of delimiters located after the last MPDU in the 229 previous PPDU has been corrupted. 230 231 first_delim_err 232 233 Indicates that the first delimiter had a FCS failure. 234 Only valid when first_mpdu and first_msdu are set. 235 236 237 238 239 reserved_2a 240 241 <legal 0> 242 243 pn_31_0 244 245 246 247 248 249 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 250 is valid. 251 252 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 253 WEPSeed[1], pn1}. Only pn[47:0] is valid. 254 255 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, 256 pn1, pn0}. Only pn[47:0] is valid. 257 258 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, 259 pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, 260 pn0}. pn[127:0] are valid. 261 262 263 264 265 pn_63_32 266 267 268 269 270 Bits [63:32] of the PN number. See description for 271 pn_31_0. 272 273 274 275 276 pn_95_64 277 278 279 280 281 Bits [95:64] of the PN number. See description for 282 pn_31_0. 283 284 285 286 287 pn_127_96 288 289 290 291 292 Bits [127:96] of the PN number. See description for 293 pn_31_0. 294 295 296 297 298 epd_en 299 300 Field only valid when AST_based_lookup_valid == 1. 301 302 303 304 305 306 In case of ndp or phy_err or AST_based_lookup_valid == 307 0, this field will be set to 0 308 309 310 311 If set to one use EPD instead of LPD 312 313 314 315 316 <legal all> 317 318 all_frames_shall_be_encrypted 319 320 In case of ndp or phy_err or AST_based_lookup_valid == 321 0, this field will be set to 0 322 323 324 325 When set, all frames (data only ?) shall be encrypted. 326 If not, RX CRYPTO shall set an error flag. 327 328 <legal all> 329 330 encrypt_type 331 332 In case of ndp or phy_err or AST_based_lookup_valid == 333 0, this field will be set to 0 334 335 336 337 Indicates type of decrypt cipher used (as defined in the 338 peer entry) 339 340 341 342 <enum 0 wep_40> WEP 40-bit 343 344 <enum 1 wep_104> WEP 104-bit 345 346 <enum 2 tkip_no_mic> TKIP without MIC 347 348 <enum 3 wep_128> WEP 128-bit 349 350 <enum 4 tkip_with_mic> TKIP with MIC 351 352 <enum 5 wapi> WAPI 353 354 <enum 6 aes_ccmp_128> AES CCMP 128 355 356 <enum 7 no_cipher> No crypto 357 358 <enum 8 aes_ccmp_256> AES CCMP 256 359 360 <enum 9 aes_gcmp_128> AES CCMP 128 361 362 <enum 10 aes_gcmp_256> AES CCMP 256 363 364 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 365 366 367 368 <enum 12 wep_varied_width> WEP encryption. As for WEP 369 per keyid the key bit width can vary, the key bit width for 370 this MPDU will be indicated in field 371 wep_key_width_for_variable key 372 373 <legal 0-12> 374 375 wep_key_width_for_variable_key 376 377 Field only valid when key_type is set to 378 wep_varied_width. 379 380 381 382 This field indicates the size of the wep key for this 383 MPDU. 384 385 386 387 <enum 0 wep_varied_width_40> WEP 40-bit 388 389 <enum 1 wep_varied_width_104> WEP 104-bit 390 391 <enum 2 wep_varied_width_128> WEP 128-bit 392 393 394 395 <legal 0-2> 396 397 mesh_sta 398 399 In case of ndp or phy_err or AST_based_lookup_valid == 400 0, this field will be set to 0 401 402 403 404 When set, this is a Mesh (11s) STA. 405 406 407 408 The interpretation of the A-MSDU 'Length' field in the 409 MPDU (if any) is decided by the e-numerations below. 410 411 412 413 <enum 0 MESH_DISABLE> 414 415 <enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and 416 includes the length of Mesh Control. 417 418 <enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and 419 excludes the length of Mesh Control. 420 421 <enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian 422 and excludes the length of Mesh Control. This is 423 802.11s-compliant. 424 425 <legal all> 426 427 bssid_hit 428 429 In case of ndp or phy_err or AST_based_lookup_valid == 430 0, this field will be set to 0 431 432 433 434 When set, the BSSID of the incoming frame matched one of 435 the 8 BSSID register values 436 437 438 439 <legal all> 440 441 bssid_number 442 443 Field only valid when bssid_hit is set. 444 445 446 447 This number indicates which one out of the 8 BSSID 448 register values matched the incoming frame 449 450 <legal all> 451 452 tid 453 454 Field only valid when mpdu_qos_control_valid is set 455 456 457 458 The TID field in the QoS control field 459 460 <legal all> 461 462 reserved_7a 463 464 <legal 0> 465 466 peer_meta_data 467 468 In case of ndp or phy_err or AST_based_lookup_valid == 469 0, this field will be set to 0 470 471 472 473 Meta data that SW has programmed in the Peer table entry 474 of the transmitting STA. 475 476 <legal all> 477 478 rxpcu_mpdu_filter_in_category 479 480 Field indicates what the reason was that this MPDU frame 481 was allowed to come into the receive path by RXPCU 482 483 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 484 frame filter programming of rxpcu 485 486 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 487 regular frame filter and would have been dropped, were it 488 not for the frame fitting into the 'monitor_client' 489 category. 490 491 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 492 regular frame filter and also did not pass the 493 rxpcu_monitor_client filter. It would have been dropped 494 accept that it did pass the 'monitor_other' category. 495 496 497 498 Note: for ndp frame, if it was expected because the 499 preceding NDPA was filter_pass, the setting 500 rxpcu_filter_pass will be used. This setting will also be 501 used for every ndp frame in case Promiscuous mode is 502 enabled. 503 504 505 506 In case promiscuous is not enabled, and an NDP is not 507 preceded by a NPDA filter pass frame, the only other setting 508 that could appear here for the NDP is rxpcu_monitor_other. 509 510 (rxpcu has a configuration bit specifically for this 511 scenario) 512 513 514 515 Note: for 516 517 <legal 0-2> 518 519 sw_frame_group_id 520 521 SW processes frames based on certain classifications. 522 This field indicates to what sw classification this MPDU is 523 mapped. 524 525 The classification is given in priority order 526 527 528 529 <enum 0 sw_frame_group_NDP_frame> Note: The 530 corresponding Rxpcu_Mpdu_filter_in_category can be 531 rxpcu_filter_pass or rxpcu_monitor_other 532 533 534 535 <enum 1 sw_frame_group_Multicast_data> 536 537 <enum 2 sw_frame_group_Unicast_data> 538 539 <enum 3 sw_frame_group_Null_data > This includes mpdus 540 of type Data Null as well as QoS Data Null 541 542 543 544 <enum 4 sw_frame_group_mgmt_0000 > 545 546 <enum 5 sw_frame_group_mgmt_0001 > 547 548 <enum 6 sw_frame_group_mgmt_0010 > 549 550 <enum 7 sw_frame_group_mgmt_0011 > 551 552 <enum 8 sw_frame_group_mgmt_0100 > 553 554 <enum 9 sw_frame_group_mgmt_0101 > 555 556 <enum 10 sw_frame_group_mgmt_0110 > 557 558 <enum 11 sw_frame_group_mgmt_0111 > 559 560 <enum 12 sw_frame_group_mgmt_1000 > 561 562 <enum 13 sw_frame_group_mgmt_1001 > 563 564 <enum 14 sw_frame_group_mgmt_1010 > 565 566 <enum 15 sw_frame_group_mgmt_1011 > 567 568 <enum 16 sw_frame_group_mgmt_1100 > 569 570 <enum 17 sw_frame_group_mgmt_1101 > 571 572 <enum 18 sw_frame_group_mgmt_1110 > 573 574 <enum 19 sw_frame_group_mgmt_1111 > 575 576 577 578 <enum 20 sw_frame_group_ctrl_0000 > 579 580 <enum 21 sw_frame_group_ctrl_0001 > 581 582 <enum 22 sw_frame_group_ctrl_0010 > 583 584 <enum 23 sw_frame_group_ctrl_0011 > 585 586 <enum 24 sw_frame_group_ctrl_0100 > 587 588 <enum 25 sw_frame_group_ctrl_0101 > 589 590 <enum 26 sw_frame_group_ctrl_0110 > 591 592 <enum 27 sw_frame_group_ctrl_0111 > 593 594 <enum 28 sw_frame_group_ctrl_1000 > 595 596 <enum 29 sw_frame_group_ctrl_1001 > 597 598 <enum 30 sw_frame_group_ctrl_1010 > 599 600 <enum 31 sw_frame_group_ctrl_1011 > 601 602 <enum 32 sw_frame_group_ctrl_1100 > 603 604 <enum 33 sw_frame_group_ctrl_1101 > 605 606 <enum 34 sw_frame_group_ctrl_1110 > 607 608 <enum 35 sw_frame_group_ctrl_1111 > 609 610 611 612 <enum 36 sw_frame_group_unsupported> This covers type 3 613 and protocol version != 0 614 615 Note: The corresponding Rxpcu_Mpdu_filter_in_category 616 can only be rxpcu_monitor_other 617 618 619 620 621 Note: The corresponding Rxpcu_Mpdu_filter_in_category 622 can be rxpcu_filter_pass 623 624 625 626 <legal 0-37> 627 628 ndp_frame 629 630 When set, the received frame was an NDP frame, and thus 631 there will be no MPDU data. 632 633 <legal all> 634 635 phy_err 636 637 When set, a PHY error was received before MAC received 638 any data, and thus there will be no MPDU data. 639 640 <legal all> 641 642 phy_err_during_mpdu_header 643 644 When set, a PHY error was received before MAC received 645 the complete MPDU header which was needed for proper 646 decoding 647 648 <legal all> 649 650 protocol_version_err 651 652 Set when RXPCU detected a version error in the Frame 653 control field 654 655 <legal all> 656 657 ast_based_lookup_valid 658 659 When set, AST based lookup for this frame has found a 660 valid result. 661 662 663 664 Note that for NDP frame this will never be set 665 666 <legal all> 667 668 reserved_9a 669 670 <legal 0> 671 672 phy_ppdu_id 673 674 A ppdu counter value that PHY increments for every PPDU 675 received. The counter value wraps around 676 677 <legal all> 678 679 ast_index 680 681 This field indicates the index of the AST entry 682 corresponding to this MPDU. It is provided by the GSE module 683 instantiated in RXPCU. 684 685 A value of 0xFFFF indicates an invalid AST index, 686 meaning that No AST entry was found or NO AST search was 687 performed 688 689 690 691 In case of ndp or phy_err, this field will be set to 692 0xFFFF 693 694 <legal all> 695 696 sw_peer_id 697 698 In case of ndp or phy_err or AST_based_lookup_valid == 699 0, this field will be set to 0 700 701 702 703 This field indicates a unique peer identifier. It is set 704 equal to field 'sw_peer_id' from the AST entry 705 706 707 708 <legal all> 709 710 mpdu_frame_control_valid 711 712 When set, the field Mpdu_Frame_control_field has valid 713 information 714 715 716 717 718 <legal all> 719 720 mpdu_duration_valid 721 722 When set, the field Mpdu_duration_field has valid 723 information 724 725 726 727 728 <legal all> 729 730 mac_addr_ad1_valid 731 732 When set, the fields mac_addr_ad1_..... have valid 733 information 734 735 736 737 738 <legal all> 739 740 mac_addr_ad2_valid 741 742 When set, the fields mac_addr_ad2_..... have valid 743 information 744 745 746 747 748 749 750 751 <legal all> 752 753 mac_addr_ad3_valid 754 755 When set, the fields mac_addr_ad3_..... have valid 756 information 757 758 759 760 761 762 763 764 <legal all> 765 766 mac_addr_ad4_valid 767 768 When set, the fields mac_addr_ad4_..... have valid 769 information 770 771 772 773 774 775 776 777 <legal all> 778 779 mpdu_sequence_control_valid 780 781 When set, the fields mpdu_sequence_control_field and 782 mpdu_sequence_number have valid information as well as field 783 784 785 786 For MPDUs without a sequence control field, this field 787 will not be set. 788 789 790 791 792 <legal all> 793 794 mpdu_qos_control_valid 795 796 When set, the field mpdu_qos_control_field has valid 797 information 798 799 800 801 For MPDUs without a QoS control field, this field will 802 not be set. 803 804 805 806 807 <legal all> 808 809 mpdu_ht_control_valid 810 811 When set, the field mpdu_HT_control_field has valid 812 information 813 814 815 816 For MPDUs without a HT control field, this field will 817 not be set. 818 819 820 821 822 <legal all> 823 824 frame_encryption_info_valid 825 826 When set, the encryption related info fields, like IV 827 and PN are valid 828 829 830 831 For MPDUs that are not encrypted, this will not be set. 832 833 834 835 836 <legal all> 837 838 mpdu_fragment_number 839 840 Field only valid when Mpdu_sequence_control_valid is set 841 AND Fragment_flag is set 842 843 844 845 The fragment number from the 802.11 header 846 847 848 849 <legal all> 850 851 more_fragment_flag 852 853 The More Fragment bit setting from the MPDU header of 854 the received frame 855 856 857 858 <legal all> 859 860 reserved_11a 861 862 <legal 0> 863 864 fr_ds 865 866 Field only valid when Mpdu_frame_control_valid is set 867 868 869 870 Set if the from DS bit is set in the frame control. 871 872 <legal all> 873 874 to_ds 875 876 Field only valid when Mpdu_frame_control_valid is set 877 878 879 880 Set if the to DS bit is set in the frame control. 881 882 <legal all> 883 884 encrypted 885 886 Field only valid when Mpdu_frame_control_valid is set. 887 888 889 890 Protected bit from the frame control. 891 892 <legal all> 893 894 mpdu_retry 895 896 Field only valid when Mpdu_frame_control_valid is set. 897 898 899 900 Retry bit from the frame control. Only valid when 901 first_msdu is set. 902 903 <legal all> 904 905 mpdu_sequence_number 906 907 Field only valid when Mpdu_sequence_control_valid is 908 set. 909 910 911 912 The sequence number from the 802.11 header. 913 914 <legal all> 915 916 key_id_octet 917 918 919 920 921 The key ID octet from the IV. 922 923 924 925 In case of ndp or phy_err or AST_based_lookup_valid == 926 0, this field will be set to 0 927 928 <legal all> 929 930 new_peer_entry 931 932 In case of ndp or phy_err or AST_based_lookup_valid == 933 0, this field will be set to 0 934 935 936 937 Set if new RX_PEER_ENTRY TLV follows. If clear, 938 RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either 939 uses old peer entry or not decrypt. 940 941 <legal all> 942 943 decrypt_needed 944 945 In case of ndp or phy_err or AST_based_lookup_valid == 946 0, this field will be set to 0 947 948 949 950 Set if decryption is needed. 951 952 953 954 Note: 955 956 When RXPCU sets bit 'ast_index_not_found' and/or 957 ast_index_timeout', RXPCU will also ensure that this bit is 958 NOT set 959 960 CRYPTO for that reason only needs to evaluate this bit 961 and non of the other ones. 962 963 <legal all> 964 965 decap_type 966 967 In case of ndp or phy_err or AST_based_lookup_valid == 968 0, this field will be set to 0 969 970 971 972 Used by the OLE during decapsulation. 973 974 975 976 Indicates the decapsulation that HW will perform: 977 978 979 980 <enum 0 RAW> No encapsulation 981 982 <enum 1 Native_WiFi> 983 984 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses 985 SNAP/LLC) 986 987 <enum 3 802_3> Indicate Ethernet 988 989 990 991 <legal all> 992 993 rx_insert_vlan_c_tag_padding 994 995 In case of ndp or phy_err or AST_based_lookup_valid == 996 0, this field will be set to 0 997 998 999 1000 Insert 4 byte of all zeros as VLAN tag if the rx payload 1001 does not have VLAN. Used during decapsulation. 1002 1003 <legal all> 1004 1005 rx_insert_vlan_s_tag_padding 1006 1007 In case of ndp or phy_err or AST_based_lookup_valid == 1008 0, this field will be set to 0 1009 1010 1011 1012 Insert 4 byte of all zeros as double VLAN tag if the rx 1013 payload does not have VLAN. Used during 1014 1015 <legal all> 1016 1017 strip_vlan_c_tag_decap 1018 1019 In case of ndp or phy_err or AST_based_lookup_valid == 1020 0, this field will be set to 0 1021 1022 1023 1024 Strip the VLAN during decapsulation. Used by the OLE. 1025 1026 <legal all> 1027 1028 strip_vlan_s_tag_decap 1029 1030 In case of ndp or phy_err or AST_based_lookup_valid == 1031 0, this field will be set to 0 1032 1033 1034 1035 Strip the double VLAN during decapsulation. Used by 1036 the OLE. 1037 1038 <legal all> 1039 1040 pre_delim_count 1041 1042 The number of delimiters before this MPDU. 1043 1044 1045 1046 Note that this number is cleared at PPDU start. 1047 1048 1049 1050 If this MPDU is the first received MPDU in the PPDU and 1051 this MPDU gets filtered-in, this field will indicate the 1052 number of delimiters located after the last MPDU in the 1053 previous PPDU. 1054 1055 1056 1057 If this MPDU is located after the first received MPDU in 1058 an PPDU, this field will indicate the number of delimiters 1059 located between the previous MPDU and this MPDU. 1060 1061 1062 1063 In case of ndp or phy_err, this field will indicate the 1064 number of delimiters located after the last MPDU in the 1065 previous PPDU. 1066 1067 <legal all> 1068 1069 ampdu_flag 1070 1071 When set, received frame was part of an A-MPDU. 1072 1073 1074 1075 1076 <legal all> 1077 1078 bar_frame 1079 1080 In case of ndp or phy_err or AST_based_lookup_valid == 1081 0, this field will be set to 0 1082 1083 1084 1085 When set, received frame is a BAR frame 1086 1087 <legal all> 1088 1089 raw_mpdu 1090 1091 Consumer: SW 1092 1093 Producer: RXOLE 1094 1095 1096 1097 RXPCU sets this field to 0 and RXOLE overwrites it. 1098 1099 1100 1101 Set to 1 by RXOLE when it has not performed any 802.11 1102 to Ethernet/Natvie WiFi header conversion on this MPDU. 1103 1104 <legal all> 1105 1106 reserved_12 1107 1108 <legal 0> 1109 1110 mpdu_length 1111 1112 In case of ndp or phy_err this field will be set to 0 1113 1114 1115 1116 MPDU length before decapsulation. 1117 1118 <legal all> 1119 1120 first_mpdu 1121 1122 See definition in RX attention descriptor 1123 1124 1125 1126 In case of ndp or phy_err, this field will be set. Note 1127 however that there will not actually be any data contents in 1128 the MPDU. 1129 1130 <legal all> 1131 1132 mcast_bcast 1133 1134 In case of ndp or phy_err or Phy_err_during_mpdu_header 1135 this field will be set to 0 1136 1137 1138 1139 See definition in RX attention descriptor 1140 1141 <legal all> 1142 1143 ast_index_not_found 1144 1145 In case of ndp or phy_err or Phy_err_during_mpdu_header 1146 this field will be set to 0 1147 1148 1149 1150 See definition in RX attention descriptor 1151 1152 <legal all> 1153 1154 ast_index_timeout 1155 1156 In case of ndp or phy_err or Phy_err_during_mpdu_header 1157 this field will be set to 0 1158 1159 1160 1161 See definition in RX attention descriptor 1162 1163 <legal all> 1164 1165 power_mgmt 1166 1167 In case of ndp or phy_err or Phy_err_during_mpdu_header 1168 this field will be set to 0 1169 1170 1171 1172 See definition in RX attention descriptor 1173 1174 <legal all> 1175 1176 non_qos 1177 1178 In case of ndp or phy_err or Phy_err_during_mpdu_header 1179 this field will be set to 1 1180 1181 1182 1183 See definition in RX attention descriptor 1184 1185 <legal all> 1186 1187 null_data 1188 1189 In case of ndp or phy_err or Phy_err_during_mpdu_header 1190 this field will be set to 0 1191 1192 1193 1194 See definition in RX attention descriptor 1195 1196 <legal all> 1197 1198 mgmt_type 1199 1200 In case of ndp or phy_err or Phy_err_during_mpdu_header 1201 this field will be set to 0 1202 1203 1204 1205 See definition in RX attention descriptor 1206 1207 <legal all> 1208 1209 ctrl_type 1210 1211 In case of ndp or phy_err or Phy_err_during_mpdu_header 1212 this field will be set to 0 1213 1214 1215 1216 See definition in RX attention descriptor 1217 1218 <legal all> 1219 1220 more_data 1221 1222 In case of ndp or phy_err or Phy_err_during_mpdu_header 1223 this field will be set to 0 1224 1225 1226 1227 See definition in RX attention descriptor 1228 1229 <legal all> 1230 1231 eosp 1232 1233 In case of ndp or phy_err or Phy_err_during_mpdu_header 1234 this field will be set to 0 1235 1236 1237 1238 See definition in RX attention descriptor 1239 1240 <legal all> 1241 1242 fragment_flag 1243 1244 In case of ndp or phy_err or Phy_err_during_mpdu_header 1245 this field will be set to 0 1246 1247 1248 1249 See definition in RX attention descriptor 1250 1251 <legal all> 1252 1253 order 1254 1255 In case of ndp or phy_err or Phy_err_during_mpdu_header 1256 this field will be set to 0 1257 1258 1259 1260 See definition in RX attention descriptor 1261 1262 1263 1264 <legal all> 1265 1266 u_apsd_trigger 1267 1268 In case of ndp or phy_err or Phy_err_during_mpdu_header 1269 this field will be set to 0 1270 1271 1272 1273 See definition in RX attention descriptor 1274 1275 <legal all> 1276 1277 encrypt_required 1278 1279 In case of ndp or phy_err or Phy_err_during_mpdu_header 1280 this field will be set to 0 1281 1282 1283 1284 See definition in RX attention descriptor 1285 1286 <legal all> 1287 1288 directed 1289 1290 In case of ndp or phy_err or Phy_err_during_mpdu_header 1291 this field will be set to 0 1292 1293 1294 1295 See definition in RX attention descriptor 1296 1297 <legal all> 1298 1299 amsdu_present 1300 1301 Field only valid when Mpdu_qos_control_valid is set 1302 1303 1304 1305 The 'amsdu_present' bit within the QoS control field of 1306 the MPDU 1307 1308 <legal all> 1309 1310 reserved_13 1311 1312 <legal 0> 1313 1314 mpdu_frame_control_field 1315 1316 Field only valid when Mpdu_frame_control_valid is set 1317 1318 1319 1320 The frame control field of this received MPDU. 1321 1322 1323 1324 Field only valid when Ndp_frame and phy_err are NOT set 1325 1326 1327 1328 Bytes 0 + 1 of the received MPDU 1329 1330 <legal all> 1331 1332 mpdu_duration_field 1333 1334 Field only valid when Mpdu_duration_valid is set 1335 1336 1337 1338 The duration field of this received MPDU. 1339 1340 <legal all> 1341 1342 mac_addr_ad1_31_0 1343 1344 Field only valid when mac_addr_ad1_valid is set 1345 1346 1347 1348 The Least Significant 4 bytes of the Received Frames MAC 1349 Address AD1 1350 1351 <legal all> 1352 1353 mac_addr_ad1_47_32 1354 1355 Field only valid when mac_addr_ad1_valid is set 1356 1357 1358 1359 The 2 most significant bytes of the Received Frames MAC 1360 Address AD1 1361 1362 <legal all> 1363 1364 mac_addr_ad2_15_0 1365 1366 Field only valid when mac_addr_ad2_valid is set 1367 1368 1369 1370 The Least Significant 2 bytes of the Received Frames MAC 1371 Address AD2 1372 1373 <legal all> 1374 1375 mac_addr_ad2_47_16 1376 1377 Field only valid when mac_addr_ad2_valid is set 1378 1379 1380 1381 The 4 most significant bytes of the Received Frames MAC 1382 Address AD2 1383 1384 <legal all> 1385 1386 mac_addr_ad3_31_0 1387 1388 Field only valid when mac_addr_ad3_valid is set 1389 1390 1391 1392 The Least Significant 4 bytes of the Received Frames MAC 1393 Address AD3 1394 1395 <legal all> 1396 1397 mac_addr_ad3_47_32 1398 1399 Field only valid when mac_addr_ad3_valid is set 1400 1401 1402 1403 The 2 most significant bytes of the Received Frames MAC 1404 Address AD3 1405 1406 <legal all> 1407 1408 mpdu_sequence_control_field 1409 1410 1411 1412 1413 The sequence control field of the MPDU 1414 1415 <legal all> 1416 1417 mac_addr_ad4_31_0 1418 1419 Field only valid when mac_addr_ad4_valid is set 1420 1421 1422 1423 The Least Significant 4 bytes of the Received Frames MAC 1424 Address AD4 1425 1426 <legal all> 1427 1428 mac_addr_ad4_47_32 1429 1430 Field only valid when mac_addr_ad4_valid is set 1431 1432 1433 1434 The 2 most significant bytes of the Received Frames MAC 1435 Address AD4 1436 1437 <legal all> 1438 1439 mpdu_qos_control_field 1440 1441 Field only valid when mpdu_qos_control_valid is set 1442 1443 1444 1445 The sequence control field of the MPDU 1446 1447 <legal all> 1448 1449 mpdu_ht_control_field 1450 1451 Field only valid when mpdu_qos_control_valid is set 1452 1453 1454 1455 The HT control field of the MPDU 1456 1457 <legal all> 1458 */ 1459 1460 1461 /* EXTERNAL REFERENCE : struct rxpt_classify_info rxpt_classify_info_details */ 1462 1463 1464 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION 1465 1466 The ID of the REO exit ring where the MSDU frame shall 1467 push after (MPDU level) reordering has finished. 1468 1469 1470 1471 <enum 0 reo_destination_tcl> Reo will push the frame 1472 into the REO2TCL ring 1473 1474 <enum 1 reo_destination_sw1> Reo will push the frame 1475 into the REO2SW1 ring 1476 1477 <enum 2 reo_destination_sw2> Reo will push the frame 1478 into the REO2SW2 ring 1479 1480 <enum 3 reo_destination_sw3> Reo will push the frame 1481 into the REO2SW3 ring 1482 1483 <enum 4 reo_destination_sw4> Reo will push the frame 1484 into the REO2SW4 ring 1485 1486 <enum 5 reo_destination_release> Reo will push the frame 1487 into the REO_release ring 1488 1489 <enum 6 reo_destination_fw> Reo will push the frame into 1490 the REO2FW ring 1491 1492 <enum 7 reo_destination_sw5> Reo will push the frame 1493 into the REO2SW5 ring (REO remaps this in chips without 1494 REO2SW5 ring, e.g. Pine) 1495 1496 <enum 8 reo_destination_sw6> Reo will push the frame 1497 into the REO2SW6 ring (REO remaps this in chips without 1498 REO2SW6 ring, e.g. Pine) 1499 1500 <enum 9 reo_destination_9> REO remaps this <enum 10 1501 reo_destination_10> REO remaps this 1502 1503 <enum 11 reo_destination_11> REO remaps this 1504 1505 <enum 12 reo_destination_12> REO remaps this <enum 13 1506 reo_destination_13> REO remaps this 1507 1508 <enum 14 reo_destination_14> REO remaps this 1509 1510 <enum 15 reo_destination_15> REO remaps this 1511 1512 <enum 16 reo_destination_16> REO remaps this 1513 1514 <enum 17 reo_destination_17> REO remaps this 1515 1516 <enum 18 reo_destination_18> REO remaps this 1517 1518 <enum 19 reo_destination_19> REO remaps this 1519 1520 <enum 20 reo_destination_20> REO remaps this 1521 1522 <enum 21 reo_destination_21> REO remaps this 1523 1524 <enum 22 reo_destination_22> REO remaps this 1525 1526 <enum 23 reo_destination_23> REO remaps this 1527 1528 <enum 24 reo_destination_24> REO remaps this 1529 1530 <enum 25 reo_destination_25> REO remaps this 1531 1532 <enum 26 reo_destination_26> REO remaps this 1533 1534 <enum 27 reo_destination_27> REO remaps this 1535 1536 <enum 28 reo_destination_28> REO remaps this 1537 1538 <enum 29 reo_destination_29> REO remaps this 1539 1540 <enum 30 reo_destination_30> REO remaps this 1541 1542 <enum 31 reo_destination_31> REO remaps this 1543 1544 1545 1546 <legal all> 1547 */ 1548 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 1549 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 1550 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 1551 1552 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB 1553 1554 If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb 1555 is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1, 1556 hash[3:0]} using the chosen Toeplitz hash from Common Parser 1557 if flow search fails. 1558 1559 If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb 1560 's not 2'b00, Rx OLE uses a REO desination indication of 1561 {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz hash 1562 from Common Parser if flow search fails. 1563 1564 This LMAC/peer-based routing is not supported in 1565 Hastings80 and HastingsPrime. 1566 1567 <legal all> 1568 */ 1569 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 1570 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 1571 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 1572 1573 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY 1574 1575 Indication to Rx OLE to enable REO destination routing 1576 based on the chosen Toeplitz hash from Common Parser, in 1577 case flow search fails 1578 1579 <legal all> 1580 */ 1581 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 1582 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 1583 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 1584 1585 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA 1586 1587 Filter pass Unicast data frame (matching 1588 rxpcu_filter_pass and sw_frame_group_Unicast_data) routing 1589 selection 1590 1591 1592 1593 1'b0: source and destination rings are selected from the 1594 RxOLE register settings for the packet type 1595 1596 1597 1598 1'b1: source ring and destination ring is selected from 1599 the rxdma0_source_ring_selection and 1600 rxdma0_destination_ring_selection fields in this STRUCT 1601 1602 <legal all> 1603 */ 1604 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 1605 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 1606 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 1607 1608 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA 1609 1610 Filter pass Multicast data frame (matching 1611 rxpcu_filter_pass and sw_frame_group_Multicast_data) routing 1612 selection 1613 1614 1615 1616 1'b0: source and destination rings are selected from the 1617 RxOLE register settings for the packet type 1618 1619 1620 1621 1'b1: source ring and destination ring is selected from 1622 the rxdma0_source_ring_selection and 1623 rxdma0_destination_ring_selection fields in this STRUCT 1624 1625 <legal all> 1626 */ 1627 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 1628 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 1629 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 1630 1631 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000 1632 1633 Filter pass BAR frame (matching rxpcu_filter_pass and 1634 sw_frame_group_ctrl_1000) routing selection 1635 1636 1637 1638 1'b0: source and destination rings are selected from the 1639 RxOLE register settings for the packet type 1640 1641 1642 1643 1'b1: source ring and destination ring is selected from 1644 the rxdma0_source_ring_selection and 1645 rxdma0_destination_ring_selection fields in this STRUCT 1646 1647 <legal all> 1648 */ 1649 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 1650 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 1651 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 1652 1653 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION 1654 1655 Field only valid when for the received frame type the 1656 corresponding pkt_selection_fp_... bit is set 1657 1658 1659 1660 <enum 0 wbm2rxdma_buf_source_ring> The data buffer for 1661 1662 <enum 1 fw2rxdma_buf_source_ring> The data buffer for 1663 this frame shall be sourced by fw2rxdma buffer source ring. 1664 1665 <enum 2 sw2rxdma_buf_source_ring> The data buffer for 1666 this frame shall be sourced by sw2rxdma buffer source ring. 1667 1668 <enum 3 no_buffer_ring> The frame shall not be written 1669 to any data buffer. 1670 1671 1672 1673 <legal all> 1674 */ 1675 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 1676 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 1677 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800 1678 1679 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION 1680 1681 Field only valid when for the received frame type the 1682 corresponding pkt_selection_fp_... bit is set 1683 1684 1685 1686 <enum 0 rxdma_release_ring> RXDMA0 shall push the frame 1687 to the Release ring. Effectively this means the frame needs 1688 to be dropped. 1689 1690 <enum 1 rxdma2fw_ring> RXDMA0 shall push the frame to 1691 the FW ring. 1692 1693 <enum 2 rxdma2sw_ring> RXDMA0 shall push the frame to 1694 the SW ring. 1695 1696 <enum 3 rxdma2reo_ring> RXDMA0 shall push the frame to 1697 the REO entrance ring. 1698 1699 1700 1701 <legal all> 1702 */ 1703 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 1704 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13 1705 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000 1706 1707 /* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B 1708 1709 <legal 0> 1710 */ 1711 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 1712 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15 1713 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000 1714 1715 /* Description RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0 1716 1717 In case of ndp or phy_err or AST_based_lookup_valid == 1718 0, this field will be set to 0 1719 1720 1721 1722 Address (lower 32 bits) of the REO queue descriptor. 1723 1724 1725 1726 If no Peer entry lookup happened for this frame, the 1727 value wil be set to 0, and the frame shall never be pushed 1728 to REO entrance ring. 1729 1730 <legal all> 1731 */ 1732 #define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 1733 #define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 1734 #define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 1735 1736 /* Description RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32 1737 1738 In case of ndp or phy_err or AST_based_lookup_valid == 1739 0, this field will be set to 0 1740 1741 1742 1743 Address (upper 8 bits) of the REO queue descriptor. 1744 1745 1746 1747 If no Peer entry lookup happened for this frame, the 1748 value wil be set to 0, and the frame shall never be pushed 1749 to REO entrance ring. 1750 1751 <legal all> 1752 */ 1753 #define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 1754 #define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 1755 #define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 1756 1757 /* Description RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER 1758 1759 In case of ndp or phy_err or AST_based_lookup_valid == 1760 0, this field will be set to 0 1761 1762 1763 1764 Indicates the MPDU queue ID to which this MPDU link 1765 descriptor belongs 1766 1767 Used for tracking and debugging 1768 1769 <legal all> 1770 */ 1771 #define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 1772 #define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_LSB 8 1773 #define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 1774 1775 /* Description RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING 1776 1777 Indicates that a delimiter FCS error was found in 1778 between the Previous MPDU and this MPDU. 1779 1780 1781 1782 Note that this is just a warning, and does not mean that 1783 this MPDU is corrupted in any way. If it is, there will be 1784 other errors indicated such as FCS or decrypt errors 1785 1786 1787 1788 In case of ndp or phy_err, this field will indicate at 1789 least one of delimiters located after the last MPDU in the 1790 previous PPDU has been corrupted. 1791 */ 1792 #define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 1793 #define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_LSB 24 1794 #define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_MASK 0x01000000 1795 1796 /* Description RX_MPDU_INFO_2_FIRST_DELIM_ERR 1797 1798 Indicates that the first delimiter had a FCS failure. 1799 Only valid when first_mpdu and first_msdu are set. 1800 1801 1802 1803 */ 1804 #define RX_MPDU_INFO_2_FIRST_DELIM_ERR_OFFSET 0x00000008 1805 #define RX_MPDU_INFO_2_FIRST_DELIM_ERR_LSB 25 1806 #define RX_MPDU_INFO_2_FIRST_DELIM_ERR_MASK 0x02000000 1807 1808 /* Description RX_MPDU_INFO_2_RESERVED_2A 1809 1810 <legal 0> 1811 */ 1812 #define RX_MPDU_INFO_2_RESERVED_2A_OFFSET 0x00000008 1813 #define RX_MPDU_INFO_2_RESERVED_2A_LSB 26 1814 #define RX_MPDU_INFO_2_RESERVED_2A_MASK 0xfc000000 1815 1816 /* Description RX_MPDU_INFO_3_PN_31_0 1817 1818 1819 1820 1821 1822 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 1823 is valid. 1824 1825 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 1826 WEPSeed[1], pn1}. Only pn[47:0] is valid. 1827 1828 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, 1829 pn1, pn0}. Only pn[47:0] is valid. 1830 1831 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, 1832 pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, 1833 pn0}. pn[127:0] are valid. 1834 1835 1836 1837 */ 1838 #define RX_MPDU_INFO_3_PN_31_0_OFFSET 0x0000000c 1839 #define RX_MPDU_INFO_3_PN_31_0_LSB 0 1840 #define RX_MPDU_INFO_3_PN_31_0_MASK 0xffffffff 1841 1842 /* Description RX_MPDU_INFO_4_PN_63_32 1843 1844 1845 1846 1847 Bits [63:32] of the PN number. See description for 1848 pn_31_0. 1849 1850 1851 1852 */ 1853 #define RX_MPDU_INFO_4_PN_63_32_OFFSET 0x00000010 1854 #define RX_MPDU_INFO_4_PN_63_32_LSB 0 1855 #define RX_MPDU_INFO_4_PN_63_32_MASK 0xffffffff 1856 1857 /* Description RX_MPDU_INFO_5_PN_95_64 1858 1859 1860 1861 1862 Bits [95:64] of the PN number. See description for 1863 pn_31_0. 1864 1865 1866 1867 */ 1868 #define RX_MPDU_INFO_5_PN_95_64_OFFSET 0x00000014 1869 #define RX_MPDU_INFO_5_PN_95_64_LSB 0 1870 #define RX_MPDU_INFO_5_PN_95_64_MASK 0xffffffff 1871 1872 /* Description RX_MPDU_INFO_6_PN_127_96 1873 1874 1875 1876 1877 Bits [127:96] of the PN number. See description for 1878 pn_31_0. 1879 1880 1881 1882 */ 1883 #define RX_MPDU_INFO_6_PN_127_96_OFFSET 0x00000018 1884 #define RX_MPDU_INFO_6_PN_127_96_LSB 0 1885 #define RX_MPDU_INFO_6_PN_127_96_MASK 0xffffffff 1886 1887 /* Description RX_MPDU_INFO_7_EPD_EN 1888 1889 Field only valid when AST_based_lookup_valid == 1. 1890 1891 1892 1893 1894 1895 In case of ndp or phy_err or AST_based_lookup_valid == 1896 0, this field will be set to 0 1897 1898 1899 1900 If set to one use EPD instead of LPD 1901 1902 1903 1904 1905 <legal all> 1906 */ 1907 #define RX_MPDU_INFO_7_EPD_EN_OFFSET 0x0000001c 1908 #define RX_MPDU_INFO_7_EPD_EN_LSB 0 1909 #define RX_MPDU_INFO_7_EPD_EN_MASK 0x00000001 1910 1911 /* Description RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED 1912 1913 In case of ndp or phy_err or AST_based_lookup_valid == 1914 0, this field will be set to 0 1915 1916 1917 1918 When set, all frames (data only ?) shall be encrypted. 1919 If not, RX CRYPTO shall set an error flag. 1920 1921 <legal all> 1922 */ 1923 #define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c 1924 #define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 1925 #define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 1926 1927 /* Description RX_MPDU_INFO_7_ENCRYPT_TYPE 1928 1929 In case of ndp or phy_err or AST_based_lookup_valid == 1930 0, this field will be set to 0 1931 1932 1933 1934 Indicates type of decrypt cipher used (as defined in the 1935 peer entry) 1936 1937 1938 1939 <enum 0 wep_40> WEP 40-bit 1940 1941 <enum 1 wep_104> WEP 104-bit 1942 1943 <enum 2 tkip_no_mic> TKIP without MIC 1944 1945 <enum 3 wep_128> WEP 128-bit 1946 1947 <enum 4 tkip_with_mic> TKIP with MIC 1948 1949 <enum 5 wapi> WAPI 1950 1951 <enum 6 aes_ccmp_128> AES CCMP 128 1952 1953 <enum 7 no_cipher> No crypto 1954 1955 <enum 8 aes_ccmp_256> AES CCMP 256 1956 1957 <enum 9 aes_gcmp_128> AES CCMP 128 1958 1959 <enum 10 aes_gcmp_256> AES CCMP 256 1960 1961 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 1962 1963 1964 1965 <enum 12 wep_varied_width> WEP encryption. As for WEP 1966 per keyid the key bit width can vary, the key bit width for 1967 this MPDU will be indicated in field 1968 wep_key_width_for_variable key 1969 1970 <legal 0-12> 1971 */ 1972 #define RX_MPDU_INFO_7_ENCRYPT_TYPE_OFFSET 0x0000001c 1973 #define RX_MPDU_INFO_7_ENCRYPT_TYPE_LSB 2 1974 #define RX_MPDU_INFO_7_ENCRYPT_TYPE_MASK 0x0000003c 1975 1976 /* Description RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY 1977 1978 Field only valid when key_type is set to 1979 wep_varied_width. 1980 1981 1982 1983 This field indicates the size of the wep key for this 1984 MPDU. 1985 1986 1987 1988 <enum 0 wep_varied_width_40> WEP 40-bit 1989 1990 <enum 1 wep_varied_width_104> WEP 104-bit 1991 1992 <enum 2 wep_varied_width_128> WEP 128-bit 1993 1994 1995 1996 <legal 0-2> 1997 */ 1998 #define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c 1999 #define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 2000 #define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 2001 2002 /* Description RX_MPDU_INFO_7_MESH_STA 2003 2004 In case of ndp or phy_err or AST_based_lookup_valid == 2005 0, this field will be set to 0 2006 2007 2008 2009 When set, this is a Mesh (11s) STA. 2010 2011 2012 2013 The interpretation of the A-MSDU 'Length' field in the 2014 MPDU (if any) is decided by the e-numerations below. 2015 2016 2017 2018 <enum 0 MESH_DISABLE> 2019 2020 <enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and 2021 includes the length of Mesh Control. 2022 2023 <enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and 2024 excludes the length of Mesh Control. 2025 2026 <enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian 2027 and excludes the length of Mesh Control. This is 2028 802.11s-compliant. 2029 2030 <legal all> 2031 */ 2032 #define RX_MPDU_INFO_7_MESH_STA_OFFSET 0x0000001c 2033 #define RX_MPDU_INFO_7_MESH_STA_LSB 8 2034 #define RX_MPDU_INFO_7_MESH_STA_MASK 0x00000300 2035 2036 /* Description RX_MPDU_INFO_7_BSSID_HIT 2037 2038 In case of ndp or phy_err or AST_based_lookup_valid == 2039 0, this field will be set to 0 2040 2041 2042 2043 When set, the BSSID of the incoming frame matched one of 2044 the 8 BSSID register values 2045 2046 2047 2048 <legal all> 2049 */ 2050 #define RX_MPDU_INFO_7_BSSID_HIT_OFFSET 0x0000001c 2051 #define RX_MPDU_INFO_7_BSSID_HIT_LSB 10 2052 #define RX_MPDU_INFO_7_BSSID_HIT_MASK 0x00000400 2053 2054 /* Description RX_MPDU_INFO_7_BSSID_NUMBER 2055 2056 Field only valid when bssid_hit is set. 2057 2058 2059 2060 This number indicates which one out of the 8 BSSID 2061 register values matched the incoming frame 2062 2063 <legal all> 2064 */ 2065 #define RX_MPDU_INFO_7_BSSID_NUMBER_OFFSET 0x0000001c 2066 #define RX_MPDU_INFO_7_BSSID_NUMBER_LSB 11 2067 #define RX_MPDU_INFO_7_BSSID_NUMBER_MASK 0x00007800 2068 2069 /* Description RX_MPDU_INFO_7_TID 2070 2071 Field only valid when mpdu_qos_control_valid is set 2072 2073 2074 2075 The TID field in the QoS control field 2076 2077 <legal all> 2078 */ 2079 #define RX_MPDU_INFO_7_TID_OFFSET 0x0000001c 2080 #define RX_MPDU_INFO_7_TID_LSB 15 2081 #define RX_MPDU_INFO_7_TID_MASK 0x00078000 2082 2083 /* Description RX_MPDU_INFO_7_RESERVED_7A 2084 2085 <legal 0> 2086 */ 2087 #define RX_MPDU_INFO_7_RESERVED_7A_OFFSET 0x0000001c 2088 #define RX_MPDU_INFO_7_RESERVED_7A_LSB 19 2089 #define RX_MPDU_INFO_7_RESERVED_7A_MASK 0xfff80000 2090 2091 /* Description RX_MPDU_INFO_8_PEER_META_DATA 2092 2093 In case of ndp or phy_err or AST_based_lookup_valid == 2094 0, this field will be set to 0 2095 2096 2097 2098 Meta data that SW has programmed in the Peer table entry 2099 of the transmitting STA. 2100 2101 <legal all> 2102 */ 2103 #define RX_MPDU_INFO_8_PEER_META_DATA_OFFSET 0x00000020 2104 #define RX_MPDU_INFO_8_PEER_META_DATA_LSB 0 2105 #define RX_MPDU_INFO_8_PEER_META_DATA_MASK 0xffffffff 2106 2107 /* Description RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY 2108 2109 Field indicates what the reason was that this MPDU frame 2110 was allowed to come into the receive path by RXPCU 2111 2112 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 2113 frame filter programming of rxpcu 2114 2115 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 2116 regular frame filter and would have been dropped, were it 2117 not for the frame fitting into the 'monitor_client' 2118 category. 2119 2120 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 2121 regular frame filter and also did not pass the 2122 rxpcu_monitor_client filter. It would have been dropped 2123 accept that it did pass the 'monitor_other' category. 2124 2125 2126 2127 Note: for ndp frame, if it was expected because the 2128 preceding NDPA was filter_pass, the setting 2129 rxpcu_filter_pass will be used. This setting will also be 2130 used for every ndp frame in case Promiscuous mode is 2131 enabled. 2132 2133 2134 2135 In case promiscuous is not enabled, and an NDP is not 2136 preceded by a NPDA filter pass frame, the only other setting 2137 that could appear here for the NDP is rxpcu_monitor_other. 2138 2139 (rxpcu has a configuration bit specifically for this 2140 scenario) 2141 2142 2143 2144 Note: for 2145 2146 <legal 0-2> 2147 */ 2148 #define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 2149 #define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 2150 #define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 2151 2152 /* Description RX_MPDU_INFO_9_SW_FRAME_GROUP_ID 2153 2154 SW processes frames based on certain classifications. 2155 This field indicates to what sw classification this MPDU is 2156 mapped. 2157 2158 The classification is given in priority order 2159 2160 2161 2162 <enum 0 sw_frame_group_NDP_frame> Note: The 2163 corresponding Rxpcu_Mpdu_filter_in_category can be 2164 rxpcu_filter_pass or rxpcu_monitor_other 2165 2166 2167 2168 <enum 1 sw_frame_group_Multicast_data> 2169 2170 <enum 2 sw_frame_group_Unicast_data> 2171 2172 <enum 3 sw_frame_group_Null_data > This includes mpdus 2173 of type Data Null as well as QoS Data Null 2174 2175 2176 2177 <enum 4 sw_frame_group_mgmt_0000 > 2178 2179 <enum 5 sw_frame_group_mgmt_0001 > 2180 2181 <enum 6 sw_frame_group_mgmt_0010 > 2182 2183 <enum 7 sw_frame_group_mgmt_0011 > 2184 2185 <enum 8 sw_frame_group_mgmt_0100 > 2186 2187 <enum 9 sw_frame_group_mgmt_0101 > 2188 2189 <enum 10 sw_frame_group_mgmt_0110 > 2190 2191 <enum 11 sw_frame_group_mgmt_0111 > 2192 2193 <enum 12 sw_frame_group_mgmt_1000 > 2194 2195 <enum 13 sw_frame_group_mgmt_1001 > 2196 2197 <enum 14 sw_frame_group_mgmt_1010 > 2198 2199 <enum 15 sw_frame_group_mgmt_1011 > 2200 2201 <enum 16 sw_frame_group_mgmt_1100 > 2202 2203 <enum 17 sw_frame_group_mgmt_1101 > 2204 2205 <enum 18 sw_frame_group_mgmt_1110 > 2206 2207 <enum 19 sw_frame_group_mgmt_1111 > 2208 2209 2210 2211 <enum 20 sw_frame_group_ctrl_0000 > 2212 2213 <enum 21 sw_frame_group_ctrl_0001 > 2214 2215 <enum 22 sw_frame_group_ctrl_0010 > 2216 2217 <enum 23 sw_frame_group_ctrl_0011 > 2218 2219 <enum 24 sw_frame_group_ctrl_0100 > 2220 2221 <enum 25 sw_frame_group_ctrl_0101 > 2222 2223 <enum 26 sw_frame_group_ctrl_0110 > 2224 2225 <enum 27 sw_frame_group_ctrl_0111 > 2226 2227 <enum 28 sw_frame_group_ctrl_1000 > 2228 2229 <enum 29 sw_frame_group_ctrl_1001 > 2230 2231 <enum 30 sw_frame_group_ctrl_1010 > 2232 2233 <enum 31 sw_frame_group_ctrl_1011 > 2234 2235 <enum 32 sw_frame_group_ctrl_1100 > 2236 2237 <enum 33 sw_frame_group_ctrl_1101 > 2238 2239 <enum 34 sw_frame_group_ctrl_1110 > 2240 2241 <enum 35 sw_frame_group_ctrl_1111 > 2242 2243 2244 2245 <enum 36 sw_frame_group_unsupported> This covers type 3 2246 and protocol version != 0 2247 2248 Note: The corresponding Rxpcu_Mpdu_filter_in_category 2249 can only be rxpcu_monitor_other 2250 2251 2252 2253 2254 Note: The corresponding Rxpcu_Mpdu_filter_in_category 2255 can be rxpcu_filter_pass 2256 2257 2258 2259 <legal 0-37> 2260 */ 2261 #define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET 0x00000024 2262 #define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB 2 2263 #define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK 0x000001fc 2264 2265 /* Description RX_MPDU_INFO_9_NDP_FRAME 2266 2267 When set, the received frame was an NDP frame, and thus 2268 there will be no MPDU data. 2269 2270 <legal all> 2271 */ 2272 #define RX_MPDU_INFO_9_NDP_FRAME_OFFSET 0x00000024 2273 #define RX_MPDU_INFO_9_NDP_FRAME_LSB 9 2274 #define RX_MPDU_INFO_9_NDP_FRAME_MASK 0x00000200 2275 2276 /* Description RX_MPDU_INFO_9_PHY_ERR 2277 2278 When set, a PHY error was received before MAC received 2279 any data, and thus there will be no MPDU data. 2280 2281 <legal all> 2282 */ 2283 #define RX_MPDU_INFO_9_PHY_ERR_OFFSET 0x00000024 2284 #define RX_MPDU_INFO_9_PHY_ERR_LSB 10 2285 #define RX_MPDU_INFO_9_PHY_ERR_MASK 0x00000400 2286 2287 /* Description RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER 2288 2289 When set, a PHY error was received before MAC received 2290 the complete MPDU header which was needed for proper 2291 decoding 2292 2293 <legal all> 2294 */ 2295 #define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 2296 #define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_LSB 11 2297 #define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 2298 2299 /* Description RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR 2300 2301 Set when RXPCU detected a version error in the Frame 2302 control field 2303 2304 <legal all> 2305 */ 2306 #define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 2307 #define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_LSB 12 2308 #define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_MASK 0x00001000 2309 2310 /* Description RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID 2311 2312 When set, AST based lookup for this frame has found a 2313 valid result. 2314 2315 2316 2317 Note that for NDP frame this will never be set 2318 2319 <legal all> 2320 */ 2321 #define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 2322 #define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_LSB 13 2323 #define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_MASK 0x00002000 2324 2325 /* Description RX_MPDU_INFO_9_RESERVED_9A 2326 2327 <legal 0> 2328 */ 2329 #define RX_MPDU_INFO_9_RESERVED_9A_OFFSET 0x00000024 2330 #define RX_MPDU_INFO_9_RESERVED_9A_LSB 14 2331 #define RX_MPDU_INFO_9_RESERVED_9A_MASK 0x0000c000 2332 2333 /* Description RX_MPDU_INFO_9_PHY_PPDU_ID 2334 2335 A ppdu counter value that PHY increments for every PPDU 2336 received. The counter value wraps around 2337 2338 <legal all> 2339 */ 2340 #define RX_MPDU_INFO_9_PHY_PPDU_ID_OFFSET 0x00000024 2341 #define RX_MPDU_INFO_9_PHY_PPDU_ID_LSB 16 2342 #define RX_MPDU_INFO_9_PHY_PPDU_ID_MASK 0xffff0000 2343 2344 /* Description RX_MPDU_INFO_10_AST_INDEX 2345 2346 This field indicates the index of the AST entry 2347 corresponding to this MPDU. It is provided by the GSE module 2348 instantiated in RXPCU. 2349 2350 A value of 0xFFFF indicates an invalid AST index, 2351 meaning that No AST entry was found or NO AST search was 2352 performed 2353 2354 2355 2356 In case of ndp or phy_err, this field will be set to 2357 0xFFFF 2358 2359 <legal all> 2360 */ 2361 #define RX_MPDU_INFO_10_AST_INDEX_OFFSET 0x00000028 2362 #define RX_MPDU_INFO_10_AST_INDEX_LSB 0 2363 #define RX_MPDU_INFO_10_AST_INDEX_MASK 0x0000ffff 2364 2365 /* Description RX_MPDU_INFO_10_SW_PEER_ID 2366 2367 In case of ndp or phy_err or AST_based_lookup_valid == 2368 0, this field will be set to 0 2369 2370 2371 2372 This field indicates a unique peer identifier. It is set 2373 equal to field 'sw_peer_id' from the AST entry 2374 2375 2376 2377 <legal all> 2378 */ 2379 #define RX_MPDU_INFO_10_SW_PEER_ID_OFFSET 0x00000028 2380 #define RX_MPDU_INFO_10_SW_PEER_ID_LSB 16 2381 #define RX_MPDU_INFO_10_SW_PEER_ID_MASK 0xffff0000 2382 2383 /* Description RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID 2384 2385 When set, the field Mpdu_Frame_control_field has valid 2386 information 2387 2388 2389 2390 2391 <legal all> 2392 */ 2393 #define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c 2394 #define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB 0 2395 #define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 2396 2397 /* Description RX_MPDU_INFO_11_MPDU_DURATION_VALID 2398 2399 When set, the field Mpdu_duration_field has valid 2400 information 2401 2402 2403 2404 2405 <legal all> 2406 */ 2407 #define RX_MPDU_INFO_11_MPDU_DURATION_VALID_OFFSET 0x0000002c 2408 #define RX_MPDU_INFO_11_MPDU_DURATION_VALID_LSB 1 2409 #define RX_MPDU_INFO_11_MPDU_DURATION_VALID_MASK 0x00000002 2410 2411 /* Description RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID 2412 2413 When set, the fields mac_addr_ad1_..... have valid 2414 information 2415 2416 2417 2418 2419 <legal all> 2420 */ 2421 #define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c 2422 #define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB 2 2423 #define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK 0x00000004 2424 2425 /* Description RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID 2426 2427 When set, the fields mac_addr_ad2_..... have valid 2428 information 2429 2430 2431 2432 2433 2434 2435 2436 <legal all> 2437 */ 2438 #define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c 2439 #define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB 3 2440 #define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK 0x00000008 2441 2442 /* Description RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID 2443 2444 When set, the fields mac_addr_ad3_..... have valid 2445 information 2446 2447 2448 2449 2450 2451 2452 2453 <legal all> 2454 */ 2455 #define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c 2456 #define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB 4 2457 #define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK 0x00000010 2458 2459 /* Description RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID 2460 2461 When set, the fields mac_addr_ad4_..... have valid 2462 information 2463 2464 2465 2466 2467 2468 2469 2470 <legal all> 2471 */ 2472 #define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c 2473 #define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB 5 2474 #define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK 0x00000020 2475 2476 /* Description RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID 2477 2478 When set, the fields mpdu_sequence_control_field and 2479 mpdu_sequence_number have valid information as well as field 2480 2481 2482 2483 For MPDUs without a sequence control field, this field 2484 will not be set. 2485 2486 2487 2488 2489 <legal all> 2490 */ 2491 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c 2492 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 2493 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 2494 2495 /* Description RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID 2496 2497 When set, the field mpdu_qos_control_field has valid 2498 information 2499 2500 2501 2502 For MPDUs without a QoS control field, this field will 2503 not be set. 2504 2505 2506 2507 2508 <legal all> 2509 */ 2510 #define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c 2511 #define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB 7 2512 #define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 2513 2514 /* Description RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID 2515 2516 When set, the field mpdu_HT_control_field has valid 2517 information 2518 2519 2520 2521 For MPDUs without a HT control field, this field will 2522 not be set. 2523 2524 2525 2526 2527 <legal all> 2528 */ 2529 #define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c 2530 #define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_LSB 8 2531 #define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_MASK 0x00000100 2532 2533 /* Description RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID 2534 2535 When set, the encryption related info fields, like IV 2536 and PN are valid 2537 2538 2539 2540 For MPDUs that are not encrypted, this will not be set. 2541 2542 2543 2544 2545 <legal all> 2546 */ 2547 #define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c 2548 #define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB 9 2549 #define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 2550 2551 /* Description RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER 2552 2553 Field only valid when Mpdu_sequence_control_valid is set 2554 AND Fragment_flag is set 2555 2556 2557 2558 The fragment number from the 802.11 header 2559 2560 2561 2562 <legal all> 2563 */ 2564 #define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c 2565 #define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_LSB 10 2566 #define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 2567 2568 /* Description RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG 2569 2570 The More Fragment bit setting from the MPDU header of 2571 the received frame 2572 2573 2574 2575 <legal all> 2576 */ 2577 #define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c 2578 #define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_LSB 14 2579 #define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_MASK 0x00004000 2580 2581 /* Description RX_MPDU_INFO_11_RESERVED_11A 2582 2583 <legal 0> 2584 */ 2585 #define RX_MPDU_INFO_11_RESERVED_11A_OFFSET 0x0000002c 2586 #define RX_MPDU_INFO_11_RESERVED_11A_LSB 15 2587 #define RX_MPDU_INFO_11_RESERVED_11A_MASK 0x00008000 2588 2589 /* Description RX_MPDU_INFO_11_FR_DS 2590 2591 Field only valid when Mpdu_frame_control_valid is set 2592 2593 2594 2595 Set if the from DS bit is set in the frame control. 2596 2597 <legal all> 2598 */ 2599 #define RX_MPDU_INFO_11_FR_DS_OFFSET 0x0000002c 2600 #define RX_MPDU_INFO_11_FR_DS_LSB 16 2601 #define RX_MPDU_INFO_11_FR_DS_MASK 0x00010000 2602 2603 /* Description RX_MPDU_INFO_11_TO_DS 2604 2605 Field only valid when Mpdu_frame_control_valid is set 2606 2607 2608 2609 Set if the to DS bit is set in the frame control. 2610 2611 <legal all> 2612 */ 2613 #define RX_MPDU_INFO_11_TO_DS_OFFSET 0x0000002c 2614 #define RX_MPDU_INFO_11_TO_DS_LSB 17 2615 #define RX_MPDU_INFO_11_TO_DS_MASK 0x00020000 2616 2617 /* Description RX_MPDU_INFO_11_ENCRYPTED 2618 2619 Field only valid when Mpdu_frame_control_valid is set. 2620 2621 2622 2623 Protected bit from the frame control. 2624 2625 <legal all> 2626 */ 2627 #define RX_MPDU_INFO_11_ENCRYPTED_OFFSET 0x0000002c 2628 #define RX_MPDU_INFO_11_ENCRYPTED_LSB 18 2629 #define RX_MPDU_INFO_11_ENCRYPTED_MASK 0x00040000 2630 2631 /* Description RX_MPDU_INFO_11_MPDU_RETRY 2632 2633 Field only valid when Mpdu_frame_control_valid is set. 2634 2635 2636 2637 Retry bit from the frame control. Only valid when 2638 first_msdu is set. 2639 2640 <legal all> 2641 */ 2642 #define RX_MPDU_INFO_11_MPDU_RETRY_OFFSET 0x0000002c 2643 #define RX_MPDU_INFO_11_MPDU_RETRY_LSB 19 2644 #define RX_MPDU_INFO_11_MPDU_RETRY_MASK 0x00080000 2645 2646 /* Description RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER 2647 2648 Field only valid when Mpdu_sequence_control_valid is 2649 set. 2650 2651 2652 2653 The sequence number from the 802.11 header. 2654 2655 <legal all> 2656 */ 2657 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c 2658 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB 20 2659 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 2660 2661 /* Description RX_MPDU_INFO_12_KEY_ID_OCTET 2662 2663 2664 2665 2666 The key ID octet from the IV. 2667 2668 2669 2670 In case of ndp or phy_err or AST_based_lookup_valid == 2671 0, this field will be set to 0 2672 2673 <legal all> 2674 */ 2675 #define RX_MPDU_INFO_12_KEY_ID_OCTET_OFFSET 0x00000030 2676 #define RX_MPDU_INFO_12_KEY_ID_OCTET_LSB 0 2677 #define RX_MPDU_INFO_12_KEY_ID_OCTET_MASK 0x000000ff 2678 2679 /* Description RX_MPDU_INFO_12_NEW_PEER_ENTRY 2680 2681 In case of ndp or phy_err or AST_based_lookup_valid == 2682 0, this field will be set to 0 2683 2684 2685 2686 Set if new RX_PEER_ENTRY TLV follows. If clear, 2687 RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either 2688 uses old peer entry or not decrypt. 2689 2690 <legal all> 2691 */ 2692 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_OFFSET 0x00000030 2693 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_LSB 8 2694 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_MASK 0x00000100 2695 2696 /* Description RX_MPDU_INFO_12_DECRYPT_NEEDED 2697 2698 In case of ndp or phy_err or AST_based_lookup_valid == 2699 0, this field will be set to 0 2700 2701 2702 2703 Set if decryption is needed. 2704 2705 2706 2707 Note: 2708 2709 When RXPCU sets bit 'ast_index_not_found' and/or 2710 ast_index_timeout', RXPCU will also ensure that this bit is 2711 NOT set 2712 2713 CRYPTO for that reason only needs to evaluate this bit 2714 and non of the other ones. 2715 2716 <legal all> 2717 */ 2718 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_OFFSET 0x00000030 2719 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_LSB 9 2720 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_MASK 0x00000200 2721 2722 /* Description RX_MPDU_INFO_12_DECAP_TYPE 2723 2724 In case of ndp or phy_err or AST_based_lookup_valid == 2725 0, this field will be set to 0 2726 2727 2728 2729 Used by the OLE during decapsulation. 2730 2731 2732 2733 Indicates the decapsulation that HW will perform: 2734 2735 2736 2737 <enum 0 RAW> No encapsulation 2738 2739 <enum 1 Native_WiFi> 2740 2741 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses 2742 SNAP/LLC) 2743 2744 <enum 3 802_3> Indicate Ethernet 2745 2746 2747 2748 <legal all> 2749 */ 2750 #define RX_MPDU_INFO_12_DECAP_TYPE_OFFSET 0x00000030 2751 #define RX_MPDU_INFO_12_DECAP_TYPE_LSB 10 2752 #define RX_MPDU_INFO_12_DECAP_TYPE_MASK 0x00000c00 2753 2754 /* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING 2755 2756 In case of ndp or phy_err or AST_based_lookup_valid == 2757 0, this field will be set to 0 2758 2759 2760 2761 Insert 4 byte of all zeros as VLAN tag if the rx payload 2762 does not have VLAN. Used during decapsulation. 2763 2764 <legal all> 2765 */ 2766 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 2767 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 2768 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 2769 2770 /* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING 2771 2772 In case of ndp or phy_err or AST_based_lookup_valid == 2773 0, this field will be set to 0 2774 2775 2776 2777 Insert 4 byte of all zeros as double VLAN tag if the rx 2778 payload does not have VLAN. Used during 2779 2780 <legal all> 2781 */ 2782 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 2783 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 2784 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 2785 2786 /* Description RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP 2787 2788 In case of ndp or phy_err or AST_based_lookup_valid == 2789 0, this field will be set to 0 2790 2791 2792 2793 Strip the VLAN during decapsulation. Used by the OLE. 2794 2795 <legal all> 2796 */ 2797 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 2798 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_LSB 14 2799 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 2800 2801 /* Description RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP 2802 2803 In case of ndp or phy_err or AST_based_lookup_valid == 2804 0, this field will be set to 0 2805 2806 2807 2808 Strip the double VLAN during decapsulation. Used by 2809 the OLE. 2810 2811 <legal all> 2812 */ 2813 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 2814 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_LSB 15 2815 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 2816 2817 /* Description RX_MPDU_INFO_12_PRE_DELIM_COUNT 2818 2819 The number of delimiters before this MPDU. 2820 2821 2822 2823 Note that this number is cleared at PPDU start. 2824 2825 2826 2827 If this MPDU is the first received MPDU in the PPDU and 2828 this MPDU gets filtered-in, this field will indicate the 2829 number of delimiters located after the last MPDU in the 2830 previous PPDU. 2831 2832 2833 2834 If this MPDU is located after the first received MPDU in 2835 an PPDU, this field will indicate the number of delimiters 2836 located between the previous MPDU and this MPDU. 2837 2838 2839 2840 In case of ndp or phy_err, this field will indicate the 2841 number of delimiters located after the last MPDU in the 2842 previous PPDU. 2843 2844 <legal all> 2845 */ 2846 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_OFFSET 0x00000030 2847 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_LSB 16 2848 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_MASK 0x0fff0000 2849 2850 /* Description RX_MPDU_INFO_12_AMPDU_FLAG 2851 2852 When set, received frame was part of an A-MPDU. 2853 2854 2855 2856 2857 <legal all> 2858 */ 2859 #define RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET 0x00000030 2860 #define RX_MPDU_INFO_12_AMPDU_FLAG_LSB 28 2861 #define RX_MPDU_INFO_12_AMPDU_FLAG_MASK 0x10000000 2862 2863 /* Description RX_MPDU_INFO_12_BAR_FRAME 2864 2865 In case of ndp or phy_err or AST_based_lookup_valid == 2866 0, this field will be set to 0 2867 2868 2869 2870 When set, received frame is a BAR frame 2871 2872 <legal all> 2873 */ 2874 #define RX_MPDU_INFO_12_BAR_FRAME_OFFSET 0x00000030 2875 #define RX_MPDU_INFO_12_BAR_FRAME_LSB 29 2876 #define RX_MPDU_INFO_12_BAR_FRAME_MASK 0x20000000 2877 2878 /* Description RX_MPDU_INFO_12_RAW_MPDU 2879 2880 Consumer: SW 2881 2882 Producer: RXOLE 2883 2884 2885 2886 RXPCU sets this field to 0 and RXOLE overwrites it. 2887 2888 2889 2890 Set to 1 by RXOLE when it has not performed any 802.11 2891 to Ethernet/Natvie WiFi header conversion on this MPDU. 2892 2893 <legal all> 2894 */ 2895 #define RX_MPDU_INFO_12_RAW_MPDU_OFFSET 0x00000030 2896 #define RX_MPDU_INFO_12_RAW_MPDU_LSB 30 2897 #define RX_MPDU_INFO_12_RAW_MPDU_MASK 0x40000000 2898 2899 /* Description RX_MPDU_INFO_12_RESERVED_12 2900 2901 <legal 0> 2902 */ 2903 #define RX_MPDU_INFO_12_RESERVED_12_OFFSET 0x00000030 2904 #define RX_MPDU_INFO_12_RESERVED_12_LSB 31 2905 #define RX_MPDU_INFO_12_RESERVED_12_MASK 0x80000000 2906 2907 /* Description RX_MPDU_INFO_13_MPDU_LENGTH 2908 2909 In case of ndp or phy_err this field will be set to 0 2910 2911 2912 2913 MPDU length before decapsulation. 2914 2915 <legal all> 2916 */ 2917 #define RX_MPDU_INFO_13_MPDU_LENGTH_OFFSET 0x00000034 2918 #define RX_MPDU_INFO_13_MPDU_LENGTH_LSB 0 2919 #define RX_MPDU_INFO_13_MPDU_LENGTH_MASK 0x00003fff 2920 2921 /* Description RX_MPDU_INFO_13_FIRST_MPDU 2922 2923 See definition in RX attention descriptor 2924 2925 2926 2927 In case of ndp or phy_err, this field will be set. Note 2928 however that there will not actually be any data contents in 2929 the MPDU. 2930 2931 <legal all> 2932 */ 2933 #define RX_MPDU_INFO_13_FIRST_MPDU_OFFSET 0x00000034 2934 #define RX_MPDU_INFO_13_FIRST_MPDU_LSB 14 2935 #define RX_MPDU_INFO_13_FIRST_MPDU_MASK 0x00004000 2936 2937 /* Description RX_MPDU_INFO_13_MCAST_BCAST 2938 2939 In case of ndp or phy_err or Phy_err_during_mpdu_header 2940 this field will be set to 0 2941 2942 2943 2944 See definition in RX attention descriptor 2945 2946 <legal all> 2947 */ 2948 #define RX_MPDU_INFO_13_MCAST_BCAST_OFFSET 0x00000034 2949 #define RX_MPDU_INFO_13_MCAST_BCAST_LSB 15 2950 #define RX_MPDU_INFO_13_MCAST_BCAST_MASK 0x00008000 2951 2952 /* Description RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND 2953 2954 In case of ndp or phy_err or Phy_err_during_mpdu_header 2955 this field will be set to 0 2956 2957 2958 2959 See definition in RX attention descriptor 2960 2961 <legal all> 2962 */ 2963 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 2964 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_LSB 16 2965 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_MASK 0x00010000 2966 2967 /* Description RX_MPDU_INFO_13_AST_INDEX_TIMEOUT 2968 2969 In case of ndp or phy_err or Phy_err_during_mpdu_header 2970 this field will be set to 0 2971 2972 2973 2974 See definition in RX attention descriptor 2975 2976 <legal all> 2977 */ 2978 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_OFFSET 0x00000034 2979 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_LSB 17 2980 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_MASK 0x00020000 2981 2982 /* Description RX_MPDU_INFO_13_POWER_MGMT 2983 2984 In case of ndp or phy_err or Phy_err_during_mpdu_header 2985 this field will be set to 0 2986 2987 2988 2989 See definition in RX attention descriptor 2990 2991 <legal all> 2992 */ 2993 #define RX_MPDU_INFO_13_POWER_MGMT_OFFSET 0x00000034 2994 #define RX_MPDU_INFO_13_POWER_MGMT_LSB 18 2995 #define RX_MPDU_INFO_13_POWER_MGMT_MASK 0x00040000 2996 2997 /* Description RX_MPDU_INFO_13_NON_QOS 2998 2999 In case of ndp or phy_err or Phy_err_during_mpdu_header 3000 this field will be set to 1 3001 3002 3003 3004 See definition in RX attention descriptor 3005 3006 <legal all> 3007 */ 3008 #define RX_MPDU_INFO_13_NON_QOS_OFFSET 0x00000034 3009 #define RX_MPDU_INFO_13_NON_QOS_LSB 19 3010 #define RX_MPDU_INFO_13_NON_QOS_MASK 0x00080000 3011 3012 /* Description RX_MPDU_INFO_13_NULL_DATA 3013 3014 In case of ndp or phy_err or Phy_err_during_mpdu_header 3015 this field will be set to 0 3016 3017 3018 3019 See definition in RX attention descriptor 3020 3021 <legal all> 3022 */ 3023 #define RX_MPDU_INFO_13_NULL_DATA_OFFSET 0x00000034 3024 #define RX_MPDU_INFO_13_NULL_DATA_LSB 20 3025 #define RX_MPDU_INFO_13_NULL_DATA_MASK 0x00100000 3026 3027 /* Description RX_MPDU_INFO_13_MGMT_TYPE 3028 3029 In case of ndp or phy_err or Phy_err_during_mpdu_header 3030 this field will be set to 0 3031 3032 3033 3034 See definition in RX attention descriptor 3035 3036 <legal all> 3037 */ 3038 #define RX_MPDU_INFO_13_MGMT_TYPE_OFFSET 0x00000034 3039 #define RX_MPDU_INFO_13_MGMT_TYPE_LSB 21 3040 #define RX_MPDU_INFO_13_MGMT_TYPE_MASK 0x00200000 3041 3042 /* Description RX_MPDU_INFO_13_CTRL_TYPE 3043 3044 In case of ndp or phy_err or Phy_err_during_mpdu_header 3045 this field will be set to 0 3046 3047 3048 3049 See definition in RX attention descriptor 3050 3051 <legal all> 3052 */ 3053 #define RX_MPDU_INFO_13_CTRL_TYPE_OFFSET 0x00000034 3054 #define RX_MPDU_INFO_13_CTRL_TYPE_LSB 22 3055 #define RX_MPDU_INFO_13_CTRL_TYPE_MASK 0x00400000 3056 3057 /* Description RX_MPDU_INFO_13_MORE_DATA 3058 3059 In case of ndp or phy_err or Phy_err_during_mpdu_header 3060 this field will be set to 0 3061 3062 3063 3064 See definition in RX attention descriptor 3065 3066 <legal all> 3067 */ 3068 #define RX_MPDU_INFO_13_MORE_DATA_OFFSET 0x00000034 3069 #define RX_MPDU_INFO_13_MORE_DATA_LSB 23 3070 #define RX_MPDU_INFO_13_MORE_DATA_MASK 0x00800000 3071 3072 /* Description RX_MPDU_INFO_13_EOSP 3073 3074 In case of ndp or phy_err or Phy_err_during_mpdu_header 3075 this field will be set to 0 3076 3077 3078 3079 See definition in RX attention descriptor 3080 3081 <legal all> 3082 */ 3083 #define RX_MPDU_INFO_13_EOSP_OFFSET 0x00000034 3084 #define RX_MPDU_INFO_13_EOSP_LSB 24 3085 #define RX_MPDU_INFO_13_EOSP_MASK 0x01000000 3086 3087 /* Description RX_MPDU_INFO_13_FRAGMENT_FLAG 3088 3089 In case of ndp or phy_err or Phy_err_during_mpdu_header 3090 this field will be set to 0 3091 3092 3093 3094 See definition in RX attention descriptor 3095 3096 <legal all> 3097 */ 3098 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_OFFSET 0x00000034 3099 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_LSB 25 3100 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_MASK 0x02000000 3101 3102 /* Description RX_MPDU_INFO_13_ORDER 3103 3104 In case of ndp or phy_err or Phy_err_during_mpdu_header 3105 this field will be set to 0 3106 3107 3108 3109 See definition in RX attention descriptor 3110 3111 3112 3113 <legal all> 3114 */ 3115 #define RX_MPDU_INFO_13_ORDER_OFFSET 0x00000034 3116 #define RX_MPDU_INFO_13_ORDER_LSB 26 3117 #define RX_MPDU_INFO_13_ORDER_MASK 0x04000000 3118 3119 /* Description RX_MPDU_INFO_13_U_APSD_TRIGGER 3120 3121 In case of ndp or phy_err or Phy_err_during_mpdu_header 3122 this field will be set to 0 3123 3124 3125 3126 See definition in RX attention descriptor 3127 3128 <legal all> 3129 */ 3130 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_OFFSET 0x00000034 3131 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_LSB 27 3132 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_MASK 0x08000000 3133 3134 /* Description RX_MPDU_INFO_13_ENCRYPT_REQUIRED 3135 3136 In case of ndp or phy_err or Phy_err_during_mpdu_header 3137 this field will be set to 0 3138 3139 3140 3141 See definition in RX attention descriptor 3142 3143 <legal all> 3144 */ 3145 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_OFFSET 0x00000034 3146 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_LSB 28 3147 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_MASK 0x10000000 3148 3149 /* Description RX_MPDU_INFO_13_DIRECTED 3150 3151 In case of ndp or phy_err or Phy_err_during_mpdu_header 3152 this field will be set to 0 3153 3154 3155 3156 See definition in RX attention descriptor 3157 3158 <legal all> 3159 */ 3160 #define RX_MPDU_INFO_13_DIRECTED_OFFSET 0x00000034 3161 #define RX_MPDU_INFO_13_DIRECTED_LSB 29 3162 #define RX_MPDU_INFO_13_DIRECTED_MASK 0x20000000 3163 3164 /* Description RX_MPDU_INFO_13_AMSDU_PRESENT 3165 3166 Field only valid when Mpdu_qos_control_valid is set 3167 3168 3169 3170 The 'amsdu_present' bit within the QoS control field of 3171 the MPDU 3172 3173 <legal all> 3174 */ 3175 #define RX_MPDU_INFO_13_AMSDU_PRESENT_OFFSET 0x00000034 3176 #define RX_MPDU_INFO_13_AMSDU_PRESENT_LSB 30 3177 #define RX_MPDU_INFO_13_AMSDU_PRESENT_MASK 0x40000000 3178 3179 /* Description RX_MPDU_INFO_13_RESERVED_13 3180 3181 <legal 0> 3182 */ 3183 #define RX_MPDU_INFO_13_RESERVED_13_OFFSET 0x00000034 3184 #define RX_MPDU_INFO_13_RESERVED_13_LSB 31 3185 #define RX_MPDU_INFO_13_RESERVED_13_MASK 0x80000000 3186 3187 /* Description RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD 3188 3189 Field only valid when Mpdu_frame_control_valid is set 3190 3191 3192 3193 The frame control field of this received MPDU. 3194 3195 3196 3197 Field only valid when Ndp_frame and phy_err are NOT set 3198 3199 3200 3201 Bytes 0 + 1 of the received MPDU 3202 3203 <legal all> 3204 */ 3205 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 3206 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB 0 3207 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff 3208 3209 /* Description RX_MPDU_INFO_14_MPDU_DURATION_FIELD 3210 3211 Field only valid when Mpdu_duration_valid is set 3212 3213 3214 3215 The duration field of this received MPDU. 3216 3217 <legal all> 3218 */ 3219 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_OFFSET 0x00000038 3220 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_LSB 16 3221 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_MASK 0xffff0000 3222 3223 /* Description RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0 3224 3225 Field only valid when mac_addr_ad1_valid is set 3226 3227 3228 3229 The Least Significant 4 bytes of the Received Frames MAC 3230 Address AD1 3231 3232 <legal all> 3233 */ 3234 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c 3235 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB 0 3236 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK 0xffffffff 3237 3238 /* Description RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32 3239 3240 Field only valid when mac_addr_ad1_valid is set 3241 3242 3243 3244 The 2 most significant bytes of the Received Frames MAC 3245 Address AD1 3246 3247 <legal all> 3248 */ 3249 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 3250 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB 0 3251 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK 0x0000ffff 3252 3253 /* Description RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0 3254 3255 Field only valid when mac_addr_ad2_valid is set 3256 3257 3258 3259 The Least Significant 2 bytes of the Received Frames MAC 3260 Address AD2 3261 3262 <legal all> 3263 */ 3264 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 3265 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB 16 3266 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK 0xffff0000 3267 3268 /* Description RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16 3269 3270 Field only valid when mac_addr_ad2_valid is set 3271 3272 3273 3274 The 4 most significant bytes of the Received Frames MAC 3275 Address AD2 3276 3277 <legal all> 3278 */ 3279 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 3280 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB 0 3281 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK 0xffffffff 3282 3283 /* Description RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0 3284 3285 Field only valid when mac_addr_ad3_valid is set 3286 3287 3288 3289 The Least Significant 4 bytes of the Received Frames MAC 3290 Address AD3 3291 3292 <legal all> 3293 */ 3294 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 3295 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB 0 3296 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK 0xffffffff 3297 3298 /* Description RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32 3299 3300 Field only valid when mac_addr_ad3_valid is set 3301 3302 3303 3304 The 2 most significant bytes of the Received Frames MAC 3305 Address AD3 3306 3307 <legal all> 3308 */ 3309 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c 3310 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB 0 3311 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK 0x0000ffff 3312 3313 /* Description RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD 3314 3315 3316 3317 3318 The sequence control field of the MPDU 3319 3320 <legal all> 3321 */ 3322 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c 3323 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 3324 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 3325 3326 /* Description RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0 3327 3328 Field only valid when mac_addr_ad4_valid is set 3329 3330 3331 3332 The Least Significant 4 bytes of the Received Frames MAC 3333 Address AD4 3334 3335 <legal all> 3336 */ 3337 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 3338 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB 0 3339 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK 0xffffffff 3340 3341 /* Description RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32 3342 3343 Field only valid when mac_addr_ad4_valid is set 3344 3345 3346 3347 The 2 most significant bytes of the Received Frames MAC 3348 Address AD4 3349 3350 <legal all> 3351 */ 3352 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 3353 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB 0 3354 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK 0x0000ffff 3355 3356 /* Description RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD 3357 3358 Field only valid when mpdu_qos_control_valid is set 3359 3360 3361 3362 The sequence control field of the MPDU 3363 3364 <legal all> 3365 */ 3366 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 3367 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_LSB 16 3368 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 3369 3370 /* Description RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD 3371 3372 Field only valid when mpdu_qos_control_valid is set 3373 3374 3375 3376 The HT control field of the MPDU 3377 3378 <legal all> 3379 */ 3380 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 3381 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_LSB 0 3382 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff 3383 3384 3385 #endif // _RX_MPDU_INFO_H_ 3386