1 /* 2 * Copyright (c) 2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #if defined(QCA6490_HEADERS_DEF) 20 21 #undef UMAC 22 #define WLAN_HEADERS 1 23 24 #include "lithium_top_reg.h" 25 #include "wcss_version.h" 26 27 #define MISSING 0 28 29 #define SOC_RESET_CONTROL_OFFSET MISSING 30 #define GPIO_PIN0_OFFSET MISSING 31 #define GPIO_PIN1_OFFSET MISSING 32 #define GPIO_PIN0_CONFIG_MASK MISSING 33 #define GPIO_PIN1_CONFIG_MASK MISSING 34 #define LOCAL_SCRATCH_OFFSET 0x18 35 #define GPIO_PIN10_OFFSET MISSING 36 #define GPIO_PIN11_OFFSET MISSING 37 #define GPIO_PIN12_OFFSET MISSING 38 #define GPIO_PIN13_OFFSET MISSING 39 #define MBOX_BASE_ADDRESS MISSING 40 #define INT_STATUS_ENABLE_ERROR_LSB MISSING 41 #define INT_STATUS_ENABLE_ERROR_MASK MISSING 42 #define INT_STATUS_ENABLE_CPU_LSB MISSING 43 #define INT_STATUS_ENABLE_CPU_MASK MISSING 44 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING 45 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING 46 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 47 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 48 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 49 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 50 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 51 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 52 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 53 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 54 #define INT_STATUS_ENABLE_ADDRESS MISSING 55 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 56 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 57 #define HOST_INT_STATUS_ADDRESS MISSING 58 #define CPU_INT_STATUS_ADDRESS MISSING 59 #define ERROR_INT_STATUS_ADDRESS MISSING 60 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING 61 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING 62 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 63 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 64 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 65 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 66 #define COUNT_DEC_ADDRESS MISSING 67 #define HOST_INT_STATUS_CPU_MASK MISSING 68 #define HOST_INT_STATUS_CPU_LSB MISSING 69 #define HOST_INT_STATUS_ERROR_MASK MISSING 70 #define HOST_INT_STATUS_ERROR_LSB MISSING 71 #define HOST_INT_STATUS_COUNTER_MASK MISSING 72 #define HOST_INT_STATUS_COUNTER_LSB MISSING 73 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING 74 #define WINDOW_DATA_ADDRESS MISSING 75 #define WINDOW_READ_ADDR_ADDRESS MISSING 76 #define WINDOW_WRITE_ADDR_ADDRESS MISSING 77 /* GPIO Register */ 78 #define GPIO_ENABLE_W1TS_LOW_ADDRESS MISSING 79 #define GPIO_PIN0_CONFIG_LSB MISSING 80 #define GPIO_PIN0_PAD_PULL_LSB MISSING 81 #define GPIO_PIN0_PAD_PULL_MASK MISSING 82 /* SI reg */ 83 #define SI_CONFIG_ERR_INT_MASK MISSING 84 #define SI_CONFIG_ERR_INT_LSB MISSING 85 86 #define RTC_SOC_BASE_ADDRESS MISSING 87 #define RTC_WMAC_BASE_ADDRESS MISSING 88 #define SOC_CORE_BASE_ADDRESS MISSING 89 #define WLAN_MAC_BASE_ADDRESS MISSING 90 #define GPIO_BASE_ADDRESS MISSING 91 #define ANALOG_INTF_BASE_ADDRESS MISSING 92 #define CE0_BASE_ADDRESS MISSING 93 #define CE1_BASE_ADDRESS MISSING 94 #define CE_COUNT 12 95 #define CE_WRAPPER_BASE_ADDRESS MISSING 96 #define SI_BASE_ADDRESS MISSING 97 #define DRAM_BASE_ADDRESS MISSING 98 99 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB MISSING 100 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK MISSING 101 #define CLOCK_CONTROL_OFFSET MISSING 102 #define CLOCK_CONTROL_SI0_CLK_MASK MISSING 103 #define RESET_CONTROL_SI0_RST_MASK MISSING 104 #define WLAN_RESET_CONTROL_OFFSET MISSING 105 #define WLAN_RESET_CONTROL_COLD_RST_MASK MISSING 106 #define WLAN_RESET_CONTROL_WARM_RST_MASK MISSING 107 #define CPU_CLOCK_OFFSET MISSING 108 109 #define CPU_CLOCK_STANDARD_LSB MISSING 110 #define CPU_CLOCK_STANDARD_MASK MISSING 111 #define LPO_CAL_ENABLE_LSB MISSING 112 #define LPO_CAL_ENABLE_MASK MISSING 113 #define WLAN_SYSTEM_SLEEP_OFFSET MISSING 114 115 #define SOC_CHIP_ID_ADDRESS MISSING 116 #define SOC_CHIP_ID_REVISION_MASK MISSING 117 #define SOC_CHIP_ID_REVISION_LSB MISSING 118 #define SOC_CHIP_ID_REVISION_MSB MISSING 119 120 #define FW_IND_EVENT_PENDING MISSING 121 #define FW_IND_INITIALIZED MISSING 122 123 #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK MISSING 124 #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK MISSING 125 #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK MISSING 126 #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK MISSING 127 #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB MISSING 128 #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB MISSING 129 #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB MISSING 130 #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB MISSING 131 132 #define SR_WR_INDEX_ADDRESS MISSING 133 #define DST_WATERMARK_ADDRESS MISSING 134 135 #define DST_WR_INDEX_ADDRESS MISSING 136 #define SRC_WATERMARK_ADDRESS MISSING 137 #define SRC_WATERMARK_LOW_MASK MISSING 138 #define SRC_WATERMARK_HIGH_MASK MISSING 139 #define DST_WATERMARK_LOW_MASK MISSING 140 #define DST_WATERMARK_HIGH_MASK MISSING 141 #define CURRENT_SRRI_ADDRESS MISSING 142 #define CURRENT_DRRI_ADDRESS MISSING 143 #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK MISSING 144 #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK MISSING 145 #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK MISSING 146 #define HOST_IS_DST_RING_LOW_WATERMARK_MASK MISSING 147 #define HOST_IS_ADDRESS MISSING 148 #define MISC_IS_ADDRESS MISSING 149 #define HOST_IS_COPY_COMPLETE_MASK MISSING 150 #define CE_WRAPPER_BASE_ADDRESS MISSING 151 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS MISSING 152 #define CE_DDR_ADDRESS_FOR_RRI_LOW MISSING 153 #define CE_DDR_ADDRESS_FOR_RRI_HIGH MISSING 154 155 #if (defined(WCSS_VERSION) && (WCSS_VERSION >= 72)) 156 #define HOST_IE_ADDRESS UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0 157 #define HOST_IE_ADDRESS_2 UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1 158 #else /* WCSS_VERSION < 72 */ 159 #define HOST_IE_ADDRESS UMAC_CE_COMMON_CE_HOST_IE_0 160 #define HOST_IE_ADDRESS_2 UMAC_CE_COMMON_CE_HOST_IE_1 161 #endif /* WCSS_VERSION */ 162 163 #define HOST_IE_COPY_COMPLETE_MASK MISSING 164 #define SR_BA_ADDRESS MISSING 165 #define SR_BA_ADDRESS_HIGH MISSING 166 #define SR_SIZE_ADDRESS MISSING 167 #define CE_CTRL1_ADDRESS MISSING 168 #define CE_CTRL1_DMAX_LENGTH_MASK MISSING 169 #define DR_BA_ADDRESS MISSING 170 #define DR_BA_ADDRESS_HIGH MISSING 171 #define DR_SIZE_ADDRESS MISSING 172 #define CE_CMD_REGISTER MISSING 173 #define CE_MSI_ADDRESS MISSING 174 #define CE_MSI_ADDRESS_HIGH MISSING 175 #define CE_MSI_DATA MISSING 176 #define CE_MSI_ENABLE_BIT MISSING 177 #define MISC_IE_ADDRESS MISSING 178 #define MISC_IS_AXI_ERR_MASK MISSING 179 #define MISC_IS_DST_ADDR_ERR_MASK MISSING 180 #define MISC_IS_SRC_LEN_ERR_MASK MISSING 181 #define MISC_IS_DST_MAX_LEN_VIO_MASK MISSING 182 #define MISC_IS_DST_RING_OVERFLOW_MASK MISSING 183 #define MISC_IS_SRC_RING_OVERFLOW_MASK MISSING 184 #define SRC_WATERMARK_LOW_LSB MISSING 185 #define SRC_WATERMARK_HIGH_LSB MISSING 186 #define DST_WATERMARK_LOW_LSB MISSING 187 #define DST_WATERMARK_HIGH_LSB MISSING 188 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK MISSING 189 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB MISSING 190 #define CE_CTRL1_DMAX_LENGTH_LSB MISSING 191 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK MISSING 192 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK MISSING 193 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB MISSING 194 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB MISSING 195 #define CE_CTRL1_IDX_UPD_EN_MASK MISSING 196 #define CE_WRAPPER_DEBUG_OFFSET MISSING 197 #define CE_WRAPPER_DEBUG_SEL_MSB MISSING 198 #define CE_WRAPPER_DEBUG_SEL_LSB MISSING 199 #define CE_WRAPPER_DEBUG_SEL_MASK MISSING 200 #define CE_DEBUG_OFFSET MISSING 201 #define CE_DEBUG_SEL_MSB MISSING 202 #define CE_DEBUG_SEL_LSB MISSING 203 #define CE_DEBUG_SEL_MASK MISSING 204 #define CE0_BASE_ADDRESS MISSING 205 #define CE1_BASE_ADDRESS MISSING 206 #define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES MISSING 207 #define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS MISSING 208 209 #define QCA6490_BOARD_DATA_SZ MISSING 210 #define QCA6490_BOARD_EXT_DATA_SZ MISSING 211 212 #define MY_TARGET_DEF QCA6490_TARGETdef 213 #define MY_HOST_DEF QCA6490_HOSTdef 214 #define MY_CEREG_DEF QCA6490_CE_TARGETdef 215 #define MY_TARGET_BOARD_DATA_SZ QCA6490_BOARD_DATA_SZ 216 #define MY_TARGET_BOARD_EXT_DATA_SZ QCA6490_BOARD_EXT_DATA_SZ 217 #include "targetdef.h" 218 #include "hostdef.h" 219 #else 220 #include "common_drv.h" 221 #include "targetdef.h" 222 #include "hostdef.h" 223 struct targetdef_s *QCA6490_TARGETdef; 224 struct hostdef_s *QCA6490_HOSTdef; 225 #endif /*QCA6490_HEADERS_DEF */ 226