1 /*
2 * Copyright (c) 2015-2021 The Linux Foundation. All rights reserved.
3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for
6 * any purpose with or without fee is hereby granted, provided that the
7 * above copyright notice and this permission notice appear in all
8 * copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17 * PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #ifndef __HIF_IO32_H__
21 #define __HIF_IO32_H__
22
23 #include <linux/io.h>
24 #include "hif.h"
25 #include "hif_main.h"
26 #include "pld_common.h"
27 /* Device memory is 32MB but bar size is only 1MB.
28 * Register remapping logic is used to access 32MB device memory.
29 * 0-512KB : Fixed address, 512KB-1MB : remapped address.
30 * Use PCIE_REMAP_1M_BAR_CTRL register to set window
31 * for pcie based wifi chipsets.
32 */
33 #define MAX_UNWINDOWED_ADDRESS 0x80000
34 #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \
35 defined(QCA_WIFI_QCN9000) || defined(QCA_WIFI_QCA6750) || \
36 defined(QCA_WIFI_QCN6432) || \
37 defined(QCA_WIFI_QCN9224) || defined(QCA_WIFI_KIWI)
38 #define WINDOW_ENABLE_BIT 0x40000000
39 #else
40 #define WINDOW_ENABLE_BIT 0x80000000
41 #endif
42 #ifdef QCA_WIFI_PEACH
43 #define WINDOW_REG_ADDRESS 0x3278
44 #else
45 #define WINDOW_REG_ADDRESS 0x310C
46 #endif
47 #define WINDOW_SHIFT 19
48 #define WINDOW_VALUE_MASK 0x3F
49 #define WINDOW_START MAX_UNWINDOWED_ADDRESS
50 #define WINDOW_RANGE_MASK 0x7FFFF
51
52 #if defined(HIF_REG_WINDOW_SUPPORT) && defined(HIF_PCI)
53
54 static inline
55 void hif_write32_mb_reg_window(void *sc,
56 void __iomem *addr, uint32_t value);
57 static inline
58 uint32_t hif_read32_mb_reg_window(void *sc,
59 void __iomem *addr);
60 #define hif_read32_mb(scn, addr) \
61 hif_read32_mb_reg_window((void *)scn, \
62 (void __iomem *)addr)
63 #define hif_write32_mb(scn, addr, value) \
64 hif_write32_mb_reg_window((void *)scn, \
65 (void __iomem *)addr, value)
66
67 #else
68 #define hif_read32_mb(scn, addr) ioread32((void __iomem *)addr)
69 #define hif_write32_mb(scn, addr, value) \
70 iowrite32((u32)(value), (void __iomem *)(addr))
71 #endif
72
73 #define Q_TARGET_ACCESS_BEGIN(scn) \
74 hif_target_sleep_state_adjust(scn, false, true)
75 #define Q_TARGET_ACCESS_END(scn) \
76 hif_target_sleep_state_adjust(scn, true, false)
77 #define TARGET_REGISTER_ACCESS_ALLOWED(scn)\
78 hif_is_target_register_access_allowed(scn)
79
80 /*
81 * A_TARGET_ACCESS_LIKELY will not wait for the target to wake up before
82 * continuing execution. Because A_TARGET_ACCESS_LIKELY does not guarantee
83 * that the target is awake before continuing, Q_TARGET_ACCESS macros must
84 * protect the actual target access. Since Q_TARGET_ACCESS protect the actual
85 * target access, A_TARGET_ACCESS_LIKELY hints are optional.
86 *
87 * To ignore "LIKELY" hints, set CONFIG_TARGET_ACCESS_LIKELY to 0
88 * (slightly worse performance, less power)
89 *
90 * To use "LIKELY" hints, set CONFIG_TARGET_ACCESS_LIKELY to 1
91 * (slightly better performance, more power)
92 *
93 * note: if a bus doesn't use hif_target_sleep_state_adjust, this will have
94 * no impact.
95 */
96 #define CONFIG_TARGET_ACCESS_LIKELY 0
97 #if CONFIG_TARGET_ACCESS_LIKELY
98 #define A_TARGET_ACCESS_LIKELY(scn) \
99 hif_target_sleep_state_adjust(scn, false, false)
100 #define A_TARGET_ACCESS_UNLIKELY(scn) \
101 hif_target_sleep_state_adjust(scn, true, false)
102 #else /* CONFIG_ATH_PCIE_ACCESS_LIKELY */
103 #define A_TARGET_ACCESS_LIKELY(scn) \
104 do { \
105 unsigned long unused = (unsigned long)(scn); \
106 unused = unused; \
107 } while (0)
108
109 #define A_TARGET_ACCESS_UNLIKELY(scn) \
110 do { \
111 unsigned long unused = (unsigned long)(scn); \
112 unused = unused; \
113 } while (0)
114 #endif /* CONFIG_ATH_PCIE_ACCESS_LIKELY */
115
116
117 #ifdef HIF_PCI
118 #include "hif_io32_pci.h"
119 #endif
120 #ifdef HIF_SNOC
121 #include "hif_io32_snoc.h"
122 #endif
123 #ifdef HIF_IPCI
124 #include "hif_io32_ipci.h"
125 #endif
126
127 #ifdef HIF_IPCI
128 /**
129 * hif_target_access_allowed(): Check if target access is allowed
130 *
131 * @scn: HIF handler
132 *
133 * Return: True if access is allowed else False
134 */
135 static inline
hif_target_access_allowed(struct hif_softc * scn)136 bool hif_target_access_allowed(struct hif_softc *scn)
137 {
138 return !(scn->recovery);
139 }
140
141 #define TARGET_ACCESS_ALLOWED(scn) \
142 hif_target_access_allowed(scn)
143 #else
144 #define TARGET_ACCESS_ALLOWED(scn) (1)
145 #endif
146
147 #if defined(HIF_REG_WINDOW_SUPPORT) && defined(HIF_PCI)
148
149 #include "qdf_lock.h"
150 #include "qdf_util.h"
151
152 /**
153 * hif_reg_write_result_check() - check register writing result
154 * @sc: hif pcie context
155 * @offset: register offset to read
156 * @exp_val: the expected value of register
157 *
158 * Return: none
159 */
hif_reg_write_result_check(struct hif_pci_softc * sc,uint32_t offset,uint32_t exp_val)160 static inline void hif_reg_write_result_check(struct hif_pci_softc *sc,
161 uint32_t offset,
162 uint32_t exp_val)
163 {
164 uint32_t value;
165
166 value = qdf_ioread32(sc->mem + offset);
167 if (exp_val != value) {
168 hif_err("Reg write failed. write val 0x%x read val 0x%x offset 0x%x",
169 exp_val,
170 value,
171 offset);
172 }
173 }
174
175 #ifdef PCIE_REG_WINDOW_LOCAL_NO_CACHE
176 /**
177 * hif_select_window_confirm(): Update the register window
178 * @sc: HIF pci handle
179 * @offset: reg offset to read from or write to
180 *
181 * Calculate the window using the offset provided and update
182 * the window reg value accordingly for windowed read/write reg
183 * access.
184 * Read back to make sure the window is written to the register.
185 * Return: None
186 */
187 static inline
hif_select_window_confirm(struct hif_pci_softc * sc,uint32_t offset)188 void hif_select_window_confirm(struct hif_pci_softc *sc, uint32_t offset)
189 {
190 uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
191
192 qdf_iowrite32(sc->mem + WINDOW_REG_ADDRESS,
193 WINDOW_ENABLE_BIT | window);
194 sc->register_window = window;
195 hif_reg_write_result_check(sc, WINDOW_REG_ADDRESS,
196 WINDOW_ENABLE_BIT | window);
197 }
198 #else /* PCIE_REG_WINDOW_LOCAL_NO_CACHE */
199
200 static inline
hif_select_window_confirm(struct hif_pci_softc * sc,uint32_t offset)201 void hif_select_window_confirm(struct hif_pci_softc *sc, uint32_t offset)
202 {
203 uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
204
205 if (window != sc->register_window) {
206 qdf_iowrite32(sc->mem + WINDOW_REG_ADDRESS,
207 WINDOW_ENABLE_BIT | window);
208 sc->register_window = window;
209 hif_reg_write_result_check(sc, WINDOW_REG_ADDRESS,
210 WINDOW_ENABLE_BIT | window);
211 }
212 }
213 #endif /* PCIE_REG_WINDOW_LOCAL_NO_CACHE */
214
215 #ifdef WINDOW_REG_PLD_LOCK_ENABLE
216 /**
217 * hif_lock_reg_access() - Lock window register access spinlock
218 * @sc: HIF handle
219 * @flags: variable pointer to save CPU states
220 *
221 * Lock register window spinlock
222 *
223 * Return: void
224 */
hif_lock_reg_access(struct hif_pci_softc * sc,unsigned long * flags)225 static inline void hif_lock_reg_access(struct hif_pci_softc *sc,
226 unsigned long *flags)
227 {
228 pld_lock_reg_window(sc->dev, flags);
229 }
230
231 /**
232 * hif_unlock_reg_access() - Unlock window register access spinlock
233 * @sc: HIF handle
234 * @flags: variable pointer to save CPU states
235 *
236 * Unlock register window spinlock
237 *
238 * Return: void
239 */
hif_unlock_reg_access(struct hif_pci_softc * sc,unsigned long * flags)240 static inline void hif_unlock_reg_access(struct hif_pci_softc *sc,
241 unsigned long *flags)
242 {
243 pld_unlock_reg_window(sc->dev, flags);
244 }
245 #else
hif_lock_reg_access(struct hif_pci_softc * sc,unsigned long * flags)246 static inline void hif_lock_reg_access(struct hif_pci_softc *sc,
247 unsigned long *flags)
248 {
249 qdf_spin_lock_irqsave(&sc->register_access_lock);
250 }
251
hif_unlock_reg_access(struct hif_pci_softc * sc,unsigned long * flags)252 static inline void hif_unlock_reg_access(struct hif_pci_softc *sc,
253 unsigned long *flags)
254 {
255 qdf_spin_unlock_irqrestore(&sc->register_access_lock);
256 }
257 #endif
258
259 /*
260 * note1: WINDOW_RANGE_MASK = (1 << WINDOW_SHIFT) -1
261 * note2: 1 << WINDOW_SHIFT = MAX_UNWINDOWED_ADDRESS
262 * note3: WINDOW_VALUE_MASK = big enough that trying to write past that window
263 * would be a bug
264 */
hif_write32_mb_reg_window(void * scn,void __iomem * addr,uint32_t value)265 static inline void hif_write32_mb_reg_window(void *scn,
266 void __iomem *addr, uint32_t value)
267 {
268 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn);
269 uint32_t offset = addr - sc->mem;
270 unsigned long flags;
271
272 if (!sc->use_register_windowing ||
273 offset < MAX_UNWINDOWED_ADDRESS) {
274 qdf_iowrite32(addr, value);
275 } else {
276 hif_lock_reg_access(sc, &flags);
277 hif_select_window_confirm(sc, offset);
278 qdf_iowrite32(sc->mem + WINDOW_START +
279 (offset & WINDOW_RANGE_MASK), value);
280 hif_unlock_reg_access(sc, &flags);
281 }
282 }
283
hif_read32_mb_reg_window(void * scn,void __iomem * addr)284 static inline uint32_t hif_read32_mb_reg_window(void *scn, void __iomem *addr)
285 {
286 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn);
287 uint32_t ret;
288 uint32_t offset = addr - sc->mem;
289 unsigned long flags;
290
291 if (!sc->use_register_windowing ||
292 offset < MAX_UNWINDOWED_ADDRESS) {
293 return qdf_ioread32(addr);
294 }
295 hif_lock_reg_access(sc, &flags);
296 hif_select_window_confirm(sc, offset);
297 ret = qdf_ioread32(sc->mem + WINDOW_START +
298 (offset & WINDOW_RANGE_MASK));
299 hif_unlock_reg_access(sc, &flags);
300
301 return ret;
302 }
303 #endif
304
305 #if defined(HIF_HAL_REG_ACCESS_SUPPORT)
306 #define A_TARGET_READ(scn, offset) \
307 hif_reg_window_read(scn, offset)
308 #define A_TARGET_WRITE(scn, offset, value) \
309 hif_reg_window_write(scn, offset, value)
310 #elif defined(CONFIG_IO_MEM_ACCESS_DEBUG)
311 uint32_t hif_target_read_checked(struct hif_softc *scn,
312 uint32_t offset);
313 void hif_target_write_checked(struct hif_softc *scn, uint32_t offset,
314 uint32_t value);
315
316 #define A_TARGET_READ(scn, offset) \
317 hif_target_read_checked(scn, (offset))
318 #define A_TARGET_WRITE(scn, offset, value) \
319 hif_target_write_checked(scn, (offset), (value))
320 #else /* CONFIG_ATH_PCIE_ACCESS_DEBUG */
321 #define A_TARGET_READ(scn, offset) \
322 hif_read32_mb(scn, scn->mem + (offset))
323 #define A_TARGET_WRITE(scn, offset, value) \
324 hif_write32_mb(scn, (scn->mem) + (offset), value)
325 #endif
326
327 #ifdef FEATURE_HIF_DELAYED_REG_WRITE
328 #define A_TARGET_DELAYED_REG_WRITE(scn, ctrl_addr, val) \
329 hif_delayed_reg_write(scn, ctrl_addr, val)
330 #endif
331
332 void hif_irq_enable(struct hif_softc *scn, int irq_id);
333 void hif_irq_disable(struct hif_softc *scn, int irq_id);
334
335 #endif /* __HIF_IO32_H__ */
336