1 /*
2 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for
6 * any purpose with or without fee is hereby granted, provided that the
7 * above copyright notice and this permission notice appear in all
8 * copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17 * PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #ifndef _HAL_6450_RX_H_
21 #define _HAL_6450_RX_H_
22 #include "qdf_util.h"
23 #include "qdf_types.h"
24 #include "qdf_lock.h"
25 #include "qdf_mem.h"
26 #include "qdf_nbuf.h"
27 #include "tcl_data_cmd.h"
28 #include "phyrx_rssi_legacy.h"
29 #include "rx_msdu_start.h"
30 #include "tlv_tag_def.h"
31 #include "hal_internal.h"
32 #include "cdp_txrx_mon_struct.h"
33 #include "qdf_trace.h"
34 #include "hal_rx.h"
35 #include "hal_tx.h"
36 #include "dp_types.h"
37 #include "hal_api_mon.h"
38 #include "phyrx_other_receive_info_ru_details.h"
39
40 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
41 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
42 RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \
43 RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \
44 RX_MSDU_START_5_MIMO_SS_BITMAP_LSB))
45
46 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \
47 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
48 RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET)), \
49 RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK, \
50 RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB))
51
52 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
53 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
54 RX_MSDU_END_10_DA_IS_MCBC_OFFSET)), \
55 RX_MSDU_END_10_DA_IS_MCBC_MASK, \
56 RX_MSDU_END_10_DA_IS_MCBC_LSB))
57
58 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \
59 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
60 RX_MSDU_END_10_SA_IS_VALID_OFFSET)), \
61 RX_MSDU_END_10_SA_IS_VALID_MASK, \
62 RX_MSDU_END_10_SA_IS_VALID_LSB))
63
64 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \
65 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
66 RX_MSDU_END_11_SA_IDX_OFFSET)), \
67 RX_MSDU_END_11_SA_IDX_MASK, \
68 RX_MSDU_END_11_SA_IDX_LSB))
69
70 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \
71 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
72 RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET)), \
73 RX_MSDU_END_10_L3_HEADER_PADDING_MASK, \
74 RX_MSDU_END_10_L3_HEADER_PADDING_LSB))
75
76 #define HAL_RX_MSDU_END_L3_TYPE_GET(_rx_msdu_end) \
77 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
78 RX_MSDU_END_5_L3_TYPE_OFFSET)), \
79 RX_MSDU_END_5_L3_TYPE_MASK, \
80 RX_MSDU_END_5_L3_TYPE_LSB))
81
82 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \
83 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
84 RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \
85 RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK, \
86 RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB))
87
88 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \
89 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
90 RX_MPDU_INFO_3_PN_31_0_OFFSET)), \
91 RX_MPDU_INFO_3_PN_31_0_MASK, \
92 RX_MPDU_INFO_3_PN_31_0_LSB))
93
94 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \
95 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
96 RX_MPDU_INFO_4_PN_63_32_OFFSET)), \
97 RX_MPDU_INFO_4_PN_63_32_MASK, \
98 RX_MPDU_INFO_4_PN_63_32_LSB))
99
100 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \
101 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
102 RX_MPDU_INFO_5_PN_95_64_OFFSET)), \
103 RX_MPDU_INFO_5_PN_95_64_MASK, \
104 RX_MPDU_INFO_5_PN_95_64_LSB))
105
106 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \
107 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
108 RX_MPDU_INFO_6_PN_127_96_OFFSET)), \
109 RX_MPDU_INFO_6_PN_127_96_MASK, \
110 RX_MPDU_INFO_6_PN_127_96_LSB))
111
112 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \
113 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
114 RX_MSDU_END_10_FIRST_MSDU_OFFSET)), \
115 RX_MSDU_END_10_FIRST_MSDU_MASK, \
116 RX_MSDU_END_10_FIRST_MSDU_LSB))
117
118 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \
119 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
120 RX_MSDU_END_10_DA_IS_VALID_OFFSET)), \
121 RX_MSDU_END_10_DA_IS_VALID_MASK, \
122 RX_MSDU_END_10_DA_IS_VALID_LSB))
123
124 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \
125 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
126 RX_MSDU_END_10_LAST_MSDU_OFFSET)), \
127 RX_MSDU_END_10_LAST_MSDU_MASK, \
128 RX_MSDU_END_10_LAST_MSDU_LSB))
129
130 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \
131 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
132 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET)), \
133 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK, \
134 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB))
135
136 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \
137 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
138 RX_MPDU_INFO_10_SW_PEER_ID_OFFSET)), \
139 RX_MPDU_INFO_10_SW_PEER_ID_MASK, \
140 RX_MPDU_INFO_10_SW_PEER_ID_LSB))
141
142 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \
143 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
144 RX_MPDU_INFO_11_TO_DS_OFFSET)), \
145 RX_MPDU_INFO_11_TO_DS_MASK, \
146 RX_MPDU_INFO_11_TO_DS_LSB))
147
148 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \
149 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
150 RX_MPDU_INFO_11_FR_DS_OFFSET)), \
151 RX_MPDU_INFO_11_FR_DS_MASK, \
152 RX_MPDU_INFO_11_FR_DS_LSB))
153
154 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \
155 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
156 RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET)), \
157 RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK, \
158 RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB))
159
160 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \
161 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
162 RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET)), \
163 RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK, \
164 RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB))
165
166 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \
167 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
168 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \
169 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \
170 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB))
171
172 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \
173 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
174 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \
175 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \
176 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB))
177
178 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \
179 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
180 RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET)), \
181 RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK, \
182 RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB))
183
184 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \
185 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
186 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \
187 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \
188 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB))
189
190 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \
191 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
192 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \
193 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \
194 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB))
195
196 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \
197 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
198 RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET)), \
199 RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK, \
200 RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB))
201
202 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \
203 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
204 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \
205 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \
206 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB))
207
208 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \
209 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
210 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \
211 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \
212 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB))
213
214 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \
215 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
216 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET)), \
217 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK, \
218 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB))
219
220 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \
221 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
222 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \
223 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \
224 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB))
225
226 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \
227 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
228 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \
229 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \
230 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB))
231
232 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \
233 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
234 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \
235 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK, \
236 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB))
237
238 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \
239 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
240 RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET)), \
241 RX_MSDU_END_14_SA_SW_PEER_ID_MASK, \
242 RX_MSDU_END_14_SA_SW_PEER_ID_LSB))
243
244 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \
245 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MPDU_FRAME_CONTROL_VALID)
246
247 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \
248 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, TO_DS)
249
250 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \
251 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD1_VALID)
252
253 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \
254 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD2_VALID)
255
256 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \
257 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, RXPCU_MPDU_FILTER_IN_CATEGORY)
258
259 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \
260 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, PHY_PPDU_ID)
261
262 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \
263 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, SW_FRAME_GROUP_ID)
264
265 #define HAL_RX_GET_SW_PEER_ID(rx_mpdu_start) \
266 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_10, SW_PEER_ID)
267
268 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \
269 ((struct rx_msdu_desc_info *) \
270 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \
271 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET))
272
273 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \
274 ((struct rx_msdu_details *) \
275 _OFFSET_TO_BYTE_PTR((link_desc),\
276 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET))
277
278 #define HAL_RX_MSDU_END_REO_DEST_IND_GET(_rx_msdu_end) \
279 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
280 RX_MSDU_END_12_REO_DESTINATION_INDICATION_OFFSET)), \
281 RX_MSDU_END_12_REO_DESTINATION_INDICATION_MASK, \
282 RX_MSDU_END_12_REO_DESTINATION_INDICATION_LSB))
283
284 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \
285 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
286 RX_MSDU_END_12_FLOW_IDX_OFFSET)), \
287 RX_MSDU_END_12_FLOW_IDX_MASK, \
288 RX_MSDU_END_12_FLOW_IDX_LSB))
289
290 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \
291 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
292 RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET)), \
293 RX_MSDU_END_10_FLOW_IDX_INVALID_MASK, \
294 RX_MSDU_END_10_FLOW_IDX_INVALID_LSB))
295
296 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \
297 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
298 RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET)), \
299 RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK, \
300 RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB))
301
302 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \
303 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
304 RX_MSDU_END_13_FSE_METADATA_OFFSET)), \
305 RX_MSDU_END_13_FSE_METADATA_MASK, \
306 RX_MSDU_END_13_FSE_METADATA_LSB))
307
308 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \
309 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
310 RX_MSDU_END_14_CCE_METADATA_OFFSET)), \
311 RX_MSDU_END_14_CCE_METADATA_MASK, \
312 RX_MSDU_END_14_CCE_METADATA_LSB))
313
314 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \
315 (_HAL_MS( \
316 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
317 msdu_end_tlv.rx_msdu_end), \
318 RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET)), \
319 RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK, \
320 RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB))
321
322 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \
323 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
324 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET)), \
325 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK, \
326 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB))
327
328 #define HAL_RX_TLV_GET_FLOW_AGGR_CONT(buf) \
329 (_HAL_MS( \
330 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
331 msdu_end_tlv.rx_msdu_end), \
332 RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_OFFSET)), \
333 RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_MASK, \
334 RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_LSB))
335
336 #define HAL_RX_TLV_GET_FLOW_AGGR_COUNT(buf) \
337 (_HAL_MS( \
338 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
339 msdu_end_tlv.rx_msdu_end), \
340 RX_MSDU_END_15_AGGREGATION_COUNT_OFFSET)), \
341 RX_MSDU_END_15_AGGREGATION_COUNT_MASK, \
342 RX_MSDU_END_15_AGGREGATION_COUNT_LSB))
343
344 #define HAL_RX_TLV_GET_FISA_TIMEOUT(buf) \
345 (_HAL_MS( \
346 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
347 msdu_end_tlv.rx_msdu_end), \
348 RX_MSDU_END_15_FISA_TIMEOUT_OFFSET)), \
349 RX_MSDU_END_15_FISA_TIMEOUT_MASK, \
350 RX_MSDU_END_15_FISA_TIMEOUT_LSB))
351
352 #define HAL_RX_TLV_GET_FISA_CUMULATIVE_L4_CHECKSUM(buf) \
353 (_HAL_MS( \
354 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
355 msdu_end_tlv.rx_msdu_end), \
356 RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_OFFSET)), \
357 RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_MASK, \
358 RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_LSB))
359
360 #define HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(buf) \
361 (_HAL_MS( \
362 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
363 msdu_end_tlv.rx_msdu_end), \
364 RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_OFFSET)), \
365 RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_MASK, \
366 RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_LSB))
367
368 #if defined(QCA_WIFI_WCN6450) && defined(WLAN_CFR_ENABLE) && \
369 defined(WLAN_ENH_CFR_ENABLE)
370 static inline
hal_rx_get_bb_info_6450(void * rx_tlv,void * ppdu_info_hdl)371 void hal_rx_get_bb_info_6450(void *rx_tlv,
372 void *ppdu_info_hdl)
373 {
374 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
375
376 ppdu_info->cfr_info.bb_captured_channel =
377 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL);
378
379 ppdu_info->cfr_info.bb_captured_timeout =
380 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT);
381
382 ppdu_info->cfr_info.bb_captured_reason =
383 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON);
384 }
385
386 static inline
hal_rx_get_rtt_info_6450(void * rx_tlv,void * ppdu_info_hdl)387 void hal_rx_get_rtt_info_6450(void *rx_tlv,
388 void *ppdu_info_hdl)
389 {
390 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
391
392 ppdu_info->cfr_info.rx_location_info_valid =
393 HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS,
394 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID);
395
396 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 =
397 HAL_RX_GET(rx_tlv,
398 PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
399 RTT_CHE_BUFFER_POINTER_LOW32);
400
401 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 =
402 HAL_RX_GET(rx_tlv,
403 PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
404 RTT_CHE_BUFFER_POINTER_HIGH8);
405
406 ppdu_info->cfr_info.chan_capture_status =
407 HAL_RX_GET(rx_tlv,
408 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
409 RESERVED_8);
410 ppdu_info->cfr_info.rx_start_ts =
411 HAL_RX_GET(rx_tlv,
412 PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
413 RX_START_TS);
414
415 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t)
416 HAL_RX_GET(rx_tlv,
417 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
418 RTT_CFO_MEASUREMENT);
419
420 ppdu_info->cfr_info.agc_gain_info0 =
421 HAL_RX_GET(rx_tlv,
422 PHYRX_PKT_END_1_RX_PKT_END_DETAILS,
423 PHY_TIMESTAMP_1_LOWER_32);
424
425 ppdu_info->cfr_info.agc_gain_info1 =
426 HAL_RX_GET(rx_tlv,
427 PHYRX_PKT_END_2_RX_PKT_END_DETAILS,
428 PHY_TIMESTAMP_1_UPPER_32);
429
430 ppdu_info->cfr_info.agc_gain_info2 =
431 HAL_RX_GET(rx_tlv,
432 PHYRX_PKT_END_3_RX_PKT_END_DETAILS,
433 PHY_TIMESTAMP_2_LOWER_32);
434
435 ppdu_info->cfr_info.agc_gain_info3 =
436 HAL_RX_GET(rx_tlv,
437 PHYRX_PKT_END_4_RX_PKT_END_DETAILS,
438 PHY_TIMESTAMP_2_UPPER_32);
439
440 ppdu_info->cfr_info.mcs_rate =
441 HAL_RX_GET(rx_tlv,
442 PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
443 RTT_MCS_RATE);
444
445 ppdu_info->cfr_info.gi_type =
446 HAL_RX_GET(rx_tlv,
447 PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
448 RTT_GI_TYPE);
449 }
450 #endif
451 #endif
452