1 /*
2  * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
3  * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for
6  * any purpose with or without fee is hereby granted, provided that the
7  * above copyright notice and this permission notice appear in all
8  * copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17  * PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #ifndef _HAL_RH_GENERIC_API_H_
21 #define _HAL_RH_GENERIC_API_H_
22 
23 #include "hal_tx.h"
24 #include "hal_rh_tx.h"
25 #include "hal_rh_rx.h"
26 #include <htt.h>
27 
28 #ifdef QCA_UNDECODED_METADATA_SUPPORT
29 static inline void
hal_rx_get_phyrx_abort(struct hal_soc * hal,void * rx_tlv,struct hal_rx_ppdu_info * ppdu_info)30 hal_rx_get_phyrx_abort(struct hal_soc *hal, void *rx_tlv,
31 		       struct hal_rx_ppdu_info *ppdu_info){
32 	switch (hal->target_type) {
33 	case TARGET_TYPE_QCN9000:
34 		ppdu_info->rx_status.phyrx_abort =
35 			HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2,
36 				   PHYRX_ABORT_REQUEST_INFO_VALID);
37 		ppdu_info->rx_status.phyrx_abort_reason =
38 			HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_11,
39 				   PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON);
40 		break;
41 	default:
42 		break;
43 	}
44 }
45 
46 static inline void
hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info * ppdu_info,uint8_t * ht_sig_info)47 hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info *ppdu_info,
48 		       uint8_t *ht_sig_info)
49 {
50 	ppdu_info->rx_status.ht_length =
51 		HAL_RX_GET(ht_sig_info, HT_SIG_INFO_0, LENGTH);
52 	ppdu_info->rx_status.smoothing =
53 		HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, SMOOTHING);
54 	ppdu_info->rx_status.not_sounding =
55 		HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, NOT_SOUNDING);
56 	ppdu_info->rx_status.aggregation =
57 		HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, AGGREGATION);
58 	ppdu_info->rx_status.ht_stbc =
59 		HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, STBC);
60 	ppdu_info->rx_status.ht_crc =
61 		HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, CRC);
62 }
63 
64 static inline void
hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info * ppdu_info,uint8_t * l_sig_a_info)65 hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info *ppdu_info,
66 			uint8_t *l_sig_a_info)
67 {
68 	ppdu_info->rx_status.l_sig_length =
69 		HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, LENGTH);
70 	ppdu_info->rx_status.l_sig_a_parity =
71 		HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, PARITY);
72 	ppdu_info->rx_status.l_sig_a_pkt_type =
73 		HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, PKT_TYPE);
74 	ppdu_info->rx_status.l_sig_a_implicit_sounding =
75 		HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0,
76 			   CAPTURED_IMPLICIT_SOUNDING);
77 }
78 
79 static inline void
hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info * ppdu_info,uint8_t * vht_sig_a_info)80 hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info *ppdu_info,
81 			  uint8_t *vht_sig_a_info)
82 {
83 	ppdu_info->rx_status.vht_no_txop_ps =
84 		HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0,
85 			   TXOP_PS_NOT_ALLOWED);
86 	ppdu_info->rx_status.vht_crc =
87 		HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, CRC);
88 }
89 
90 static inline void
hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info * ppdu_info,uint8_t * he_sig_a_su_info)91 hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info *ppdu_info,
92 				uint8_t *he_sig_a_su_info) {
93 	ppdu_info->rx_status.he_crc =
94 		HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, CRC);
95 }
96 
97 static inline void
hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info * ppdu_info,uint8_t * he_sig_a_mu_dl_info)98 hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info *ppdu_info,
99 				   uint8_t *he_sig_a_mu_dl_info) {
100 	ppdu_info->rx_status.he_crc =
101 		HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, CRC);
102 }
103 #else
104 static inline void
hal_rx_get_phyrx_abort(struct hal_soc * hal,void * rx_tlv,struct hal_rx_ppdu_info * ppdu_info)105 hal_rx_get_phyrx_abort(struct hal_soc *hal, void *rx_tlv,
106 		       struct hal_rx_ppdu_info *ppdu_info)
107 {
108 }
109 
110 static inline void
hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info * ppdu_info,uint8_t * ht_sig_info)111 hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info *ppdu_info,
112 		       uint8_t *ht_sig_info)
113 {
114 }
115 
116 static inline void
hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info * ppdu_info,uint8_t * l_sig_a_info)117 hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info *ppdu_info,
118 			uint8_t *l_sig_a_info)
119 {
120 }
121 
122 static inline void
hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info * ppdu_info,uint8_t * vht_sig_a_info)123 hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info *ppdu_info,
124 			  uint8_t *vht_sig_a_info)
125 {
126 }
127 
128 static inline void
hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info * ppdu_info,uint8_t * he_sig_a_su_info)129 hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info *ppdu_info,
130 				uint8_t *he_sig_a_su_info)
131 {
132 }
133 
134 static inline void
hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info * ppdu_info,uint8_t * he_sig_a_mu_dl_info)135 hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info *ppdu_info,
136 				   uint8_t *he_sig_a_mu_dl_info)
137 {
138 }
139 #endif /* QCA_UNDECODED_METADATA_SUPPORT */
140 
141 /**
142  * hal_tx_desc_set_buf_addr_generic_rh - Fill Buffer Address information
143  *	in Tx Descriptor
144  * @desc: Handle to Tx Descriptor
145  * @paddr: Physical Address
146  * @rbm_id: Return Buffer Manager ID
147  * @desc_id: Descriptor ID
148  * @type: 0 - Address points to a MSDU buffer
149  *		1 - Address points to MSDU extension descriptor
150  *
151  * Return: void
152  */
153 static inline void
hal_tx_desc_set_buf_addr_generic_rh(void * desc,dma_addr_t paddr,uint8_t rbm_id,uint32_t desc_id,uint8_t type)154 hal_tx_desc_set_buf_addr_generic_rh(void *desc, dma_addr_t paddr,
155 				    uint8_t rbm_id, uint32_t desc_id,
156 				    uint8_t type)
157 {
158 	/* Set buffer_addr_info.buffer_addr_31_0 */
159 	HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0,
160 		    BUFFER_ADDR_INFO_BUF_ADDR_INFO) =
161 		HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr);
162 
163 	/* Set buffer_addr_info.buffer_addr_39_32 */
164 	HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
165 			 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
166 		HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32,
167 		       (((uint64_t)paddr) >> 32));
168 
169 	/* Set buffer_addr_info.return_buffer_manager = rbm id */
170 	HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
171 			 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
172 		HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1,
173 		       RETURN_BUFFER_MANAGER, rbm_id);
174 
175 	/* Set buffer_addr_info.sw_buffer_cookie = desc_id */
176 	HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
177 		    BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
178 		HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE,
179 			  desc_id);
180 
181 	/* Set  Buffer or Ext Descriptor Type */
182 	HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2,
183 		    BUF_OR_EXT_DESC_TYPE) |=
184 		HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type);
185 }
186 
187 #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX)
188 /**
189  * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL
190  * @tlv_tag: Taf of the TLVs
191  * @rx_tlv: the pointer to the TLVs
192  * @ppdu_info: pointer to ppdu_info
193  *
194  * Return: true if the tlv is handled, false if not
195  */
196 static inline bool
hal_rx_handle_other_tlvs(uint32_t tlv_tag,void * rx_tlv,struct hal_rx_ppdu_info * ppdu_info)197 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv,
198 			 struct hal_rx_ppdu_info *ppdu_info)
199 {
200 	uint32_t value;
201 
202 	switch (tlv_tag) {
203 	case WIFIPHYRX_HE_SIG_A_MU_UL_E:
204 	{
205 		uint8_t *he_sig_a_mu_ul_info =
206 			(uint8_t *)rx_tlv +
207 			HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0,
208 					  HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS);
209 		ppdu_info->rx_status.he_flags = 1;
210 
211 		value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0,
212 				   FORMAT_INDICATION);
213 		if (value == 0) {
214 			ppdu_info->rx_status.he_data1 =
215 				QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
216 		} else {
217 			ppdu_info->rx_status.he_data1 =
218 				QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
219 		}
220 
221 		/* data1 */
222 		ppdu_info->rx_status.he_data1 |=
223 			QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
224 			QDF_MON_STATUS_HE_DL_UL_KNOWN |
225 			QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
226 
227 		/* data2 */
228 		ppdu_info->rx_status.he_data2 |=
229 			QDF_MON_STATUS_TXOP_KNOWN;
230 
231 		/*data3*/
232 		value = HAL_RX_GET(he_sig_a_mu_ul_info,
233 				   HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID);
234 		ppdu_info->rx_status.he_data3 = value;
235 		/* 1 for UL and 0 for DL */
236 		value = 1;
237 		value = value << QDF_MON_STATUS_DL_UL_SHIFT;
238 		ppdu_info->rx_status.he_data3 |= value;
239 
240 		/*data4*/
241 		value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0,
242 				   SPATIAL_REUSE);
243 		ppdu_info->rx_status.he_data4 = value;
244 
245 		/*data5*/
246 		value = HAL_RX_GET(he_sig_a_mu_ul_info,
247 				   HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW);
248 		ppdu_info->rx_status.he_data5 = value;
249 		ppdu_info->rx_status.bw = value;
250 
251 		/*data6*/
252 		value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1,
253 				   TXOP_DURATION);
254 		value = value << QDF_MON_STATUS_TXOP_SHIFT;
255 		ppdu_info->rx_status.he_data6 |= value;
256 		return true;
257 	}
258 	default:
259 		return false;
260 	}
261 }
262 #else
263 static inline bool
hal_rx_handle_other_tlvs(uint32_t tlv_tag,void * rx_tlv,struct hal_rx_ppdu_info * ppdu_info)264 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv,
265 			 struct hal_rx_ppdu_info *ppdu_info)
266 {
267 	return false;
268 }
269 #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */
270 
271 #if defined(RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET) && \
272 defined(RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET)
273 
274 static inline void
hal_rx_handle_mu_ul_info(void * rx_tlv,struct mon_rx_user_status * mon_rx_user_status)275 hal_rx_handle_mu_ul_info(void *rx_tlv,
276 			 struct mon_rx_user_status *mon_rx_user_status)
277 {
278 	mon_rx_user_status->mu_ul_user_v0_word0 =
279 		HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_11,
280 			   SW_RESPONSE_REFERENCE_PTR);
281 
282 	mon_rx_user_status->mu_ul_user_v0_word1 =
283 		HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_22,
284 			   SW_RESPONSE_REFERENCE_PTR_EXT);
285 }
286 
287 static inline void
hal_rx_populate_byte_count(void * rx_tlv,void * ppduinfo,struct mon_rx_user_status * mon_rx_user_status)288 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo,
289 			   struct mon_rx_user_status *mon_rx_user_status)
290 {
291 	uint32_t mpdu_ok_byte_count;
292 	uint32_t mpdu_err_byte_count;
293 
294 	mpdu_ok_byte_count = HAL_RX_GET(rx_tlv,
295 					RX_PPDU_END_USER_STATS_17,
296 					MPDU_OK_BYTE_COUNT);
297 	mpdu_err_byte_count = HAL_RX_GET(rx_tlv,
298 					 RX_PPDU_END_USER_STATS_19,
299 					 MPDU_ERR_BYTE_COUNT);
300 
301 	mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count;
302 	mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count;
303 }
304 #else
305 static inline void
hal_rx_handle_mu_ul_info(void * rx_tlv,struct mon_rx_user_status * mon_rx_user_status)306 hal_rx_handle_mu_ul_info(void *rx_tlv,
307 			 struct mon_rx_user_status *mon_rx_user_status)
308 {
309 }
310 
311 static inline void
hal_rx_populate_byte_count(void * rx_tlv,void * ppduinfo,struct mon_rx_user_status * mon_rx_user_status)312 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo,
313 			   struct mon_rx_user_status *mon_rx_user_status)
314 {
315 	struct hal_rx_ppdu_info *ppdu_info =
316 			(struct hal_rx_ppdu_info *)ppduinfo;
317 
318 	/* HKV1: doesn't support mpdu byte count */
319 	mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len;
320 	mon_rx_user_status->mpdu_err_byte_count = 0;
321 }
322 #endif
323 
324 static inline void
hal_rx_populate_mu_user_info(void * rx_tlv,void * ppduinfo,uint32_t user_id,struct mon_rx_user_status * mon_rx_user_status)325 hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, uint32_t user_id,
326 			     struct mon_rx_user_status *mon_rx_user_status)
327 {
328 	struct mon_rx_info *mon_rx_info;
329 	struct mon_rx_user_info *mon_rx_user_info;
330 	struct hal_rx_ppdu_info *ppdu_info =
331 			(struct hal_rx_ppdu_info *)ppduinfo;
332 
333 	mon_rx_info = &ppdu_info->rx_info;
334 	mon_rx_user_info = &ppdu_info->rx_user_info[user_id];
335 	mon_rx_user_info->qos_control_info_valid =
336 		mon_rx_info->qos_control_info_valid;
337 	mon_rx_user_info->qos_control =  mon_rx_info->qos_control;
338 
339 	mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index;
340 	mon_rx_user_status->tid = ppdu_info->rx_status.tid;
341 	mon_rx_user_status->tcp_msdu_count =
342 		ppdu_info->rx_status.tcp_msdu_count;
343 	mon_rx_user_status->udp_msdu_count =
344 		ppdu_info->rx_status.udp_msdu_count;
345 	mon_rx_user_status->other_msdu_count =
346 		ppdu_info->rx_status.other_msdu_count;
347 	mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control;
348 	mon_rx_user_status->frame_control_info_valid =
349 		ppdu_info->rx_status.frame_control_info_valid;
350 	mon_rx_user_status->data_sequence_control_info_valid =
351 		ppdu_info->rx_status.data_sequence_control_info_valid;
352 	mon_rx_user_status->first_data_seq_ctrl =
353 		ppdu_info->rx_status.first_data_seq_ctrl;
354 	mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type;
355 	mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags;
356 	mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags;
357 	mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags;
358 	mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags;
359 	mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags;
360 
361 	mon_rx_user_status->mpdu_cnt_fcs_ok =
362 		ppdu_info->com_info.mpdu_cnt_fcs_ok;
363 	mon_rx_user_status->mpdu_cnt_fcs_err =
364 		ppdu_info->com_info.mpdu_cnt_fcs_err;
365 	qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap,
366 		     &ppdu_info->com_info.mpdu_fcs_ok_bitmap,
367 		     HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
368 		     sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0]));
369 
370 	hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status);
371 }
372 
373 #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, word_1, word_2, \
374 					ppdu_info, rssi_info_tlv) \
375 	{						\
376 	ppdu_info->rx_status.rssi_chain[chain][0] = \
377 			HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\
378 				   RSSI_PRI20_CHAIN##chain); \
379 	ppdu_info->rx_status.rssi_chain[chain][1] = \
380 			HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\
381 				   RSSI_EXT20_CHAIN##chain); \
382 	ppdu_info->rx_status.rssi_chain[chain][2] = \
383 			HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\
384 				   RSSI_EXT40_LOW20_CHAIN##chain); \
385 	ppdu_info->rx_status.rssi_chain[chain][3] = \
386 			HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\
387 				   RSSI_EXT40_HIGH20_CHAIN##chain); \
388 	ppdu_info->rx_status.rssi_chain[chain][4] = \
389 			HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\
390 				   RSSI_EXT80_LOW20_CHAIN##chain); \
391 	ppdu_info->rx_status.rssi_chain[chain][5] = \
392 			HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\
393 				   RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \
394 	ppdu_info->rx_status.rssi_chain[chain][6] = \
395 			HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\
396 				   RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \
397 	ppdu_info->rx_status.rssi_chain[chain][7] = \
398 			HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\
399 				   RSSI_EXT80_HIGH20_CHAIN##chain); \
400 	}						\
401 
402 #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \
403 	{HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, 0, 1, ppdu_info, rssi_info_tlv) \
404 	HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, 2, 3, ppdu_info, rssi_info_tlv) \
405 	HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, 4, 5, ppdu_info, rssi_info_tlv) \
406 	HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, 6, 7, ppdu_info, rssi_info_tlv) \
407 	HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, 8, 9, ppdu_info, rssi_info_tlv) \
408 	HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, 10, 11, ppdu_info, rssi_info_tlv) \
409 	HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, 12, 13, ppdu_info, rssi_info_tlv) \
410 	HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, 14, 15, ppdu_info, rssi_info_tlv)} \
411 
412 static inline uint32_t
hal_rx_update_rssi_chain(struct hal_rx_ppdu_info * ppdu_info,uint8_t * rssi_info_tlv)413 hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info,
414 			 uint8_t *rssi_info_tlv)
415 {
416 	HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv)
417 	return 0;
418 }
419 
420 #ifdef WLAN_TX_PKT_CAPTURE_ENH
421 static inline void
hal_get_qos_control(void * rx_tlv,struct hal_rx_ppdu_info * ppdu_info)422 hal_get_qos_control(void *rx_tlv,
423 		    struct hal_rx_ppdu_info *ppdu_info)
424 {
425 	ppdu_info->rx_info.qos_control_info_valid =
426 		HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
427 			   QOS_CONTROL_INFO_VALID);
428 
429 	if (ppdu_info->rx_info.qos_control_info_valid)
430 		ppdu_info->rx_info.qos_control =
431 			HAL_RX_GET(rx_tlv,
432 				   RX_PPDU_END_USER_STATS_5,
433 				   QOS_CONTROL_FIELD);
434 }
435 
436 static inline void
hal_get_mac_addr1(uint8_t * rx_mpdu_start,struct hal_rx_ppdu_info * ppdu_info)437 hal_get_mac_addr1(uint8_t *rx_mpdu_start,
438 		  struct hal_rx_ppdu_info *ppdu_info)
439 {
440 	if ((ppdu_info->sw_frame_group_id
441 	     == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) ||
442 	    (ppdu_info->sw_frame_group_id ==
443 	     HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) {
444 		ppdu_info->rx_info.mac_addr1_valid =
445 				HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start);
446 
447 		*(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] =
448 			HAL_RX_GET(rx_mpdu_start,
449 				   RX_MPDU_INFO_15,
450 				   MAC_ADDR_AD1_31_0);
451 		if (ppdu_info->sw_frame_group_id ==
452 		    HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) {
453 			*(uint16_t *)&ppdu_info->rx_info.mac_addr1[4] =
454 				HAL_RX_GET(rx_mpdu_start,
455 					   RX_MPDU_INFO_16,
456 					   MAC_ADDR_AD1_47_32);
457 		}
458 	}
459 }
460 #else
461 static inline void
hal_get_qos_control(void * rx_tlv,struct hal_rx_ppdu_info * ppdu_info)462 hal_get_qos_control(void *rx_tlv,
463 		    struct hal_rx_ppdu_info *ppdu_info)
464 {
465 }
466 
467 static inline void
hal_get_mac_addr1(uint8_t * rx_mpdu_start,struct hal_rx_ppdu_info * ppdu_info)468 hal_get_mac_addr1(uint8_t *rx_mpdu_start,
469 		  struct hal_rx_ppdu_info *ppdu_info)
470 {
471 }
472 #endif
473 
474 #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS
475 static inline void
hal_update_frame_type_cnt(uint8_t * rx_mpdu_start,struct hal_rx_ppdu_info * ppdu_info)476 hal_update_frame_type_cnt(uint8_t *rx_mpdu_start,
477 			  struct hal_rx_ppdu_info *ppdu_info)
478 {
479 	uint16_t frame_ctrl;
480 	uint8_t fc_type;
481 
482 	if (HAL_RX_GET_FC_VALID(rx_mpdu_start)) {
483 		frame_ctrl = HAL_RX_GET(rx_mpdu_start,
484 					RX_MPDU_INFO_14,
485 					MPDU_FRAME_CONTROL_FIELD);
486 		fc_type = HAL_RX_GET_FRAME_CTRL_TYPE(frame_ctrl);
487 		if (fc_type == HAL_RX_FRAME_CTRL_TYPE_MGMT)
488 			ppdu_info->frm_type_info.rx_mgmt_cnt++;
489 		else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_CTRL)
490 			ppdu_info->frm_type_info.rx_ctrl_cnt++;
491 		else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_DATA)
492 			ppdu_info->frm_type_info.rx_data_cnt++;
493 	}
494 }
495 #else
496 static inline void
hal_update_frame_type_cnt(uint8_t * rx_mpdu_start,struct hal_rx_ppdu_info * ppdu_info)497 hal_update_frame_type_cnt(uint8_t *rx_mpdu_start,
498 			  struct hal_rx_ppdu_info *ppdu_info)
499 {
500 }
501 #endif
502 
503 /**
504  * hal_rx_status_get_tlv_info_generic_rh() - process receive info TLV
505  * @rx_tlv_hdr: pointer to TLV header
506  * @ppduinfo: pointer to ppdu_info
507  * @hal_soc_hdl: HAL SOC handle
508  * @nbuf: pkt buffer
509  *
510  * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv
511  */
512 static inline uint32_t
hal_rx_status_get_tlv_info_generic_rh(void * rx_tlv_hdr,void * ppduinfo,hal_soc_handle_t hal_soc_hdl,qdf_nbuf_t nbuf)513 hal_rx_status_get_tlv_info_generic_rh(void *rx_tlv_hdr, void *ppduinfo,
514 				      hal_soc_handle_t hal_soc_hdl,
515 				      qdf_nbuf_t nbuf)
516 {
517 	struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
518 	uint32_t tlv_tag, user_id, tlv_len, value;
519 	uint8_t group_id = 0;
520 	uint8_t he_dcm = 0;
521 	uint8_t he_stbc = 0;
522 	uint16_t he_gi = 0;
523 	uint16_t he_ltf = 0;
524 	void *rx_tlv;
525 	bool unhandled = false;
526 	struct mon_rx_user_status *mon_rx_user_status;
527 	struct hal_rx_ppdu_info *ppdu_info =
528 			(struct hal_rx_ppdu_info *)ppduinfo;
529 
530 	tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
531 	user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr);
532 	tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
533 
534 	rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
535 
536 	qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
537 			   rx_tlv, tlv_len);
538 
539 	switch (tlv_tag) {
540 	case WIFIRX_PPDU_START_E:
541 	{
542 		if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id ==
543 		    HAL_RX_GET(rx_tlv, RX_PPDU_START_0, PHY_PPDU_ID)))
544 			hal_err("Matching ppdu_id(%u) detected",
545 				 ppdu_info->com_info.last_ppdu_id);
546 
547 		/* Reset ppdu_info before processing the ppdu */
548 		qdf_mem_zero(ppdu_info,
549 			     sizeof(struct hal_rx_ppdu_info));
550 
551 		ppdu_info->com_info.last_ppdu_id =
552 			ppdu_info->com_info.ppdu_id =
553 				HAL_RX_GET(rx_tlv, RX_PPDU_START_0,
554 					   PHY_PPDU_ID);
555 
556 		/* channel number is set in PHY meta data */
557 		ppdu_info->rx_status.chan_num =
558 			(HAL_RX_GET(rx_tlv, RX_PPDU_START_1,
559 				SW_PHY_META_DATA) & 0x0000FFFF);
560 		ppdu_info->rx_status.chan_freq =
561 			(HAL_RX_GET(rx_tlv, RX_PPDU_START_1,
562 				SW_PHY_META_DATA) & 0xFFFF0000) >> 16;
563 		if (ppdu_info->rx_status.chan_num) {
564 			ppdu_info->rx_status.chan_freq =
565 				hal_rx_radiotap_num_to_freq(
566 				ppdu_info->rx_status.chan_num,
567 				 ppdu_info->rx_status.chan_freq);
568 		}
569 		ppdu_info->com_info.ppdu_timestamp =
570 			HAL_RX_GET(rx_tlv, RX_PPDU_START_2,
571 				   PPDU_START_TIMESTAMP);
572 		ppdu_info->rx_status.ppdu_timestamp =
573 			ppdu_info->com_info.ppdu_timestamp;
574 		ppdu_info->rx_state = HAL_RX_MON_PPDU_START;
575 
576 		break;
577 	}
578 
579 	case WIFIRX_PPDU_START_USER_INFO_E:
580 		break;
581 
582 	case WIFIRX_PPDU_END_E:
583 		dp_nofl_debug("[%s][%d] ppdu_end_e len=%d",
584 			      __func__, __LINE__, tlv_len);
585 		/* This is followed by sub-TLVs of PPDU_END */
586 		ppdu_info->rx_state = HAL_RX_MON_PPDU_END;
587 		break;
588 
589 	case WIFIPHYRX_PKT_END_E:
590 		hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info);
591 		break;
592 
593 	case WIFIRXPCU_PPDU_END_INFO_E:
594 		ppdu_info->rx_status.rx_antenna =
595 			HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, RX_ANTENNA);
596 		ppdu_info->rx_status.tsft =
597 			HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1,
598 				   WB_TIMESTAMP_UPPER_32);
599 		ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) |
600 			HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0,
601 				   WB_TIMESTAMP_LOWER_32);
602 		ppdu_info->rx_status.duration =
603 			HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8,
604 				   RX_PPDU_DURATION);
605 		hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info);
606 		hal_rx_get_phyrx_abort(hal, rx_tlv, ppdu_info);
607 		break;
608 
609 	/*
610 	 * WIFIRX_PPDU_END_USER_STATS_E comes for each user received.
611 	 * for MU, based on num users we see this tlv that many times.
612 	 */
613 	case WIFIRX_PPDU_END_USER_STATS_E:
614 	{
615 		unsigned long tid = 0;
616 		uint16_t seq = 0;
617 
618 		ppdu_info->rx_status.ast_index =
619 				HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4,
620 					   AST_INDEX);
621 
622 		tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12,
623 				 RECEIVED_QOS_DATA_TID_BITMAP);
624 		ppdu_info->rx_status.tid = qdf_find_first_bit(&tid,
625 							      sizeof(tid) * 8);
626 
627 		if (ppdu_info->rx_status.tid == (sizeof(tid) * 8))
628 			ppdu_info->rx_status.tid = HAL_TID_INVALID;
629 
630 		ppdu_info->rx_status.tcp_msdu_count =
631 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
632 				   TCP_MSDU_COUNT) +
633 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
634 				   TCP_ACK_MSDU_COUNT);
635 		ppdu_info->rx_status.udp_msdu_count =
636 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
637 				   UDP_MSDU_COUNT);
638 		ppdu_info->rx_status.other_msdu_count =
639 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
640 				   OTHER_MSDU_COUNT);
641 
642 		if (ppdu_info->sw_frame_group_id
643 		    != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) {
644 			ppdu_info->rx_status.frame_control_info_valid =
645 				HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
646 					   FRAME_CONTROL_INFO_VALID);
647 
648 			if (ppdu_info->rx_status.frame_control_info_valid)
649 				ppdu_info->rx_status.frame_control =
650 					HAL_RX_GET(rx_tlv,
651 						   RX_PPDU_END_USER_STATS_4,
652 						   FRAME_CONTROL_FIELD);
653 
654 			hal_get_qos_control(rx_tlv, ppdu_info);
655 		}
656 
657 		ppdu_info->rx_status.data_sequence_control_info_valid =
658 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
659 				   DATA_SEQUENCE_CONTROL_INFO_VALID);
660 
661 		seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5,
662 				 FIRST_DATA_SEQ_CTRL);
663 		if (ppdu_info->rx_status.data_sequence_control_info_valid)
664 			ppdu_info->rx_status.first_data_seq_ctrl = seq;
665 
666 		ppdu_info->rx_status.preamble_type =
667 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
668 				   HT_CONTROL_FIELD_PKT_TYPE);
669 		switch (ppdu_info->rx_status.preamble_type) {
670 		case HAL_RX_PKT_TYPE_11N:
671 			ppdu_info->rx_status.ht_flags = 1;
672 			ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT;
673 			break;
674 		case HAL_RX_PKT_TYPE_11AC:
675 			ppdu_info->rx_status.vht_flags = 1;
676 			break;
677 		case HAL_RX_PKT_TYPE_11AX:
678 			ppdu_info->rx_status.he_flags = 1;
679 			break;
680 		default:
681 			break;
682 		}
683 
684 		ppdu_info->com_info.mpdu_cnt_fcs_ok =
685 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
686 				   MPDU_CNT_FCS_OK);
687 		ppdu_info->com_info.mpdu_cnt_fcs_err =
688 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2,
689 				   MPDU_CNT_FCS_ERR);
690 		if ((ppdu_info->com_info.mpdu_cnt_fcs_ok |
691 			ppdu_info->com_info.mpdu_cnt_fcs_err) > 1)
692 			ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG;
693 		else
694 			ppdu_info->rx_status.rs_flags &=
695 				(~IEEE80211_AMPDU_FLAG);
696 
697 		ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] =
698 				HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_7,
699 					   FCS_OK_BITMAP_31_0);
700 
701 		ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] =
702 				HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_8,
703 					   FCS_OK_BITMAP_63_32);
704 
705 		if (user_id < HAL_MAX_UL_MU_USERS) {
706 			mon_rx_user_status =
707 				&ppdu_info->rx_user_status[user_id];
708 
709 			hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status);
710 
711 			ppdu_info->com_info.num_users++;
712 
713 			hal_rx_populate_mu_user_info(rx_tlv, ppdu_info,
714 						     user_id,
715 						     mon_rx_user_status);
716 		}
717 		break;
718 	}
719 
720 	case WIFIRX_PPDU_END_USER_STATS_EXT_E:
721 		ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] =
722 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_1,
723 				   FCS_OK_BITMAP_95_64);
724 
725 		ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] =
726 			 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_2,
727 				    FCS_OK_BITMAP_127_96);
728 
729 		ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] =
730 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_3,
731 				   FCS_OK_BITMAP_159_128);
732 
733 		ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] =
734 			 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_4,
735 				    FCS_OK_BITMAP_191_160);
736 
737 		ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] =
738 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_5,
739 				   FCS_OK_BITMAP_223_192);
740 
741 		ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] =
742 			 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_6,
743 				    FCS_OK_BITMAP_255_224);
744 		break;
745 
746 	case WIFIRX_PPDU_END_STATUS_DONE_E:
747 		return HAL_TLV_STATUS_PPDU_DONE;
748 
749 	case WIFIDUMMY_E:
750 		return HAL_TLV_STATUS_BUF_DONE;
751 
752 	case WIFIPHYRX_HT_SIG_E:
753 	{
754 		uint8_t *ht_sig_info = (uint8_t *)rx_tlv +
755 				HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0,
756 				HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS);
757 		value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1,
758 				   FEC_CODING);
759 		ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
760 			1 : 0;
761 		ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info,
762 						      HT_SIG_INFO_0, MCS);
763 		ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs;
764 		ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info,
765 						     HT_SIG_INFO_0, CBW);
766 		ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info,
767 						      HT_SIG_INFO_1, SHORT_GI);
768 		ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
769 		ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >>
770 					    HT_SIG_SU_NSS_SHIFT) + 1;
771 		ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1);
772 		hal_rx_get_ht_sig_info(ppdu_info, ht_sig_info);
773 		break;
774 	}
775 
776 	case WIFIPHYRX_L_SIG_B_E:
777 	{
778 		uint8_t *l_sig_b_info = (uint8_t *)rx_tlv +
779 				HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0,
780 				L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS);
781 
782 		value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE);
783 		ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info);
784 		switch (value) {
785 		case 1:
786 			ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS;
787 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3;
788 			break;
789 		case 2:
790 			ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS;
791 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2;
792 			break;
793 		case 3:
794 			ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS;
795 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1;
796 			break;
797 		case 4:
798 			ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS;
799 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0;
800 			break;
801 		case 5:
802 			ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS;
803 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6;
804 			break;
805 		case 6:
806 			ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS;
807 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5;
808 			break;
809 		case 7:
810 			ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS;
811 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4;
812 			break;
813 		default:
814 			break;
815 		}
816 		ppdu_info->rx_status.cck_flag = 1;
817 		ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
818 	break;
819 	}
820 
821 	case WIFIPHYRX_L_SIG_A_E:
822 	{
823 		uint8_t *l_sig_a_info = (uint8_t *)rx_tlv +
824 				HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0,
825 				L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS);
826 
827 		value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE);
828 		ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info);
829 		switch (value) {
830 		case 8:
831 			ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS;
832 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0;
833 			break;
834 		case 9:
835 			ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS;
836 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1;
837 			break;
838 		case 10:
839 			ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS;
840 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2;
841 			break;
842 		case 11:
843 			ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS;
844 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3;
845 			break;
846 		case 12:
847 			ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS;
848 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4;
849 			break;
850 		case 13:
851 			ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS;
852 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5;
853 			break;
854 		case 14:
855 			ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS;
856 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6;
857 			break;
858 		case 15:
859 			ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS;
860 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7;
861 			break;
862 		default:
863 			break;
864 		}
865 		ppdu_info->rx_status.ofdm_flag = 1;
866 		ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
867 		hal_rx_get_l_sig_a_info(ppdu_info, l_sig_a_info);
868 	break;
869 	}
870 
871 	case WIFIPHYRX_VHT_SIG_A_E:
872 	{
873 		uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv +
874 				HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0,
875 				VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS);
876 
877 		value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1,
878 				SU_MU_CODING);
879 		ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
880 			1 : 0;
881 		group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0,
882 				      GROUP_ID);
883 		ppdu_info->rx_status.vht_flag_values5 = group_id;
884 		ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info,
885 				VHT_SIG_A_INFO_1, MCS);
886 		ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info,
887 				VHT_SIG_A_INFO_1, GI_SETTING);
888 
889 		switch (hal->target_type) {
890 		case TARGET_TYPE_QCA8074:
891 		case TARGET_TYPE_QCA8074V2:
892 		case TARGET_TYPE_QCA6018:
893 		case TARGET_TYPE_QCA5018:
894 		case TARGET_TYPE_QCN9000:
895 		case TARGET_TYPE_QCN6122:
896 #ifdef QCA_WIFI_QCA6390
897 		case TARGET_TYPE_QCA6390:
898 #endif
899 		case TARGET_TYPE_QCA6490:
900 			ppdu_info->rx_status.is_stbc =
901 				HAL_RX_GET(vht_sig_a_info,
902 					   VHT_SIG_A_INFO_0, STBC);
903 			value =  HAL_RX_GET(vht_sig_a_info,
904 					    VHT_SIG_A_INFO_0, N_STS);
905 			value = value & VHT_SIG_SU_NSS_MASK;
906 			if (ppdu_info->rx_status.is_stbc && (value > 0))
907 				value = ((value + 1) >> 1) - 1;
908 			ppdu_info->rx_status.nss =
909 				((value & VHT_SIG_SU_NSS_MASK) + 1);
910 
911 			break;
912 		case TARGET_TYPE_QCA6290:
913 #if !defined(QCA_WIFI_QCA6290_11AX)
914 			ppdu_info->rx_status.is_stbc =
915 				HAL_RX_GET(vht_sig_a_info,
916 					   VHT_SIG_A_INFO_0, STBC);
917 			value =  HAL_RX_GET(vht_sig_a_info,
918 					    VHT_SIG_A_INFO_0, N_STS);
919 			value = value & VHT_SIG_SU_NSS_MASK;
920 			if (ppdu_info->rx_status.is_stbc && (value > 0))
921 				value = ((value + 1) >> 1) - 1;
922 			ppdu_info->rx_status.nss =
923 				((value & VHT_SIG_SU_NSS_MASK) + 1);
924 #else
925 			ppdu_info->rx_status.nss = 0;
926 #endif
927 			break;
928 		case TARGET_TYPE_QCA6750:
929 			ppdu_info->rx_status.nss = 0;
930 			break;
931 		default:
932 			break;
933 		}
934 		ppdu_info->rx_status.vht_flag_values3[0] =
935 				(((ppdu_info->rx_status.mcs) << 4)
936 				| ppdu_info->rx_status.nss);
937 		ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info,
938 				VHT_SIG_A_INFO_0, BANDWIDTH);
939 		ppdu_info->rx_status.vht_flag_values2 =
940 			ppdu_info->rx_status.bw;
941 		ppdu_info->rx_status.vht_flag_values4 =
942 			HAL_RX_GET(vht_sig_a_info,
943 				   VHT_SIG_A_INFO_1, SU_MU_CODING);
944 
945 		ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info,
946 				VHT_SIG_A_INFO_1, BEAMFORMED);
947 		if (group_id == 0 || group_id == 63)
948 			ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
949 		else
950 			ppdu_info->rx_status.reception_type =
951 				HAL_RX_TYPE_MU_MIMO;
952 
953 		hal_rx_get_vht_sig_a_info(ppdu_info, vht_sig_a_info);
954 		break;
955 	}
956 	case WIFIPHYRX_HE_SIG_A_SU_E:
957 	{
958 		uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv +
959 			HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0,
960 			HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS);
961 		ppdu_info->rx_status.he_flags = 1;
962 		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
963 				   FORMAT_INDICATION);
964 		if (value == 0) {
965 			ppdu_info->rx_status.he_data1 =
966 				QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
967 		} else {
968 			ppdu_info->rx_status.he_data1 =
969 				 QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
970 		}
971 
972 		/* data1 */
973 		ppdu_info->rx_status.he_data1 |=
974 			QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
975 			QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN |
976 			QDF_MON_STATUS_HE_DL_UL_KNOWN |
977 			QDF_MON_STATUS_HE_MCS_KNOWN |
978 			QDF_MON_STATUS_HE_DCM_KNOWN |
979 			QDF_MON_STATUS_HE_CODING_KNOWN |
980 			QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
981 			QDF_MON_STATUS_HE_STBC_KNOWN |
982 			QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
983 			QDF_MON_STATUS_HE_DOPPLER_KNOWN;
984 
985 		/* data2 */
986 		ppdu_info->rx_status.he_data2 =
987 			QDF_MON_STATUS_HE_GI_KNOWN;
988 		ppdu_info->rx_status.he_data2 |=
989 			QDF_MON_STATUS_TXBF_KNOWN |
990 			QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
991 			QDF_MON_STATUS_TXOP_KNOWN |
992 			QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
993 			QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
994 			QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
995 
996 		/* data3 */
997 		value = HAL_RX_GET(he_sig_a_su_info,
998 				   HE_SIG_A_SU_INFO_0, BSS_COLOR_ID);
999 		ppdu_info->rx_status.he_data3 = value;
1000 		value = HAL_RX_GET(he_sig_a_su_info,
1001 				   HE_SIG_A_SU_INFO_0, BEAM_CHANGE);
1002 		value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT;
1003 		ppdu_info->rx_status.he_data3 |= value;
1004 		value = HAL_RX_GET(he_sig_a_su_info,
1005 				   HE_SIG_A_SU_INFO_0, DL_UL_FLAG);
1006 		value = value << QDF_MON_STATUS_DL_UL_SHIFT;
1007 		ppdu_info->rx_status.he_data3 |= value;
1008 
1009 		value = HAL_RX_GET(he_sig_a_su_info,
1010 				   HE_SIG_A_SU_INFO_0, TRANSMIT_MCS);
1011 		ppdu_info->rx_status.mcs = value;
1012 		value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
1013 		ppdu_info->rx_status.he_data3 |= value;
1014 
1015 		value = HAL_RX_GET(he_sig_a_su_info,
1016 				   HE_SIG_A_SU_INFO_0, DCM);
1017 		he_dcm = value;
1018 		value = value << QDF_MON_STATUS_DCM_SHIFT;
1019 		ppdu_info->rx_status.he_data3 |= value;
1020 		value = HAL_RX_GET(he_sig_a_su_info,
1021 				   HE_SIG_A_SU_INFO_1, CODING);
1022 		ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
1023 			1 : 0;
1024 		value = value << QDF_MON_STATUS_CODING_SHIFT;
1025 		ppdu_info->rx_status.he_data3 |= value;
1026 		value = HAL_RX_GET(he_sig_a_su_info,
1027 				   HE_SIG_A_SU_INFO_1,
1028 				   LDPC_EXTRA_SYMBOL);
1029 		value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
1030 		ppdu_info->rx_status.he_data3 |= value;
1031 		value = HAL_RX_GET(he_sig_a_su_info,
1032 				   HE_SIG_A_SU_INFO_1, STBC);
1033 		he_stbc = value;
1034 		value = value << QDF_MON_STATUS_STBC_SHIFT;
1035 		ppdu_info->rx_status.he_data3 |= value;
1036 
1037 		/* data4 */
1038 		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
1039 				   SPATIAL_REUSE);
1040 		ppdu_info->rx_status.he_data4 = value;
1041 
1042 		/* data5 */
1043 		value = HAL_RX_GET(he_sig_a_su_info,
1044 				   HE_SIG_A_SU_INFO_0, TRANSMIT_BW);
1045 		ppdu_info->rx_status.he_data5 = value;
1046 		ppdu_info->rx_status.bw = value;
1047 		value = HAL_RX_GET(he_sig_a_su_info,
1048 				   HE_SIG_A_SU_INFO_0, CP_LTF_SIZE);
1049 		switch (value) {
1050 		case 0:
1051 				he_gi = HE_GI_0_8;
1052 				he_ltf = HE_LTF_1_X;
1053 				break;
1054 		case 1:
1055 				he_gi = HE_GI_0_8;
1056 				he_ltf = HE_LTF_2_X;
1057 				break;
1058 		case 2:
1059 				he_gi = HE_GI_1_6;
1060 				he_ltf = HE_LTF_2_X;
1061 				break;
1062 		case 3:
1063 				if (he_dcm && he_stbc) {
1064 					he_gi = HE_GI_0_8;
1065 					he_ltf = HE_LTF_4_X;
1066 				} else {
1067 					he_gi = HE_GI_3_2;
1068 					he_ltf = HE_LTF_4_X;
1069 				}
1070 				break;
1071 		}
1072 		ppdu_info->rx_status.sgi = he_gi;
1073 		ppdu_info->rx_status.ltf_size = he_ltf;
1074 		hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf);
1075 		value = he_gi << QDF_MON_STATUS_GI_SHIFT;
1076 		ppdu_info->rx_status.he_data5 |= value;
1077 		value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
1078 		ppdu_info->rx_status.he_data5 |= value;
1079 
1080 		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS);
1081 		value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
1082 		ppdu_info->rx_status.he_data5 |= value;
1083 
1084 		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
1085 				   PACKET_EXTENSION_A_FACTOR);
1086 		value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
1087 		ppdu_info->rx_status.he_data5 |= value;
1088 
1089 		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF);
1090 		value = value << QDF_MON_STATUS_TXBF_SHIFT;
1091 		ppdu_info->rx_status.he_data5 |= value;
1092 		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
1093 				   PACKET_EXTENSION_PE_DISAMBIGUITY);
1094 		value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
1095 		ppdu_info->rx_status.he_data5 |= value;
1096 
1097 		/* data6 */
1098 		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS);
1099 		value++;
1100 		ppdu_info->rx_status.nss = value;
1101 		ppdu_info->rx_status.he_data6 = value;
1102 		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
1103 				   DOPPLER_INDICATION);
1104 		value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
1105 		ppdu_info->rx_status.he_data6 |= value;
1106 		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
1107 				   TXOP_DURATION);
1108 		value = value << QDF_MON_STATUS_TXOP_SHIFT;
1109 		ppdu_info->rx_status.he_data6 |= value;
1110 
1111 		ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info,
1112 							     HE_SIG_A_SU_INFO_1, TXBF);
1113 		ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
1114 		hal_rx_get_crc_he_sig_a_su_info(ppdu_info, he_sig_a_su_info);
1115 		break;
1116 	}
1117 	case WIFIPHYRX_HE_SIG_A_MU_DL_E:
1118 	{
1119 		uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv +
1120 			HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0,
1121 			HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS);
1122 
1123 		ppdu_info->rx_status.he_mu_flags = 1;
1124 
1125 		/* HE Flags */
1126 		/*data1*/
1127 		ppdu_info->rx_status.he_data1 =
1128 					QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
1129 		ppdu_info->rx_status.he_data1 |=
1130 			QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
1131 			QDF_MON_STATUS_HE_DL_UL_KNOWN |
1132 			QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
1133 			QDF_MON_STATUS_HE_STBC_KNOWN |
1134 			QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
1135 			QDF_MON_STATUS_HE_DOPPLER_KNOWN;
1136 
1137 		/* data2 */
1138 		ppdu_info->rx_status.he_data2 =
1139 			QDF_MON_STATUS_HE_GI_KNOWN;
1140 		ppdu_info->rx_status.he_data2 |=
1141 			QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
1142 			QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
1143 			QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
1144 			QDF_MON_STATUS_TXOP_KNOWN |
1145 			QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
1146 
1147 		/*data3*/
1148 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1149 				   HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID);
1150 		ppdu_info->rx_status.he_data3 = value;
1151 
1152 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1153 				   HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG);
1154 		value = value << QDF_MON_STATUS_DL_UL_SHIFT;
1155 		ppdu_info->rx_status.he_data3 |= value;
1156 
1157 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1158 				   HE_SIG_A_MU_DL_INFO_1,
1159 				   LDPC_EXTRA_SYMBOL);
1160 		value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
1161 		ppdu_info->rx_status.he_data3 |= value;
1162 
1163 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1164 				   HE_SIG_A_MU_DL_INFO_1, STBC);
1165 		he_stbc = value;
1166 		value = value << QDF_MON_STATUS_STBC_SHIFT;
1167 		ppdu_info->rx_status.he_data3 |= value;
1168 
1169 		/*data4*/
1170 		value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
1171 				   SPATIAL_REUSE);
1172 		ppdu_info->rx_status.he_data4 = value;
1173 
1174 		/*data5*/
1175 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1176 				   HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
1177 		ppdu_info->rx_status.he_data5 = value;
1178 		ppdu_info->rx_status.bw = value;
1179 
1180 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1181 				   HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE);
1182 		switch (value) {
1183 		case 0:
1184 			he_gi = HE_GI_0_8;
1185 			he_ltf = HE_LTF_4_X;
1186 			break;
1187 		case 1:
1188 			he_gi = HE_GI_0_8;
1189 			he_ltf = HE_LTF_2_X;
1190 			break;
1191 		case 2:
1192 			he_gi = HE_GI_1_6;
1193 			he_ltf = HE_LTF_2_X;
1194 			break;
1195 		case 3:
1196 			he_gi = HE_GI_3_2;
1197 			he_ltf = HE_LTF_4_X;
1198 			break;
1199 		}
1200 		ppdu_info->rx_status.sgi = he_gi;
1201 		ppdu_info->rx_status.ltf_size = he_ltf;
1202 		hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf);
1203 		value = he_gi << QDF_MON_STATUS_GI_SHIFT;
1204 		ppdu_info->rx_status.he_data5 |= value;
1205 
1206 		value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
1207 		ppdu_info->rx_status.he_data5 |= value;
1208 
1209 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1210 				   HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS);
1211 		value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
1212 		ppdu_info->rx_status.he_data5 |= value;
1213 
1214 		value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
1215 				   PACKET_EXTENSION_A_FACTOR);
1216 		value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
1217 		ppdu_info->rx_status.he_data5 |= value;
1218 
1219 		value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
1220 				   PACKET_EXTENSION_PE_DISAMBIGUITY);
1221 		value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
1222 		ppdu_info->rx_status.he_data5 |= value;
1223 
1224 		/*data6*/
1225 		value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
1226 				   DOPPLER_INDICATION);
1227 		value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
1228 		ppdu_info->rx_status.he_data6 |= value;
1229 
1230 		value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
1231 				   TXOP_DURATION);
1232 		value = value << QDF_MON_STATUS_TXOP_SHIFT;
1233 		ppdu_info->rx_status.he_data6 |= value;
1234 
1235 		/* HE-MU Flags */
1236 		/* HE-MU-flags1 */
1237 		ppdu_info->rx_status.he_flags1 =
1238 			QDF_MON_STATUS_SIG_B_MCS_KNOWN |
1239 			QDF_MON_STATUS_SIG_B_DCM_KNOWN |
1240 			QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
1241 			QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
1242 			QDF_MON_STATUS_RU_0_KNOWN;
1243 
1244 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1245 				   HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B);
1246 		ppdu_info->rx_status.he_flags1 |= value;
1247 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1248 				   HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B);
1249 		value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT;
1250 		ppdu_info->rx_status.he_flags1 |= value;
1251 
1252 		/* HE-MU-flags2 */
1253 		ppdu_info->rx_status.he_flags2 =
1254 			QDF_MON_STATUS_BW_KNOWN;
1255 
1256 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1257 				   HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
1258 		ppdu_info->rx_status.he_flags2 |= value;
1259 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1260 				   HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B);
1261 		value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
1262 		ppdu_info->rx_status.he_flags2 |= value;
1263 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1264 				   HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS);
1265 		value = value - 1;
1266 		value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
1267 		ppdu_info->rx_status.he_flags2 |= value;
1268 		ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
1269 		hal_rx_get_crc_he_sig_a_mu_dl_info(ppdu_info,
1270 						   he_sig_a_mu_dl_info);
1271 		break;
1272 	}
1273 	case WIFIPHYRX_HE_SIG_B1_MU_E:
1274 	{
1275 		uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv +
1276 			HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0,
1277 			HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS);
1278 
1279 		ppdu_info->rx_status.he_sig_b_common_known |=
1280 			QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0;
1281 		/* TODO: Check on the availability of other fields in
1282 		 * sig_b_common
1283 		 */
1284 
1285 		value = HAL_RX_GET(he_sig_b1_mu_info,
1286 				   HE_SIG_B1_MU_INFO_0, RU_ALLOCATION);
1287 		ppdu_info->rx_status.he_RU[0] = value;
1288 		ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
1289 		break;
1290 	}
1291 	case WIFIPHYRX_HE_SIG_B2_MU_E:
1292 	{
1293 		uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv +
1294 			HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0,
1295 			HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS);
1296 		/*
1297 		 * Not all "HE" fields can be updated from
1298 		 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
1299 		 * to populate rest of the "HE" fields for MU scenarios.
1300 		 */
1301 
1302 		/* HE-data1 */
1303 		ppdu_info->rx_status.he_data1 |=
1304 			QDF_MON_STATUS_HE_MCS_KNOWN |
1305 			QDF_MON_STATUS_HE_CODING_KNOWN;
1306 
1307 		/* HE-data2 */
1308 
1309 		/* HE-data3 */
1310 		value = HAL_RX_GET(he_sig_b2_mu_info,
1311 				   HE_SIG_B2_MU_INFO_0, STA_MCS);
1312 		ppdu_info->rx_status.mcs = value;
1313 		value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
1314 		ppdu_info->rx_status.he_data3 |= value;
1315 
1316 		value = HAL_RX_GET(he_sig_b2_mu_info,
1317 				   HE_SIG_B2_MU_INFO_0, STA_CODING);
1318 		value = value << QDF_MON_STATUS_CODING_SHIFT;
1319 		ppdu_info->rx_status.he_data3 |= value;
1320 
1321 		/* HE-data4 */
1322 		value = HAL_RX_GET(he_sig_b2_mu_info,
1323 				   HE_SIG_B2_MU_INFO_0, STA_ID);
1324 		value = value << QDF_MON_STATUS_STA_ID_SHIFT;
1325 		ppdu_info->rx_status.he_data4 |= value;
1326 
1327 		/* HE-data5 */
1328 
1329 		/* HE-data6 */
1330 		value = HAL_RX_GET(he_sig_b2_mu_info,
1331 				   HE_SIG_B2_MU_INFO_0, NSTS);
1332 		/* value n indicates n+1 spatial streams */
1333 		value++;
1334 		ppdu_info->rx_status.nss = value;
1335 		ppdu_info->rx_status.he_data6 |= value;
1336 
1337 		break;
1338 	}
1339 	case WIFIPHYRX_HE_SIG_B2_OFDMA_E:
1340 	{
1341 		uint8_t *he_sig_b2_ofdma_info =
1342 		(uint8_t *)rx_tlv +
1343 		HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0,
1344 		HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS);
1345 
1346 		/*
1347 		 * Not all "HE" fields can be updated from
1348 		 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
1349 		 * to populate rest of "HE" fields for MU OFDMA scenarios.
1350 		 */
1351 
1352 		/* HE-data1 */
1353 		ppdu_info->rx_status.he_data1 |=
1354 			QDF_MON_STATUS_HE_MCS_KNOWN |
1355 			QDF_MON_STATUS_HE_DCM_KNOWN |
1356 			QDF_MON_STATUS_HE_CODING_KNOWN;
1357 
1358 		/* HE-data2 */
1359 		ppdu_info->rx_status.he_data2 |=
1360 					QDF_MON_STATUS_TXBF_KNOWN;
1361 
1362 		/* HE-data3 */
1363 		value = HAL_RX_GET(he_sig_b2_ofdma_info,
1364 				   HE_SIG_B2_OFDMA_INFO_0, STA_MCS);
1365 		ppdu_info->rx_status.mcs = value;
1366 		value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
1367 		ppdu_info->rx_status.he_data3 |= value;
1368 
1369 		value = HAL_RX_GET(he_sig_b2_ofdma_info,
1370 				   HE_SIG_B2_OFDMA_INFO_0, STA_DCM);
1371 		he_dcm = value;
1372 		value = value << QDF_MON_STATUS_DCM_SHIFT;
1373 		ppdu_info->rx_status.he_data3 |= value;
1374 
1375 		value = HAL_RX_GET(he_sig_b2_ofdma_info,
1376 				   HE_SIG_B2_OFDMA_INFO_0, STA_CODING);
1377 		value = value << QDF_MON_STATUS_CODING_SHIFT;
1378 		ppdu_info->rx_status.he_data3 |= value;
1379 
1380 		/* HE-data4 */
1381 		value = HAL_RX_GET(he_sig_b2_ofdma_info,
1382 				   HE_SIG_B2_OFDMA_INFO_0, STA_ID);
1383 		value = value << QDF_MON_STATUS_STA_ID_SHIFT;
1384 		ppdu_info->rx_status.he_data4 |= value;
1385 
1386 		/* HE-data5 */
1387 		value = HAL_RX_GET(he_sig_b2_ofdma_info,
1388 				   HE_SIG_B2_OFDMA_INFO_0, TXBF);
1389 		value = value << QDF_MON_STATUS_TXBF_SHIFT;
1390 		ppdu_info->rx_status.he_data5 |= value;
1391 
1392 		/* HE-data6 */
1393 		value = HAL_RX_GET(he_sig_b2_ofdma_info,
1394 				   HE_SIG_B2_OFDMA_INFO_0, NSTS);
1395 		/* value n indicates n+1 spatial streams */
1396 		value++;
1397 		ppdu_info->rx_status.nss = value;
1398 		ppdu_info->rx_status.he_data6 |= value;
1399 		ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA;
1400 		break;
1401 	}
1402 	case WIFIPHYRX_RSSI_LEGACY_E:
1403 	{
1404 		uint8_t reception_type;
1405 		int8_t rssi_value;
1406 		uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv +
1407 			HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19,
1408 				      RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS);
1409 
1410 		ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv,
1411 			PHYRX_RSSI_LEGACY_35, RSSI_COMB);
1412 		ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv);
1413 		ppdu_info->rx_status.he_re = 0;
1414 
1415 		reception_type = HAL_RX_GET(rx_tlv,
1416 					    PHYRX_RSSI_LEGACY_0,
1417 					    RECEPTION_TYPE);
1418 		switch (reception_type) {
1419 		case QDF_RECEPTION_TYPE_ULOFMDA:
1420 			ppdu_info->rx_status.reception_type =
1421 				HAL_RX_TYPE_MU_OFDMA;
1422 			ppdu_info->rx_status.ulofdma_flag = 1;
1423 			ppdu_info->rx_status.he_data1 =
1424 				QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
1425 			break;
1426 		case QDF_RECEPTION_TYPE_ULMIMO:
1427 			ppdu_info->rx_status.reception_type =
1428 				HAL_RX_TYPE_MU_MIMO;
1429 			ppdu_info->rx_status.he_data1 =
1430 				QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
1431 			break;
1432 		default:
1433 			ppdu_info->rx_status.reception_type =
1434 				HAL_RX_TYPE_SU;
1435 			break;
1436 		}
1437 		hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv);
1438 		rssi_value = HAL_RX_GET(rssi_info_tlv,
1439 					RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0);
1440 		ppdu_info->rx_status.rssi[0] = rssi_value;
1441 		dp_nofl_debug("RSSI_PRI20_CHAIN0: %d\n", rssi_value);
1442 
1443 		rssi_value = HAL_RX_GET(rssi_info_tlv,
1444 					RECEIVE_RSSI_INFO_2, RSSI_PRI20_CHAIN1);
1445 		ppdu_info->rx_status.rssi[1] = rssi_value;
1446 		dp_nofl_debug("RSSI_PRI20_CHAIN1: %d\n", rssi_value);
1447 
1448 		rssi_value = HAL_RX_GET(rssi_info_tlv,
1449 					RECEIVE_RSSI_INFO_4, RSSI_PRI20_CHAIN2);
1450 		ppdu_info->rx_status.rssi[2] = rssi_value;
1451 		dp_nofl_debug("RSSI_PRI20_CHAIN2: %d\n", rssi_value);
1452 
1453 		rssi_value = HAL_RX_GET(rssi_info_tlv,
1454 					RECEIVE_RSSI_INFO_6, RSSI_PRI20_CHAIN3);
1455 		ppdu_info->rx_status.rssi[3] = rssi_value;
1456 		dp_nofl_debug("RSSI_PRI20_CHAIN3: %d\n", rssi_value);
1457 
1458 		rssi_value = HAL_RX_GET(rssi_info_tlv,
1459 					RECEIVE_RSSI_INFO_8, RSSI_PRI20_CHAIN4);
1460 		ppdu_info->rx_status.rssi[4] = rssi_value;
1461 		dp_nofl_debug("RSSI_PRI20_CHAIN4: %d\n", rssi_value);
1462 
1463 		rssi_value = HAL_RX_GET(rssi_info_tlv,
1464 					RECEIVE_RSSI_INFO_10,
1465 					RSSI_PRI20_CHAIN5);
1466 		ppdu_info->rx_status.rssi[5] = rssi_value;
1467 		dp_nofl_debug("RSSI_PRI20_CHAIN5: %d\n", rssi_value);
1468 
1469 		rssi_value = HAL_RX_GET(rssi_info_tlv,
1470 					RECEIVE_RSSI_INFO_12,
1471 					RSSI_PRI20_CHAIN6);
1472 		ppdu_info->rx_status.rssi[6] = rssi_value;
1473 		dp_nofl_debug("RSSI_PRI20_CHAIN6: %d\n", rssi_value);
1474 
1475 		rssi_value = HAL_RX_GET(rssi_info_tlv,
1476 					RECEIVE_RSSI_INFO_14,
1477 					RSSI_PRI20_CHAIN7);
1478 		ppdu_info->rx_status.rssi[7] = rssi_value;
1479 		dp_nofl_debug("RSSI_PRI20_CHAIN7: %d\n", rssi_value);
1480 		break;
1481 	}
1482 	case WIFIPHYRX_OTHER_RECEIVE_INFO_E:
1483 		hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr,
1484 							 ppdu_info);
1485 		break;
1486 	case WIFIRX_HEADER_E:
1487 	{
1488 		struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info;
1489 
1490 		if (ppdu_info->fcs_ok_cnt >=
1491 		    HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) {
1492 			hal_err("Number of MPDUs(%d) per status buff exceeded",
1493 				ppdu_info->fcs_ok_cnt);
1494 			break;
1495 		}
1496 
1497 		/* Update first_msdu_payload for every mpdu and increment
1498 		 * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV
1499 		 */
1500 		ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload =
1501 			rx_tlv;
1502 		ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len;
1503 		ppdu_info->msdu_info.first_msdu_payload = rx_tlv;
1504 		ppdu_info->msdu_info.payload_len = tlv_len;
1505 		ppdu_info->user_id = user_id;
1506 		ppdu_info->hdr_len = tlv_len;
1507 		ppdu_info->data = rx_tlv;
1508 		ppdu_info->data += 4;
1509 
1510 		/* for every RX_HEADER TLV increment mpdu_cnt */
1511 		com_info->mpdu_cnt++;
1512 		return HAL_TLV_STATUS_HEADER;
1513 	}
1514 	case WIFIRX_MPDU_START_E:
1515 	{
1516 		uint8_t *rx_mpdu_start = (uint8_t *)rx_tlv;
1517 		uint32_t ppdu_id = HAL_RX_GET_PPDU_ID(rx_mpdu_start);
1518 		uint8_t filter_category = 0;
1519 
1520 		hal_update_frame_type_cnt(rx_mpdu_start, ppdu_info);
1521 
1522 		ppdu_info->nac_info.fc_valid =
1523 				HAL_RX_GET_FC_VALID(rx_mpdu_start);
1524 
1525 		ppdu_info->nac_info.to_ds_flag =
1526 				HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start);
1527 
1528 		ppdu_info->nac_info.frame_control =
1529 			HAL_RX_GET(rx_mpdu_start,
1530 				   RX_MPDU_INFO_14,
1531 				   MPDU_FRAME_CONTROL_FIELD);
1532 
1533 		ppdu_info->sw_frame_group_id =
1534 			HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start);
1535 
1536 		ppdu_info->rx_user_status[user_id].sw_peer_id =
1537 			HAL_RX_GET_SW_PEER_ID(rx_mpdu_start);
1538 
1539 		if (ppdu_info->sw_frame_group_id ==
1540 		    HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) {
1541 			ppdu_info->rx_status.frame_control_info_valid =
1542 				ppdu_info->nac_info.fc_valid;
1543 			ppdu_info->rx_status.frame_control =
1544 				ppdu_info->nac_info.frame_control;
1545 		}
1546 
1547 		hal_get_mac_addr1(rx_mpdu_start,
1548 				  ppdu_info);
1549 
1550 		ppdu_info->nac_info.mac_addr2_valid =
1551 				HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start);
1552 
1553 		*(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] =
1554 			HAL_RX_GET(rx_mpdu_start,
1555 				   RX_MPDU_INFO_16,
1556 				   MAC_ADDR_AD2_15_0);
1557 
1558 		*(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] =
1559 			HAL_RX_GET(rx_mpdu_start,
1560 				   RX_MPDU_INFO_17,
1561 				   MAC_ADDR_AD2_47_16);
1562 
1563 		if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) {
1564 			ppdu_info->rx_status.prev_ppdu_id = ppdu_id;
1565 			ppdu_info->rx_status.ppdu_len =
1566 				HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
1567 					   MPDU_LENGTH);
1568 		} else {
1569 			ppdu_info->rx_status.ppdu_len +=
1570 				HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
1571 					   MPDU_LENGTH);
1572 		}
1573 
1574 		filter_category =
1575 				HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start);
1576 
1577 		if (filter_category == 0)
1578 			ppdu_info->rx_status.rxpcu_filter_pass = 1;
1579 		else if (filter_category == 1)
1580 			ppdu_info->rx_status.monitor_direct_used = 1;
1581 
1582 		ppdu_info->nac_info.mcast_bcast =
1583 			HAL_RX_GET(rx_mpdu_start,
1584 				   RX_MPDU_INFO_13,
1585 				   MCAST_BCAST);
1586 		break;
1587 	}
1588 	case WIFIRX_MPDU_END_E:
1589 		ppdu_info->user_id = user_id;
1590 		ppdu_info->fcs_err =
1591 			HAL_RX_GET(rx_tlv, RX_MPDU_END_1,
1592 				   FCS_ERR);
1593 		return HAL_TLV_STATUS_MPDU_END;
1594 	case WIFIRX_MSDU_END_E:
1595 		if (user_id < HAL_MAX_UL_MU_USERS) {
1596 			ppdu_info->rx_msdu_info[user_id].cce_metadata =
1597 				HAL_RX_MSDU_END_CCE_METADATA_GET(rx_tlv);
1598 			ppdu_info->rx_msdu_info[user_id].fse_metadata =
1599 				HAL_RX_MSDU_END_FSE_METADATA_GET(rx_tlv);
1600 			ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout =
1601 				HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(rx_tlv);
1602 			ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid =
1603 				HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(rx_tlv);
1604 			ppdu_info->rx_msdu_info[user_id].flow_idx =
1605 				HAL_RX_MSDU_END_FLOW_IDX_GET(rx_tlv);
1606 		}
1607 		return HAL_TLV_STATUS_MSDU_END;
1608 	case 0:
1609 		return HAL_TLV_STATUS_PPDU_DONE;
1610 
1611 	default:
1612 		if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info))
1613 			unhandled = false;
1614 		else
1615 			unhandled = true;
1616 		break;
1617 	}
1618 
1619 	if (!unhandled)
1620 		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
1621 			  "%s TLV type: %d, TLV len:%d %s",
1622 			  __func__, tlv_tag, tlv_len,
1623 			  unhandled == true ? "unhandled" : "");
1624 
1625 	qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
1626 			   rx_tlv, tlv_len);
1627 
1628 	return HAL_TLV_STATUS_PPDU_NOT_DONE;
1629 }
1630 
1631 /**
1632  * hal_rx_dump_rx_attention_tlv_generic_rh: dump RX attention TLV in structured
1633  *					    humman readable format.
1634  * @pkttlvs: pointer to pkttlvs.
1635  * @dbg_level: log level.
1636  *
1637  * Return: void
1638  */
hal_rx_dump_rx_attention_tlv_generic_rh(void * pkttlvs,uint8_t dbg_level)1639 static inline void hal_rx_dump_rx_attention_tlv_generic_rh(void *pkttlvs,
1640 							   uint8_t dbg_level)
1641 {
1642 	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
1643 	struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
1644 
1645 	hal_verbose_debug("rx_attention tlv (1/2) - "
1646 			  "rxpcu_mpdu_filter_in_category: %x "
1647 			  "sw_frame_group_id: %x "
1648 			  "reserved_0: %x "
1649 			  "phy_ppdu_id: %x "
1650 			  "first_mpdu : %x "
1651 			  "reserved_1a: %x "
1652 			  "mcast_bcast: %x "
1653 			  "ast_index_not_found: %x "
1654 			  "ast_index_timeout: %x "
1655 			  "power_mgmt: %x "
1656 			  "non_qos: %x "
1657 			  "null_data: %x "
1658 			  "mgmt_type: %x "
1659 			  "ctrl_type: %x "
1660 			  "more_data: %x "
1661 			  "eosp: %x "
1662 			  "a_msdu_error: %x "
1663 			  "fragment_flag: %x "
1664 			  "order: %x "
1665 			  "cce_match: %x "
1666 			  "overflow_err: %x "
1667 			  "msdu_length_err: %x "
1668 			  "tcp_udp_chksum_fail: %x "
1669 			  "ip_chksum_fail: %x "
1670 			  "sa_idx_invalid: %x "
1671 			  "da_idx_invalid: %x "
1672 			  "reserved_1b: %x "
1673 			  "rx_in_tx_decrypt_byp: %x ",
1674 			  rx_attn->rxpcu_mpdu_filter_in_category,
1675 			  rx_attn->sw_frame_group_id,
1676 			  rx_attn->reserved_0,
1677 			  rx_attn->phy_ppdu_id,
1678 			  rx_attn->first_mpdu,
1679 			  rx_attn->reserved_1a,
1680 			  rx_attn->mcast_bcast,
1681 			  rx_attn->ast_index_not_found,
1682 			  rx_attn->ast_index_timeout,
1683 			  rx_attn->power_mgmt,
1684 			  rx_attn->non_qos,
1685 			  rx_attn->null_data,
1686 			  rx_attn->mgmt_type,
1687 			  rx_attn->ctrl_type,
1688 			  rx_attn->more_data,
1689 			  rx_attn->eosp,
1690 			  rx_attn->a_msdu_error,
1691 			  rx_attn->fragment_flag,
1692 			  rx_attn->order,
1693 			  rx_attn->cce_match,
1694 			  rx_attn->overflow_err,
1695 			  rx_attn->msdu_length_err,
1696 			  rx_attn->tcp_udp_chksum_fail,
1697 			  rx_attn->ip_chksum_fail,
1698 			  rx_attn->sa_idx_invalid,
1699 			  rx_attn->da_idx_invalid,
1700 			  rx_attn->reserved_1b,
1701 			  rx_attn->rx_in_tx_decrypt_byp);
1702 
1703 	hal_verbose_debug("rx_attention tlv (2/2) - "
1704 			  "encrypt_required: %x "
1705 			  "directed: %x "
1706 			  "buffer_fragment: %x "
1707 			  "mpdu_length_err: %x "
1708 			  "tkip_mic_err: %x "
1709 			  "decrypt_err: %x "
1710 			  "unencrypted_frame_err: %x "
1711 			  "fcs_err: %x "
1712 			  "flow_idx_timeout: %x "
1713 			  "flow_idx_invalid: %x "
1714 			  "wifi_parser_error: %x "
1715 			  "amsdu_parser_error: %x "
1716 			  "sa_idx_timeout: %x "
1717 			  "da_idx_timeout: %x "
1718 			  "msdu_limit_error: %x "
1719 			  "da_is_valid: %x "
1720 			  "da_is_mcbc: %x "
1721 			  "sa_is_valid: %x "
1722 			  "decrypt_status_code: %x "
1723 			  "rx_bitmap_not_updated: %x "
1724 			  "reserved_2: %x "
1725 			  "msdu_done: %x ",
1726 			  rx_attn->encrypt_required,
1727 			  rx_attn->directed,
1728 			  rx_attn->buffer_fragment,
1729 			  rx_attn->mpdu_length_err,
1730 			  rx_attn->tkip_mic_err,
1731 			  rx_attn->decrypt_err,
1732 			  rx_attn->unencrypted_frame_err,
1733 			  rx_attn->fcs_err,
1734 			  rx_attn->flow_idx_timeout,
1735 			  rx_attn->flow_idx_invalid,
1736 			  rx_attn->wifi_parser_error,
1737 			  rx_attn->amsdu_parser_error,
1738 			  rx_attn->sa_idx_timeout,
1739 			  rx_attn->da_idx_timeout,
1740 			  rx_attn->msdu_limit_error,
1741 			  rx_attn->da_is_valid,
1742 			  rx_attn->da_is_mcbc,
1743 			  rx_attn->sa_is_valid,
1744 			  rx_attn->decrypt_status_code,
1745 			  rx_attn->rx_bitmap_not_updated,
1746 			  rx_attn->reserved_2,
1747 			  rx_attn->msdu_done);
1748 }
1749 
1750 /**
1751  * hal_rx_dump_mpdu_end_tlv_generic_rh: dump RX mpdu_end TLV in structured
1752  *					human readable format.
1753  * @pkttlvs: pointer to pkttlvs.
1754  * @dbg_level: log level.
1755  *
1756  * Return: void
1757  */
hal_rx_dump_mpdu_end_tlv_generic_rh(void * pkttlvs,uint8_t dbg_level)1758 static inline void hal_rx_dump_mpdu_end_tlv_generic_rh(void *pkttlvs,
1759 						       uint8_t dbg_level)
1760 {
1761 	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
1762 	struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
1763 
1764 	hal_verbose_debug("rx_mpdu_end tlv - "
1765 			  "rxpcu_mpdu_filter_in_category: %x "
1766 			  "sw_frame_group_id: %x "
1767 			  "phy_ppdu_id: %x "
1768 			  "unsup_ktype_short_frame: %x "
1769 			  "rx_in_tx_decrypt_byp: %x "
1770 			  "overflow_err: %x "
1771 			  "mpdu_length_err: %x "
1772 			  "tkip_mic_err: %x "
1773 			  "decrypt_err: %x "
1774 			  "unencrypted_frame_err: %x "
1775 			  "pn_fields_contain_valid_info: %x "
1776 			  "fcs_err: %x "
1777 			  "msdu_length_err: %x "
1778 			  "rxdma0_destination_ring: %x "
1779 			  "rxdma1_destination_ring: %x "
1780 			  "decrypt_status_code: %x "
1781 			  "rx_bitmap_not_updated: %x ",
1782 			  mpdu_end->rxpcu_mpdu_filter_in_category,
1783 			  mpdu_end->sw_frame_group_id,
1784 			  mpdu_end->phy_ppdu_id,
1785 			  mpdu_end->unsup_ktype_short_frame,
1786 			  mpdu_end->rx_in_tx_decrypt_byp,
1787 			  mpdu_end->overflow_err,
1788 			  mpdu_end->mpdu_length_err,
1789 			  mpdu_end->tkip_mic_err,
1790 			  mpdu_end->decrypt_err,
1791 			  mpdu_end->unencrypted_frame_err,
1792 			  mpdu_end->pn_fields_contain_valid_info,
1793 			  mpdu_end->fcs_err,
1794 			  mpdu_end->msdu_length_err,
1795 			  mpdu_end->rxdma0_destination_ring,
1796 			  mpdu_end->rxdma1_destination_ring,
1797 			  mpdu_end->decrypt_status_code,
1798 			  mpdu_end->rx_bitmap_not_updated);
1799 }
1800 
1801 #ifdef NO_RX_PKT_HDR_TLV
hal_rx_dump_pkt_hdr_tlv_generic_rh(void * pkttlvs,uint8_t dbg_level)1802 static inline void hal_rx_dump_pkt_hdr_tlv_generic_rh(void *pkttlvs,
1803 						      uint8_t dbg_level)
1804 {
1805 }
1806 #else
1807 /**
1808  * hal_rx_dump_pkt_hdr_tlv_generic_rh: dump RX pkt header TLV in hex format
1809  * @pkttlvs: pointer to pkttlvs.
1810  * @dbg_level: log level.
1811  *
1812  * Return: void
1813  */
hal_rx_dump_pkt_hdr_tlv_generic_rh(void * pkttlvs,uint8_t dbg_level)1814 static inline void hal_rx_dump_pkt_hdr_tlv_generic_rh(void *pkttlvs,
1815 						      uint8_t dbg_level)
1816 {
1817 	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
1818 	struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv;
1819 
1820 	hal_verbose_debug("\n---------------\nrx_pkt_hdr_tlv"
1821 			  "\n---------------\nphy_ppdu_id %d ",
1822 			  pkt_hdr_tlv->phy_ppdu_id);
1823 	hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 128);
1824 }
1825 #endif
1826 
1827 /**
1828  * hal_rx_dump_mpdu_start_tlv_generic_rh: dump RX mpdu_start TLV in structured
1829  *					  human readable format.
1830  * @pkttlvs: pointer to pkttlvs.
1831  * @dbg_level: log level.
1832  *
1833  * Return: void
1834  */
hal_rx_dump_mpdu_start_tlv_generic_rh(void * pkttlvs,uint8_t dbg_level)1835 static inline void hal_rx_dump_mpdu_start_tlv_generic_rh(void *pkttlvs,
1836 							 uint8_t dbg_level)
1837 {
1838 	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
1839 	struct rx_mpdu_start *mpdu_start =
1840 					&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1841 	struct rx_mpdu_info *mpdu_info =
1842 		(struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details;
1843 
1844 	hal_verbose_debug(
1845 			  "rx_mpdu_start tlv (1/5) - "
1846 			  "rxpcu_mpdu_filter_in_category: %x "
1847 			  "sw_frame_group_id: %x "
1848 			  "ndp_frame: %x "
1849 			  "phy_err: %x "
1850 			  "phy_err_during_mpdu_header: %x "
1851 			  "protocol_version_err: %x "
1852 			  "ast_based_lookup_valid: %x "
1853 			  "phy_ppdu_id: %x "
1854 			  "ast_index: %x "
1855 			  "sw_peer_id: %x "
1856 			  "mpdu_frame_control_valid: %x "
1857 			  "mpdu_duration_valid: %x "
1858 			  "mac_addr_ad1_valid: %x "
1859 			  "mac_addr_ad2_valid: %x "
1860 			  "mac_addr_ad3_valid: %x "
1861 			  "mac_addr_ad4_valid: %x "
1862 			  "mpdu_sequence_control_valid: %x "
1863 			  "mpdu_qos_control_valid: %x "
1864 			  "mpdu_ht_control_valid: %x "
1865 			  "frame_encryption_info_valid: %x ",
1866 			  mpdu_info->rxpcu_mpdu_filter_in_category,
1867 			  mpdu_info->sw_frame_group_id,
1868 			  mpdu_info->ndp_frame,
1869 			  mpdu_info->phy_err,
1870 			  mpdu_info->phy_err_during_mpdu_header,
1871 			  mpdu_info->protocol_version_err,
1872 			  mpdu_info->ast_based_lookup_valid,
1873 			  mpdu_info->phy_ppdu_id,
1874 			  mpdu_info->ast_index,
1875 			  mpdu_info->sw_peer_id,
1876 			  mpdu_info->mpdu_frame_control_valid,
1877 			  mpdu_info->mpdu_duration_valid,
1878 			  mpdu_info->mac_addr_ad1_valid,
1879 			  mpdu_info->mac_addr_ad2_valid,
1880 			  mpdu_info->mac_addr_ad3_valid,
1881 			  mpdu_info->mac_addr_ad4_valid,
1882 			  mpdu_info->mpdu_sequence_control_valid,
1883 			  mpdu_info->mpdu_qos_control_valid,
1884 			  mpdu_info->mpdu_ht_control_valid,
1885 			  mpdu_info->frame_encryption_info_valid);
1886 
1887 	hal_verbose_debug(
1888 			  "rx_mpdu_start tlv (2/5) - "
1889 			  "fr_ds: %x "
1890 			  "to_ds: %x "
1891 			  "encrypted: %x "
1892 			  "mpdu_retry: %x "
1893 			  "mpdu_sequence_number: %x "
1894 			  "epd_en: %x "
1895 			  "all_frames_shall_be_encrypted: %x "
1896 			  "encrypt_type: %x "
1897 			  "bssid_hit: %x "
1898 			  "bssid_number: %x "
1899 			  "tid: %x "
1900 			  "pn_31_0: %x "
1901 			  "pn_63_32: %x "
1902 			  "pn_95_64: %x "
1903 			  "pn_127_96: %x "
1904 			  "peer_meta_data: %x "
1905 			  "rxpt_classify_info.reo_destination_indication: %x "
1906 			  "rxpt_classify_info.use_flow_id_toeplitz_clfy: %x "
1907 			  "rx_reo_queue_desc_addr_31_0: %x ",
1908 			  mpdu_info->fr_ds,
1909 			  mpdu_info->to_ds,
1910 			  mpdu_info->encrypted,
1911 			  mpdu_info->mpdu_retry,
1912 			  mpdu_info->mpdu_sequence_number,
1913 			  mpdu_info->epd_en,
1914 			  mpdu_info->all_frames_shall_be_encrypted,
1915 			  mpdu_info->encrypt_type,
1916 			  mpdu_info->bssid_hit,
1917 			  mpdu_info->bssid_number,
1918 			  mpdu_info->tid,
1919 			  mpdu_info->pn_31_0,
1920 			  mpdu_info->pn_63_32,
1921 			  mpdu_info->pn_95_64,
1922 			  mpdu_info->pn_127_96,
1923 			  mpdu_info->peer_meta_data,
1924 			  mpdu_info->rxpt_classify_info_details.reo_destination_indication,
1925 			  mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy,
1926 			  mpdu_info->rx_reo_queue_desc_addr_31_0);
1927 
1928 	hal_verbose_debug(
1929 			  "rx_mpdu_start tlv (3/5) - "
1930 			  "rx_reo_queue_desc_addr_39_32: %x "
1931 			  "receive_queue_number: %x "
1932 			  "pre_delim_err_warning: %x "
1933 			  "first_delim_err: %x "
1934 			  "key_id_octet: %x "
1935 			  "new_peer_entry: %x "
1936 			  "decrypt_needed: %x "
1937 			  "decap_type: %x "
1938 			  "rx_insert_vlan_c_tag_padding: %x "
1939 			  "rx_insert_vlan_s_tag_padding: %x "
1940 			  "strip_vlan_c_tag_decap: %x "
1941 			  "strip_vlan_s_tag_decap: %x "
1942 			  "pre_delim_count: %x "
1943 			  "ampdu_flag: %x "
1944 			  "bar_frame: %x "
1945 			  "mpdu_length: %x "
1946 			  "first_mpdu: %x "
1947 			  "mcast_bcast: %x "
1948 			  "ast_index_not_found: %x "
1949 			  "ast_index_timeout: %x ",
1950 			  mpdu_info->rx_reo_queue_desc_addr_39_32,
1951 			  mpdu_info->receive_queue_number,
1952 			  mpdu_info->pre_delim_err_warning,
1953 			  mpdu_info->first_delim_err,
1954 			  mpdu_info->key_id_octet,
1955 			  mpdu_info->new_peer_entry,
1956 			  mpdu_info->decrypt_needed,
1957 			  mpdu_info->decap_type,
1958 			  mpdu_info->rx_insert_vlan_c_tag_padding,
1959 			  mpdu_info->rx_insert_vlan_s_tag_padding,
1960 			  mpdu_info->strip_vlan_c_tag_decap,
1961 			  mpdu_info->strip_vlan_s_tag_decap,
1962 			  mpdu_info->pre_delim_count,
1963 			  mpdu_info->ampdu_flag,
1964 			  mpdu_info->bar_frame,
1965 			  mpdu_info->mpdu_length,
1966 			  mpdu_info->first_mpdu,
1967 			  mpdu_info->mcast_bcast,
1968 			  mpdu_info->ast_index_not_found,
1969 			  mpdu_info->ast_index_timeout);
1970 
1971 	hal_verbose_debug(
1972 			  "rx_mpdu_start tlv (4/5) - "
1973 			  "power_mgmt: %x "
1974 			  "non_qos: %x "
1975 			  "null_data: %x "
1976 			  "mgmt_type: %x "
1977 			  "ctrl_type: %x "
1978 			  "more_data: %x "
1979 			  "eosp: %x "
1980 			  "fragment_flag: %x "
1981 			  "order: %x "
1982 			  "u_apsd_trigger: %x "
1983 			  "encrypt_required: %x "
1984 			  "directed: %x "
1985 			  "mpdu_frame_control_field: %x "
1986 			  "mpdu_duration_field: %x "
1987 			  "mac_addr_ad1_31_0: %x "
1988 			  "mac_addr_ad1_47_32: %x "
1989 			  "mac_addr_ad2_15_0: %x "
1990 			  "mac_addr_ad2_47_16: %x "
1991 			  "mac_addr_ad3_31_0: %x "
1992 			  "mac_addr_ad3_47_32: %x ",
1993 			  mpdu_info->power_mgmt,
1994 			  mpdu_info->non_qos,
1995 			  mpdu_info->null_data,
1996 			  mpdu_info->mgmt_type,
1997 			  mpdu_info->ctrl_type,
1998 			  mpdu_info->more_data,
1999 			  mpdu_info->eosp,
2000 			  mpdu_info->fragment_flag,
2001 			  mpdu_info->order,
2002 			  mpdu_info->u_apsd_trigger,
2003 			  mpdu_info->encrypt_required,
2004 			  mpdu_info->directed,
2005 			  mpdu_info->mpdu_frame_control_field,
2006 			  mpdu_info->mpdu_duration_field,
2007 			  mpdu_info->mac_addr_ad1_31_0,
2008 			  mpdu_info->mac_addr_ad1_47_32,
2009 			  mpdu_info->mac_addr_ad2_15_0,
2010 			  mpdu_info->mac_addr_ad2_47_16,
2011 			  mpdu_info->mac_addr_ad3_31_0,
2012 			  mpdu_info->mac_addr_ad3_47_32);
2013 
2014 	hal_verbose_debug(
2015 			  "rx_mpdu_start tlv (5/5) - "
2016 			  "mpdu_sequence_control_field: %x "
2017 			  "mac_addr_ad4_31_0: %x "
2018 			  "mac_addr_ad4_47_32: %x "
2019 			  "mpdu_qos_control_field: %x "
2020 			  "mpdu_ht_control_field: %x ",
2021 			  mpdu_info->mpdu_sequence_control_field,
2022 			  mpdu_info->mac_addr_ad4_31_0,
2023 			  mpdu_info->mac_addr_ad4_47_32,
2024 			  mpdu_info->mpdu_qos_control_field,
2025 			  mpdu_info->mpdu_ht_control_field);
2026 }
2027 
2028 static void
hal_tx_set_pcp_tid_map_generic_rh(struct hal_soc * soc,uint8_t * map)2029 hal_tx_set_pcp_tid_map_generic_rh(struct hal_soc *soc, uint8_t *map)
2030 {
2031 }
2032 
2033 static void
hal_tx_update_pcp_tid_generic_rh(struct hal_soc * soc,uint8_t pcp,uint8_t tid)2034 hal_tx_update_pcp_tid_generic_rh(struct hal_soc *soc,
2035 				 uint8_t pcp, uint8_t tid)
2036 {
2037 }
2038 
2039 static void
hal_tx_update_tidmap_prty_generic_rh(struct hal_soc * soc,uint8_t value)2040 hal_tx_update_tidmap_prty_generic_rh(struct hal_soc *soc, uint8_t value)
2041 {
2042 }
2043 
2044 /**
2045  * hal_rx_msdu_packet_metadata_get_generic_rh(): API to get the
2046  * msdu information from rx_msdu_end TLV
2047  *
2048  * @buf: pointer to the start of RX PKT TLV headers
2049  * @pkt_msdu_metadata: pointer to the msdu metadata
2050  */
2051 static void
hal_rx_msdu_packet_metadata_get_generic_rh(uint8_t * buf,void * pkt_msdu_metadata)2052 hal_rx_msdu_packet_metadata_get_generic_rh(uint8_t *buf,
2053 					   void *pkt_msdu_metadata)
2054 {
2055 	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
2056 	struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
2057 	struct hal_rx_msdu_metadata *msdu_metadata =
2058 		(struct hal_rx_msdu_metadata *)pkt_msdu_metadata;
2059 
2060 	msdu_metadata->l3_hdr_pad =
2061 		HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
2062 	msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
2063 	msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
2064 	msdu_metadata->sa_sw_peer_id =
2065 		HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
2066 }
2067 
2068 /**
2069  * hal_rx_msdu_end_offset_get_generic(): API to get the
2070  * msdu_end structure offset rx_pkt_tlv structure
2071  *
2072  * NOTE: API returns offset of msdu_end TLV from structure
2073  * rx_pkt_tlvs
2074  */
hal_rx_msdu_end_offset_get_generic(void)2075 static uint32_t hal_rx_msdu_end_offset_get_generic(void)
2076 {
2077 	return RX_PKT_TLV_OFFSET(msdu_end_tlv);
2078 }
2079 
2080 /**
2081  * hal_rx_attn_offset_get_generic(): API to get the
2082  * msdu_end structure offset rx_pkt_tlv structure
2083  *
2084  * NOTE: API returns offset of attn TLV from structure
2085  * rx_pkt_tlvs
2086  */
hal_rx_attn_offset_get_generic(void)2087 static uint32_t hal_rx_attn_offset_get_generic(void)
2088 {
2089 	return RX_PKT_TLV_OFFSET(attn_tlv);
2090 }
2091 
2092 /**
2093  * hal_rx_msdu_start_offset_get_generic(): API to get the
2094  * msdu_start structure offset rx_pkt_tlv structure
2095  *
2096  * NOTE: API returns offset of attn TLV from structure
2097  * rx_pkt_tlvs
2098  */
hal_rx_msdu_start_offset_get_generic(void)2099 static uint32_t hal_rx_msdu_start_offset_get_generic(void)
2100 {
2101 	return RX_PKT_TLV_OFFSET(msdu_start_tlv);
2102 }
2103 
2104 /**
2105  * hal_rx_mpdu_start_offset_get_generic(): API to get the
2106  * mpdu_start structure offset rx_pkt_tlv structure
2107  *
2108  * NOTE: API returns offset of attn TLV from structure
2109  * rx_pkt_tlvs
2110  */
hal_rx_mpdu_start_offset_get_generic(void)2111 static uint32_t hal_rx_mpdu_start_offset_get_generic(void)
2112 {
2113 	return RX_PKT_TLV_OFFSET(mpdu_start_tlv);
2114 }
2115 
2116 /**
2117  * hal_rx_mpdu_end_offset_get_generic(): API to get the
2118  * mpdu_end structure offset rx_pkt_tlv structure
2119  *
2120  * NOTE: API returns offset of attn TLV from structure
2121  * rx_pkt_tlvs
2122  */
hal_rx_mpdu_end_offset_get_generic(void)2123 static uint32_t hal_rx_mpdu_end_offset_get_generic(void)
2124 {
2125 	return RX_PKT_TLV_OFFSET(mpdu_end_tlv);
2126 }
2127 
2128 #ifndef NO_RX_PKT_HDR_TLV
hal_rx_pkt_tlv_offset_get_generic(void)2129 static uint32_t hal_rx_pkt_tlv_offset_get_generic(void)
2130 {
2131 	return RX_PKT_TLV_OFFSET(pkt_hdr_tlv);
2132 }
2133 #endif
2134 
2135 #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET
2136 /**
2137  * hal_tx_desc_set_search_type_generic_rh - Set the search type value
2138  * @desc: Handle to Tx Descriptor
2139  * @search_type: search type
2140  *		     0 – Normal search
2141  *		     1 – Index based address search
2142  *		     2 – Index based flow search
2143  *
2144  * Return: void
2145  */
2146 static inline
hal_tx_desc_set_search_type_generic_rh(void * desc,uint8_t search_type)2147 void hal_tx_desc_set_search_type_generic_rh(void *desc, uint8_t search_type)
2148 {
2149 	HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |=
2150 		HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type);
2151 }
2152 #else
2153 static inline
hal_tx_desc_set_search_type_generic_rh(void * desc,uint8_t search_type)2154 void hal_tx_desc_set_search_type_generic_rh(void *desc, uint8_t search_type)
2155 {
2156 }
2157 
2158 #endif
2159 
2160 #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET
2161 /**
2162  * hal_tx_desc_set_search_index_generic_rh - Set the search index value
2163  * @desc: Handle to Tx Descriptor
2164  * @search_index: The index that will be used for index based address or
2165  *                flow search. The field is valid when 'search_type' is
2166  *                1 0r 2
2167  *
2168  * Return: void
2169  */
2170 static inline
hal_tx_desc_set_search_index_generic_rh(void * desc,uint32_t search_index)2171 void hal_tx_desc_set_search_index_generic_rh(void *desc, uint32_t search_index)
2172 {
2173 	HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |=
2174 		HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index);
2175 }
2176 #else
2177 static inline
hal_tx_desc_set_search_index_generic_rh(void * desc,uint32_t search_index)2178 void hal_tx_desc_set_search_index_generic_rh(void *desc, uint32_t search_index)
2179 {
2180 }
2181 #endif
2182 
2183 #ifdef TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET
2184 /**
2185  * hal_tx_desc_set_cache_set_num_generic_rh - Set the cache-set-num value
2186  * @desc: Handle to Tx Descriptor
2187  * @cache_num: Cache set number that should be used to cache the index
2188  *                based search results, for address and flow search.
2189  *                This value should be equal to LSB four bits of the hash value
2190  *                of match data, in case of search index points to an entry
2191  *                which may be used in content based search also. The value can
2192  *                be anything when the entry pointed by search index will not be
2193  *                used for content based search.
2194  *
2195  * Return: void
2196  */
2197 static inline
hal_tx_desc_set_cache_set_num_generic_rh(void * desc,uint8_t cache_num)2198 void hal_tx_desc_set_cache_set_num_generic_rh(void *desc, uint8_t cache_num)
2199 {
2200 	HAL_SET_FLD(desc, TCL_DATA_CMD_5, CACHE_SET_NUM) |=
2201 		HAL_TX_SM(TCL_DATA_CMD_5, CACHE_SET_NUM, cache_num);
2202 }
2203 #else
2204 static inline
hal_tx_desc_set_cache_set_num_generic_rh(void * desc,uint8_t cache_num)2205 void hal_tx_desc_set_cache_set_num_generic_rh(void *desc, uint8_t cache_num)
2206 {
2207 }
2208 #endif
2209 
2210 #ifdef WLAN_SUPPORT_RX_FISA
2211 /**
2212  * hal_rx_flow_get_tuple_info_rh() - Setup a flow search entry in HW FST
2213  * @rx_fst: Pointer to the Rx Flow Search Table
2214  * @hal_hash: HAL 5 tuple hash
2215  * @flow_tuple_info: 5-tuple info of the flow returned to the caller
2216  *
2217  * Return: Success/Failure
2218  */
2219 static void *
hal_rx_flow_get_tuple_info_rh(uint8_t * rx_fst,uint32_t hal_hash,uint8_t * flow_tuple_info)2220 hal_rx_flow_get_tuple_info_rh(uint8_t *rx_fst, uint32_t hal_hash,
2221 			      uint8_t *flow_tuple_info)
2222 {
2223 	struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
2224 	void *hal_fse = NULL;
2225 	struct hal_flow_tuple_info *tuple_info
2226 		= (struct hal_flow_tuple_info *)flow_tuple_info;
2227 
2228 	hal_fse = (uint8_t *)fst->base_vaddr +
2229 		(hal_hash * HAL_RX_FST_ENTRY_SIZE);
2230 
2231 	if (!hal_fse || !tuple_info)
2232 		return NULL;
2233 
2234 	if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY_9, VALID))
2235 		return NULL;
2236 
2237 	tuple_info->src_ip_127_96 =
2238 				qdf_ntohl(HAL_GET_FLD(hal_fse,
2239 						      RX_FLOW_SEARCH_ENTRY_0,
2240 						      SRC_IP_127_96));
2241 	tuple_info->src_ip_95_64 =
2242 				qdf_ntohl(HAL_GET_FLD(hal_fse,
2243 						      RX_FLOW_SEARCH_ENTRY_1,
2244 						      SRC_IP_95_64));
2245 	tuple_info->src_ip_63_32 =
2246 				qdf_ntohl(HAL_GET_FLD(hal_fse,
2247 						      RX_FLOW_SEARCH_ENTRY_2,
2248 						      SRC_IP_63_32));
2249 	tuple_info->src_ip_31_0 =
2250 				qdf_ntohl(HAL_GET_FLD(hal_fse,
2251 						      RX_FLOW_SEARCH_ENTRY_3,
2252 						      SRC_IP_31_0));
2253 	tuple_info->dest_ip_127_96 =
2254 				qdf_ntohl(HAL_GET_FLD(hal_fse,
2255 						      RX_FLOW_SEARCH_ENTRY_4,
2256 						      DEST_IP_127_96));
2257 	tuple_info->dest_ip_95_64 =
2258 				qdf_ntohl(HAL_GET_FLD(hal_fse,
2259 						      RX_FLOW_SEARCH_ENTRY_5,
2260 						      DEST_IP_95_64));
2261 	tuple_info->dest_ip_63_32 =
2262 				qdf_ntohl(HAL_GET_FLD(hal_fse,
2263 						      RX_FLOW_SEARCH_ENTRY_6,
2264 						      DEST_IP_63_32));
2265 	tuple_info->dest_ip_31_0 =
2266 			qdf_ntohl(HAL_GET_FLD(hal_fse,
2267 					      RX_FLOW_SEARCH_ENTRY_7,
2268 					      DEST_IP_31_0));
2269 	tuple_info->dest_port = HAL_GET_FLD(hal_fse,
2270 					    RX_FLOW_SEARCH_ENTRY_8,
2271 					    DEST_PORT);
2272 	tuple_info->src_port = HAL_GET_FLD(hal_fse,
2273 					   RX_FLOW_SEARCH_ENTRY_8,
2274 					   SRC_PORT);
2275 	tuple_info->l4_protocol = HAL_GET_FLD(hal_fse,
2276 					      RX_FLOW_SEARCH_ENTRY_9,
2277 					      L4_PROTOCOL);
2278 
2279 	return hal_fse;
2280 }
2281 
2282 /**
2283  * hal_rx_flow_delete_entry_rh() - Setup a flow search entry in HW FST
2284  * @rx_fst: Pointer to the Rx Flow Search Table
2285  * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST
2286  *
2287  * Return: Success/Failure
2288  */
2289 static QDF_STATUS
hal_rx_flow_delete_entry_rh(uint8_t * rx_fst,void * hal_rx_fse)2290 hal_rx_flow_delete_entry_rh(uint8_t *rx_fst, void *hal_rx_fse)
2291 {
2292 	uint8_t *fse = (uint8_t *)hal_rx_fse;
2293 
2294 	if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID))
2295 		return QDF_STATUS_E_NOENT;
2296 
2297 	HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
2298 
2299 	return QDF_STATUS_SUCCESS;
2300 }
2301 
2302 /**
2303  * hal_rx_fst_get_fse_size_rh() - Retrieve the size of each entry
2304  *
2305  * Return: size of each entry/flow in Rx FST
2306  */
2307 static inline uint32_t
hal_rx_fst_get_fse_size_rh(void)2308 hal_rx_fst_get_fse_size_rh(void)
2309 {
2310 	return HAL_RX_FST_ENTRY_SIZE;
2311 }
2312 #else
2313 static inline void *
hal_rx_flow_get_tuple_info_rh(uint8_t * rx_fst,uint32_t hal_hash,uint8_t * flow_tuple_info)2314 hal_rx_flow_get_tuple_info_rh(uint8_t *rx_fst, uint32_t hal_hash,
2315 			      uint8_t *flow_tuple_info)
2316 {
2317 	return NULL;
2318 }
2319 
2320 static inline QDF_STATUS
hal_rx_flow_delete_entry_rh(uint8_t * rx_fst,void * hal_rx_fse)2321 hal_rx_flow_delete_entry_rh(uint8_t *rx_fst, void *hal_rx_fse)
2322 {
2323 	return QDF_STATUS_SUCCESS;
2324 }
2325 
2326 static inline uint32_t
hal_rx_fst_get_fse_size_rh(void)2327 hal_rx_fst_get_fse_size_rh(void)
2328 {
2329 	return 0;
2330 }
2331 #endif /* WLAN_SUPPORT_RX_FISA */
2332 
2333 /**
2334  * hal_rx_get_frame_ctrl_field_rh(): Function to retrieve frame control field
2335  *
2336  * @buf: Network buffer
2337  *
2338  * Returns: rx more fragment bit
2339  */
hal_rx_get_frame_ctrl_field_rh(uint8_t * buf)2340 static uint16_t hal_rx_get_frame_ctrl_field_rh(uint8_t *buf)
2341 {
2342 	struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
2343 	struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
2344 	uint16_t frame_ctrl = 0;
2345 
2346 	frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info);
2347 
2348 	return frame_ctrl;
2349 }
2350 
2351 #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
2352 static inline void
hal_tx_comp_get_buffer_timestamp_rh(void * desc,struct hal_tx_completion_status * ts)2353 hal_tx_comp_get_buffer_timestamp_rh(void *desc,
2354 				    struct hal_tx_completion_status *ts)
2355 {
2356 	uint32_t *msg_word = (struct uint32_t *)desc;
2357 
2358 	ts->buffer_timestamp =
2359 		HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_GET(*(msg_word + 4));
2360 }
2361 #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY || WLAN_CONFIG_TX_DELAY */
2362 static inline void
hal_tx_comp_get_buffer_timestamp_rh(void * desc,struct hal_tx_completion_status * ts)2363 hal_tx_comp_get_buffer_timestamp_rh(void *desc,
2364 				    struct hal_tx_completion_status *ts)
2365 {
2366 }
2367 #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY || WLAN_CONFIG_TX_DELAY */
2368 
hal_tx_get_compl_status_rh(uint8_t tx_status)2369 static inline uint8_t hal_tx_get_compl_status_rh(uint8_t tx_status)
2370 {
2371 	switch (tx_status) {
2372 	case HTT_TX_MSDU_RELEASE_REASON_FRAME_ACKED:
2373 		return HAL_TX_TQM_RR_FRAME_ACKED;
2374 	case HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_TX:
2375 		return HAL_TX_TQM_RR_REM_CMD_TX;
2376 	case HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_NOTX:
2377 		return HAL_TX_TQM_RR_REM_CMD_NOTX;
2378 	case HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_AGED:
2379 		return HAL_TX_TQM_RR_REM_CMD_AGED;
2380 	case HTT_TX_MSDU_RELEASE_FW_REASON1:
2381 		return HAL_TX_TQM_RR_FW_REASON1;
2382 	case HTT_TX_MSDU_RELEASE_FW_REASON2:
2383 		return HAL_TX_TQM_RR_FW_REASON2;
2384 	case HTT_TX_MSDU_RELEASE_FW_REASON3:
2385 		return HAL_TX_TQM_RR_FW_REASON3;
2386 	case HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_DISABLEQ:
2387 		return HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE;
2388 	default:
2389 		return HAL_TX_TQM_RR_REM_CMD_REM;
2390 	}
2391 }
2392 
2393 static inline void
hal_tx_comp_get_status_generic_rh(void * desc,void * ts1,struct hal_soc * hal)2394 hal_tx_comp_get_status_generic_rh(void *desc, void *ts1, struct hal_soc *hal)
2395 {
2396 	uint8_t tx_status;
2397 	struct hal_tx_completion_status *ts =
2398 		(struct hal_tx_completion_status *)ts1;
2399 	uint32_t *msg_word = (uint32_t *)desc;
2400 
2401 	if (HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_GET(*(msg_word + 1)) ==
2402 	    HTT_TX_MSDU_RELEASE_SOURCE_FW)
2403 		ts->release_src = HAL_TX_COMP_RELEASE_SOURCE_FW;
2404 	else
2405 		ts->release_src = HAL_TX_COMP_RELEASE_SOURCE_TQM;
2406 
2407 	if (HTT_TX_MSDU_INFO_VALID_GET(*(msg_word + 2))) {
2408 		ts->peer_id = HTT_TX_MSDU_INFO_SW_PEER_ID_GET(*(msg_word + 2));
2409 		ts->tid = HTT_TX_MSDU_INFO_TID_GET(*(msg_word + 2));
2410 	} else {
2411 		ts->peer_id = HTT_INVALID_PEER;
2412 		ts->tid = HTT_INVALID_TID;
2413 	}
2414 	ts->transmit_cnt = HTT_TX_MSDU_INFO_TRANSMIT_CNT_GET(*(msg_word + 2));
2415 
2416 	tx_status = HTT_TX_MSDU_INFO_RELEASE_REASON_GET(*(msg_word + 3));
2417 	ts->status = hal_tx_get_compl_status_rh(tx_status);
2418 
2419 	ts->ppdu_id = HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_GET(*(msg_word + 3));
2420 
2421 	ts->ack_frame_rssi =
2422 		HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_GET(*(msg_word + 4));
2423 	ts->first_msdu = HTT_TX_MSDU_INFO_FIRST_MSDU_GET(*(msg_word + 4));
2424 	ts->last_msdu = HTT_TX_MSDU_INFO_LAST_MSDU_GET(*(msg_word + 4));
2425 	ts->msdu_part_of_amsdu =
2426 		HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_GET(*(msg_word + 4));
2427 
2428 	ts->valid = HTT_TX_RATE_STATS_INFO_VALID_GET(*(msg_word + 5));
2429 
2430 	if (ts->valid) {
2431 		ts->bw = HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_GET(*(msg_word + 5));
2432 		ts->pkt_type =
2433 			HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_GET(*(msg_word + 5));
2434 		ts->stbc = HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_GET(*(msg_word + 5));
2435 		ts->ldpc = HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_GET(*(msg_word + 5));
2436 		ts->sgi = HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_GET(*(msg_word + 5));
2437 		ts->mcs = HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_GET(*(msg_word + 5));
2438 		ts->ofdma =
2439 			HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_GET(*(msg_word + 5));
2440 		ts->tones_in_ru = HTT_TX_RATE_STATS_INFO_TONES_IN_RU_GET(*(msg_word + 5));
2441 	}
2442 
2443 	ts->tsf = HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_GET(*(msg_word + 6));
2444 	hal_tx_comp_get_buffer_timestamp_rh(desc, ts);
2445 }
2446 #endif /* _HAL_RH_GENERIC_API_H_ */
2447