1 /*
2 * Copyright (c) 2021 The Linux Foundation. All rights reserved.
3 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for
6 * any purpose with or without fee is hereby granted, provided that the
7 * above copyright notice and this permission notice appear in all
8 * copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17 * PERFORMANCE OF THIS SOFTWARE.
18 */
19 #include "qdf_types.h"
20 #include "qdf_util.h"
21 #include "qdf_mem.h"
22 #include "qdf_nbuf.h"
23 #include "qdf_module.h"
24
25 #include "target_type.h"
26 #include "wcss_version.h"
27
28 #include "hal_be_hw_headers.h"
29 #include "hal_internal.h"
30 #include "hal_api.h"
31 #include "hal_flow.h"
32 #include "rx_flow_search_entry.h"
33 #include "hal_rx_flow_info.h"
34 #include "hal_be_api.h"
35 #include "tcl_entrance_from_ppe_ring.h"
36 #include "sw_monitor_ring.h"
37 #include "wcss_seq_hwioreg_umac.h"
38 #include "wfss_ce_reg_seq_hwioreg.h"
39 #include <uniform_reo_status_header.h>
40 #include <wbm_release_ring_tx.h>
41 #include <phyrx_location.h>
42 #if defined(WLAN_PKT_CAPTURE_TX_2_0) || \
43 defined(WLAN_PKT_CAPTURE_RX_2_0)
44 #include <mon_ingress_ring.h>
45 #include <mon_destination_ring.h>
46 #endif
47 #include "rx_reo_queue_1k.h"
48
49 #include <hal_be_rx.h>
50
51 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
52 RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET
53 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
54 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
55 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
56 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
57 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
58 RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
59 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
60 REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
61 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \
62 STATUS_HEADER_REO_STATUS_NUMBER
63 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
64 STATUS_HEADER_TIMESTAMP
65 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
66 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
67 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
68 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
69 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
70 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET
71 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
72 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET
73 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
74 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET
75 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
76 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB
77 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
78 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK
79 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
80 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB
81 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
82 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK
83 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
84 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB
85 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
86 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK
87 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
88 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB
89 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
90 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK
91 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
92 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB
93 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
94 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK
95 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
96 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK
97 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
98 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET
99 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
100 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB
101
102 #if defined(WLAN_PKT_CAPTURE_TX_2_0) || defined(WLAN_PKT_CAPTURE_RX_2_0)
103 #include "hal_be_api_mon.h"
104 #endif
105
106 #ifdef CONFIG_WIFI_EMULATION_WIFI_3_0
107 #define CMEM_REG_BASE 0x0010e000
108
109 #define CMEM_WINDOW_ADDRESS_9224 \
110 ((CMEM_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
111 #endif
112
113 #define CE_WINDOW_ADDRESS_9224 \
114 ((CE_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
115
116 #define UMAC_WINDOW_ADDRESS_9224 \
117 ((UMAC_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
118
119 #ifdef CONFIG_WIFI_EMULATION_WIFI_3_0
120 #define WINDOW_CONFIGURATION_VALUE_9224 \
121 ((CE_WINDOW_ADDRESS_9224 << 6) |\
122 (UMAC_WINDOW_ADDRESS_9224 << 12) | \
123 CMEM_WINDOW_ADDRESS_9224 | \
124 WINDOW_ENABLE_BIT)
125 #else
126 #define WINDOW_CONFIGURATION_VALUE_9224 \
127 ((CE_WINDOW_ADDRESS_9224 << 6) |\
128 (UMAC_WINDOW_ADDRESS_9224 << 12) | \
129 WINDOW_ENABLE_BIT)
130 #endif
131
132 /* For Berryllium sw2rxdma ring size increased to 20 bits */
133 #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF
134
135 #include "hal_9224_rx.h"
136 #include "hal_9224_tx.h"
137 #include "hal_be_rx_tlv.h"
138 #include <hal_be_generic_api.h>
139
140 enum hal_all_sigb_pkt_type {
141 HAL_SIGB_RX_PKT_TYPE_11A = 0,
142 HAL_SIGB_RX_PKT_TYPE_11B,
143 HAL_SIGB_RX_PKT_TYPE_HT_MM,
144 HAL_SIGB_RX_PKT_TYPE_11AC,
145 HAL_SIGB_RX_PKT_TYPE_11AX,
146 HAL_SIGB_RX_PKT_TYPE_HT_GF,
147 HAL_SIGB_RX_PKT_TYPE_11BE,
148 };
149
150 #define PMM_REG_BASE_QCN9224 0xB500F8
151
152 /**
153 * hal_read_pmm_scratch_reg() - API to read PMM Scratch register
154 * @soc: HAL soc
155 * @base_addr: Base PMM register
156 * @reg_enum: Enum of the scratch register
157 *
158 * Return: uint32_t
159 */
160 static inline
hal_read_pmm_scratch_reg(struct hal_soc * soc,uint32_t base_addr,enum hal_scratch_reg_enum reg_enum)161 uint32_t hal_read_pmm_scratch_reg(struct hal_soc *soc,
162 uint32_t base_addr,
163 enum hal_scratch_reg_enum reg_enum)
164 {
165 uint32_t val = 0;
166
167 pld_reg_read(soc->qdf_dev->dev, base_addr + (reg_enum * 4), &val, NULL);
168 return val;
169 }
170
171 /**
172 * hal_get_tsf2_scratch_reg_qcn9224() - API to read tsf2 scratch register
173 * @hal_soc_hdl: HAL soc context
174 * @mac_id: mac id
175 * @value: Pointer to update tsf2 value
176 *
177 * Return: void
178 */
hal_get_tsf2_scratch_reg_qcn9224(hal_soc_handle_t hal_soc_hdl,uint8_t mac_id,uint64_t * value)179 static void hal_get_tsf2_scratch_reg_qcn9224(hal_soc_handle_t hal_soc_hdl,
180 uint8_t mac_id, uint64_t *value)
181 {
182 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
183 uint32_t offset_lo, offset_hi;
184 enum hal_scratch_reg_enum enum_lo, enum_hi;
185
186 hal_get_tsf_enum(DEFAULT_TSF_ID, mac_id, &enum_lo, &enum_hi);
187
188 offset_lo = hal_read_pmm_scratch_reg(soc,
189 PMM_REG_BASE_QCN9224,
190 enum_lo);
191
192 offset_hi = hal_read_pmm_scratch_reg(soc,
193 PMM_REG_BASE_QCN9224,
194 enum_hi);
195
196 *value = ((uint64_t)(offset_hi) << 32 | offset_lo);
197 }
198
199 /**
200 * hal_get_tqm_scratch_reg_qcn9224() - API to read tqm scratch register
201 * @hal_soc_hdl: HAL soc context
202 * @value: Pointer to update tqm value
203 *
204 * Return: void
205 */
hal_get_tqm_scratch_reg_qcn9224(hal_soc_handle_t hal_soc_hdl,uint64_t * value)206 static void hal_get_tqm_scratch_reg_qcn9224(hal_soc_handle_t hal_soc_hdl,
207 uint64_t *value)
208 {
209 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
210 uint32_t offset_lo, offset_hi;
211
212 offset_lo = hal_read_pmm_scratch_reg(soc,
213 PMM_REG_BASE_QCN9224,
214 PMM_TQM_CLOCK_OFFSET_LO_US);
215
216 offset_hi = hal_read_pmm_scratch_reg(soc,
217 PMM_REG_BASE_QCN9224,
218 PMM_TQM_CLOCK_OFFSET_HI_US);
219
220 *value = ((uint64_t)(offset_hi) << 32 | offset_lo);
221 }
222
223 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
224 #define HAL_PPE_VP_ENTRIES_MAX 32
225 #define HAL_PPE_VP_SEARCH_IDX_REG_MAX 8
226
227 /**
228 * hal_get_link_desc_size_9224() - API to get the link desc size
229 *
230 * Return: uint32_t
231 */
hal_get_link_desc_size_9224(void)232 static uint32_t hal_get_link_desc_size_9224(void)
233 {
234 return LINK_DESC_SIZE;
235 }
236
237 /**
238 * hal_rx_get_tlv_9224() - API to get the tlv
239 * @rx_tlv: TLV data extracted from the rx packet
240 *
241 * Return: uint8_t
242 */
hal_rx_get_tlv_9224(void * rx_tlv)243 static uint8_t hal_rx_get_tlv_9224(void *rx_tlv)
244 {
245 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH);
246 }
247
248 /**
249 * hal_rx_wbm_err_msdu_continuation_get_9224() - API to check if WBM msdu
250 * continuation bit is set
251 * @wbm_desc: wbm release ring descriptor
252 *
253 * Return: true if msdu continuation bit is set.
254 */
255 static inline
hal_rx_wbm_err_msdu_continuation_get_9224(void * wbm_desc)256 uint8_t hal_rx_wbm_err_msdu_continuation_get_9224(void *wbm_desc)
257 {
258 uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) +
259 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET);
260
261 return (comp_desc &
262 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK) >>
263 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB;
264 }
265
266 #if (defined(WLAN_SA_API_ENABLE)) && (defined(QCA_WIFI_QCA9574))
267 #define HAL_RX_EVM_DEMF_SEGMENT_SIZE 128
268 #define HAL_RX_EVM_DEMF_MAX_STREAMS 2
269 #define HAL_RX_SU_EVM_MEMBER_LEN 4
270 static inline void
hal_rx_update_su_evm_info(void * rx_tlv,void * ppdu_info_hdl)271 hal_rx_update_su_evm_info(void *rx_tlv,
272 void *ppdu_info_hdl)
273 {
274 uint32_t nss_count, pilot_count;
275 uint16_t istream = 0, ipilot = 0;
276 uint8_t pilot_shift = 0;
277 uint8_t *pilot_ptr = NULL;
278 uint16_t segment = 0;
279
280 struct hal_rx_ppdu_info *ppdu_info =
281 (struct hal_rx_ppdu_info *)ppdu_info_hdl;
282 nss_count = ppdu_info->evm_info.nss_count;
283 pilot_count = ppdu_info->evm_info.pilot_count;
284
285 if (nss_count * pilot_count > HAL_RX_MAX_SU_EVM_COUNT)
286 return;
287
288 /* move rx_tlv by 4 to skip no_of_data_sym, nss_cnt and pilot_cnt */
289 rx_tlv = (uint8_t *)rx_tlv + HAL_RX_SU_EVM_MEMBER_LEN;
290
291 /* EVM values = number_of_streams * number_of_pilots
292 * each EVM value is 8 bits, So, each variable acc_linear_evm_x_y
293 * is (32 bits) will contain 4 EVM values.
294 * For ex:
295 * acc_linear_evm_0_0 : <Pilot0, stream0>, <Pilot0, stream1>,
296 * <Pilot1, stream0>, <Pilot1, stream1>
297 * .....
298 * acc_linear_evm_1_15 : <Pilot62, stream0>, <Pilot62, stream1>,
299 * <Pilot63, stream0>, <Pilot63, stream1> ...
300 */
301
302 for (istream = 0; istream < nss_count; istream++) {
303 segment = HAL_RX_EVM_DEMF_SEGMENT_SIZE * (istream / HAL_RX_EVM_DEMF_MAX_STREAMS);
304 pilot_ptr = (uint8_t *)rx_tlv + segment;
305 for (ipilot = 0; ipilot < pilot_count; ipilot++) {
306 /* In case there is one stream in Demf segment,
307 * pilots are one after the other
308 */
309 if (nss_count == 1 ||
310 ((nss_count == HAL_RX_EVM_DEMF_MAX_STREAMS + 1) &&
311 (istream == HAL_RX_EVM_DEMF_MAX_STREAMS)))
312 pilot_shift = ipilot;
313 /* In case there are more than one stream in DemF
314 * segment, pilot 0 of all streams come one after the
315 * other before pilot 1
316 */
317 else
318 pilot_shift = (ipilot * HAL_RX_EVM_DEMF_MAX_STREAMS)
319 + (istream % HAL_RX_EVM_DEMF_MAX_STREAMS);
320
321 ppdu_info->evm_info.pilot_evm[segment + pilot_shift] =
322 *(pilot_ptr + pilot_shift);
323 }
324 }
325 }
326
327 /**
328 * hal_rx_proc_phyrx_other_receive_info_tlv_9224() - API to get tlv info
329 * @rx_tlv_hdr: RX TLV header
330 * @ppdu_info_hdl: Handle to PPDU info to update
331 *
332 * Return: None
333 */
334 static inline
hal_rx_proc_phyrx_other_receive_info_tlv_9224(void * rx_tlv_hdr,void * ppdu_info_hdl)335 void hal_rx_proc_phyrx_other_receive_info_tlv_9224(void *rx_tlv_hdr,
336 void *ppdu_info_hdl)
337 {
338 uint32_t tlv_tag, tlv_len, pkt_type;
339 void *rx_tlv;
340 uint32_t ru_details_channel_0;
341 struct hal_rx_ppdu_info *ppdu_info =
342 (struct hal_rx_ppdu_info *)ppdu_info_hdl;
343
344 hal_rx_proc_phyrx_all_sigb_tlv_9224(rx_tlv_hdr, ppdu_info_hdl);
345
346 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
347 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
348
349 if (!tlv_len)
350 return;
351
352 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
353 rx_tlv = (uint8_t *)rx_tlv + HAL_RX_TLV64_HDR_SIZE;
354
355 pkt_type = HAL_RX_GET_64(rx_tlv,
356 PHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS,
357 PKT_TYPE);
358
359 switch (tlv_tag) {
360 case WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E:
361 if (pkt_type ==
362 HAL_RX_PKT_TYPE_11AX) {
363 ru_details_channel_0 =
364 HAL_RX_GET(rx_tlv,
365 PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS,
366 RU_DETAILS_CHANNEL_0);
367
368 qdf_mem_copy(ppdu_info->rx_status.he_RU,
369 &ru_details_channel_0,
370 sizeof(ppdu_info->rx_status.he_RU));
371
372 ppdu_info->rx_status.he_flags1 |=
373 QDF_MON_STATUS_CHANNEL_1_RU_KNOWN;
374 if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_40) {
375 ppdu_info->rx_status.he_flags1 |=
376 QDF_MON_STATUS_CHANNEL_2_RU_KNOWN;
377 }
378 }
379
380 break;
381 default:
382 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
383 "%s unhandled TLV type: %d, TLV len:%d",
384 __func__, tlv_tag, tlv_len);
385 break;
386 }
387 }
388
389 static inline uint32_t
hal_rx_parse_ru_allocation_9224(struct hal_soc * hal_soc,void * tlv,struct hal_rx_ppdu_info * ppdu_info)390 hal_rx_parse_ru_allocation_9224(struct hal_soc *hal_soc, void *tlv,
391 struct hal_rx_ppdu_info *ppdu_info)
392 {
393 uint64_t *ehtsig_tlv = (uint64_t *)tlv;
394 struct hal_eht_sig_ofdma_cmn_eb1 *ofdma_cc1_cmn_eb1;
395 struct hal_eht_sig_ofdma_cmn_eb1 *ofdma_cc2_cmn_eb1;
396 struct hal_eht_sig_ofdma_cmn_eb2 *ofdma_cc1_cmn_eb2;
397 struct hal_eht_sig_ofdma_cmn_eb2 *ofdma_cc2_cmn_eb2;
398 uint8_t num_ru_allocation_known = 0;
399
400 ofdma_cc1_cmn_eb1 = (struct hal_eht_sig_ofdma_cmn_eb1 *)ehtsig_tlv;
401 ofdma_cc2_cmn_eb1 =
402 (struct hal_eht_sig_ofdma_cmn_eb1 *)(ehtsig_tlv + 1);
403 ofdma_cc1_cmn_eb2 =
404 (struct hal_eht_sig_ofdma_cmn_eb2 *)(ehtsig_tlv + 2);
405 ofdma_cc2_cmn_eb2 =
406 (struct hal_eht_sig_ofdma_cmn_eb2 *)(ehtsig_tlv + 3);
407
408 switch (ppdu_info->u_sig_info.bw) {
409 case HAL_EHT_BW_320_2:
410 case HAL_EHT_BW_320_1:
411 num_ru_allocation_known += 8;
412
413 ppdu_info->rx_status.eht_data[4] |=
414 (ofdma_cc1_cmn_eb2->ru_allocation2_3 <<
415 QDF_MON_STATUS_EHT_RU_ALLOC_FIELD1_5_SHIFT);
416 ppdu_info->rx_status.eht_data[4] |= 1 <<
417 QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN1_5_SHIFT;
418
419 ppdu_info->rx_status.eht_data[4] |=
420 (ofdma_cc2_cmn_eb2->ru_allocation2_3 <<
421 QDF_MON_STATUS_EHT_RU_ALLOC_FIELD2_5_SHIFT);
422 ppdu_info->rx_status.eht_data[4] |= 1 <<
423 QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN2_5_SHIFT;
424
425 ppdu_info->rx_status.eht_data[5] |=
426 (ofdma_cc1_cmn_eb2->ru_allocation2_4 <<
427 QDF_MON_STATUS_EHT_RU_ALLOC_FIELD1_6_SHIFT);
428 ppdu_info->rx_status.eht_data[5] |= 1 <<
429 QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN1_6_SHIFT;
430
431 ppdu_info->rx_status.eht_data[5] |=
432 (ofdma_cc2_cmn_eb2->ru_allocation2_4 <<
433 QDF_MON_STATUS_EHT_RU_ALLOC_FIELD2_6_SHIFT);
434 ppdu_info->rx_status.eht_data[5] |= 1 <<
435 QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN2_6_SHIFT;
436
437 ppdu_info->rx_status.eht_data[5] |=
438 (ofdma_cc1_cmn_eb2->ru_allocation2_5 <<
439 QDF_MON_STATUS_EHT_RU_ALLOC_FIELD1_7_SHIFT);
440 ppdu_info->rx_status.eht_data[5] |= 1 <<
441 QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN1_7_SHIFT;
442
443 ppdu_info->rx_status.eht_data[6] |=
444 (ofdma_cc2_cmn_eb2->ru_allocation2_5 <<
445 QDF_MON_STATUS_EHT_RU_ALLOC_FIELD2_7_SHIFT);
446 ppdu_info->rx_status.eht_data[6] |= 1 <<
447 QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN2_7_SHIFT;
448
449 ppdu_info->rx_status.eht_data[6] |=
450 (ofdma_cc1_cmn_eb2->ru_allocation2_6 <<
451 QDF_MON_STATUS_EHT_RU_ALLOC_FIELD1_8_SHIFT);
452 ppdu_info->rx_status.eht_data[6] |= 1 <<
453 QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN1_8_SHIFT;
454
455 ppdu_info->rx_status.eht_data[6] |=
456 (ofdma_cc2_cmn_eb2->ru_allocation2_6 <<
457 QDF_MON_STATUS_EHT_RU_ALLOC_FIELD2_8_SHIFT);
458 num_ru_allocation_known += 4;
459 fallthrough;
460
461 case HAL_EHT_BW_160:
462 ppdu_info->rx_status.eht_data[3] |=
463 (ofdma_cc1_cmn_eb2->ru_allocation2_1 <<
464 QDF_MON_STATUS_EHT_RU_ALLOC_FIELD1_3_SHIFT);
465 ppdu_info->rx_status.eht_data[3] |= 1 <<
466 QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN1_3_SHIFT;
467 ppdu_info->rx_status.eht_data[3] |=
468 (ofdma_cc2_cmn_eb2->ru_allocation2_1 <<
469 QDF_MON_STATUS_EHT_RU_ALLOC_FIELD2_3_SHIFT);
470 ppdu_info->rx_status.eht_data[3] |= 1 <<
471 QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN2_3_SHIFT;
472 ppdu_info->rx_status.eht_data[3] |=
473 (ofdma_cc1_cmn_eb2->ru_allocation2_2 <<
474 QDF_MON_STATUS_EHT_RU_ALLOC_FIELD1_4_SHIFT);
475 ppdu_info->rx_status.eht_data[3] |= 1 <<
476 QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN1_4_SHIFT;
477 ppdu_info->rx_status.eht_data[4] |=
478 (ofdma_cc2_cmn_eb2->ru_allocation2_2 <<
479 QDF_MON_STATUS_EHT_RU_ALLOC_FIELD2_4_SHIFT);
480 ppdu_info->rx_status.eht_data[4] |= 1 <<
481 QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN2_4_SHIFT;
482 ppdu_info->tlv_aggr.rd_idx += 16;
483 fallthrough;
484
485 case HAL_EHT_BW_80:
486 num_ru_allocation_known += 2;
487
488 ppdu_info->rx_status.eht_data[2] |=
489 (ofdma_cc1_cmn_eb1->ru_allocation1_2 <<
490 QDF_MON_STATUS_EHT_RU_ALLOC_FIELD1_2_SHIFT);
491 ppdu_info->rx_status.eht_data[2] |= 1 <<
492 QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN1_2_SHIFT;
493 ppdu_info->rx_status.eht_data[2] |=
494 (ofdma_cc2_cmn_eb1->ru_allocation1_2 <<
495 QDF_MON_STATUS_EHT_RU_ALLOC_FIELD2_2_SHIFT);
496 ppdu_info->rx_status.eht_data[2] |= 1 <<
497 QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN2_2_SHIFT;
498 fallthrough;
499
500 case HAL_EHT_BW_40:
501 num_ru_allocation_known += 1;
502
503 ppdu_info->rx_status.eht_data[2] |=
504 (ofdma_cc2_cmn_eb1->ru_allocation1_1 <<
505 QDF_MON_STATUS_EHT_RU_ALLOC_FIELD2_1_SHIFT);
506 ppdu_info->rx_status.eht_data[2] |= 1 <<
507 QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN2_1_SHIFT;
508 ppdu_info->tlv_aggr.rd_idx += 8;
509 fallthrough;
510
511 case HAL_EHT_BW_20:
512 num_ru_allocation_known += 1;
513
514 ppdu_info->rx_status.eht_data[1] |=
515 (ofdma_cc1_cmn_eb1->ru_allocation1_1 <<
516 QDF_MON_STATUS_EHT_RU_ALLOC_FIELD1_1_SHIFT);
517 ppdu_info->rx_status.eht_data[1] |= 1 <<
518 QDF_MON_STATUS_EHT_RU_ALLOC_KNOWN1_1_SHIFT;
519 ppdu_info->tlv_aggr.rd_idx += 8;
520 break;
521 default:
522 break;
523 }
524
525 ppdu_info->rx_status.eht_known |= (num_ru_allocation_known <<
526 QDF_MON_STATUS_EHT_NUM_KNOWN_RU_ALLOCATIONS_SHIFT);
527
528 return HAL_TLV_STATUS_PPDU_NOT_DONE;
529 }
530
531 static inline uint32_t
hal_rx_parse_eht_sig_non_ofdma_9224(struct hal_soc * hal_soc,void * tlv,struct hal_rx_ppdu_info * ppdu_info)532 hal_rx_parse_eht_sig_non_ofdma_9224(struct hal_soc *hal_soc, void *tlv,
533 struct hal_rx_ppdu_info *ppdu_info)
534 {
535 hal_rx_parse_usig_overflow(hal_soc, tlv, ppdu_info);
536 hal_rx_parse_non_ofdma_users(hal_soc, tlv, ppdu_info);
537
538 if (hal_rx_is_mu_mimo_user(hal_soc, ppdu_info)) {
539 ppdu_info->tlv_aggr.rd_idx += 16;
540 hal_rx_parse_eht_sig_mumimo_user_info(hal_soc, tlv,
541 ppdu_info);
542 } else {
543 ppdu_info->tlv_aggr.rd_idx += 4;
544 hal_rx_parse_eht_sig_non_mumimo_user_info(hal_soc, tlv,
545 ppdu_info);
546 }
547
548 return HAL_TLV_STATUS_PPDU_NOT_DONE;
549 }
550
551 static inline uint32_t
hal_rx_parse_eht_sig_ofdma_9224(struct hal_soc * hal_soc,void * tlv,struct hal_rx_ppdu_info * ppdu_info)552 hal_rx_parse_eht_sig_ofdma_9224(struct hal_soc *hal_soc, void *tlv,
553 struct hal_rx_ppdu_info *ppdu_info)
554 {
555 hal_rx_parse_usig_overflow(hal_soc, tlv, ppdu_info);
556 hal_rx_parse_ru_allocation_9224(hal_soc, tlv, ppdu_info);
557 hal_rx_parse_eht_sig_non_mumimo_user_info(hal_soc, tlv,
558 ppdu_info);
559
560 return HAL_TLV_STATUS_PPDU_NOT_DONE;
561 }
562
563 /**
564 * hal_rx_parse_eht_sig_hdr_9224()
565 * - process eht sig header
566 * @hal_soc: HAL soc handle
567 * @tlv: pointer to EHT SIG TLV buffer
568 * @ppdu_info_handle: pointer to ppdu_info
569 *
570 * Return: None
571 */
572 static
hal_rx_parse_eht_sig_hdr_9224(struct hal_soc * hal_soc,uint8_t * tlv,void * ppdu_info_handle)573 void hal_rx_parse_eht_sig_hdr_9224(struct hal_soc *hal_soc,
574 uint8_t *tlv,
575 void *ppdu_info_handle)
576 {
577 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_handle;
578
579 ppdu_info->rx_status.eht_flags = 1;
580
581 if (hal_rx_is_frame_type_ndp(hal_soc, ppdu_info))
582 hal_rx_parse_eht_sig_ndp(hal_soc, tlv, ppdu_info);
583 else if (hal_rx_is_non_ofdma(hal_soc, ppdu_info))
584 hal_rx_parse_eht_sig_non_ofdma_9224(hal_soc, tlv, ppdu_info);
585 else if (hal_rx_is_ofdma(hal_soc, ppdu_info))
586 hal_rx_parse_eht_sig_ofdma_9224(hal_soc, tlv, ppdu_info);
587 }
588
589 #else
590 /**
591 * hal_rx_proc_phyrx_other_receive_info_tlv_9224() - API to get tlv info
592 * @rx_tlv_hdr: RX TLV header
593 * @ppdu_info_hdl: Handle to PPDU info to update
594 *
595 * Return: None
596 */
597 static inline
hal_rx_proc_phyrx_other_receive_info_tlv_9224(void * rx_tlv_hdr,void * ppdu_info_hdl)598 void hal_rx_proc_phyrx_other_receive_info_tlv_9224(void *rx_tlv_hdr,
599 void *ppdu_info_hdl)
600 {
601 }
602 #endif /* WLAN_SA_API_ENABLE && QCA_WIFI_QCA9574 */
603
604 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
605 static inline
hal_rx_get_bb_info_9224(void * rx_tlv,void * ppdu_info_hdl)606 void hal_rx_get_bb_info_9224(void *rx_tlv, void *ppdu_info_hdl)
607 {
608 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
609
610 ppdu_info->cfr_info.bb_captured_channel =
611 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL);
612
613 ppdu_info->cfr_info.bb_captured_timeout =
614 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT);
615
616 ppdu_info->cfr_info.bb_captured_reason =
617 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON);
618 }
619
620 static inline
hal_rx_get_rtt_info_9224(void * rx_tlv,void * ppdu_info_hdl)621 void hal_rx_get_rtt_info_9224(void *rx_tlv, void *ppdu_info_hdl)
622 {
623 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
624
625 ppdu_info->cfr_info.rx_location_info_valid =
626 HAL_RX_GET_64(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
627 RX_LOCATION_INFO_VALID);
628
629 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 =
630 HAL_RX_GET_64(rx_tlv,
631 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
632 RTT_CHE_BUFFER_POINTER_LOW32);
633
634 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 =
635 HAL_RX_GET_64(rx_tlv,
636 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
637 RTT_CHE_BUFFER_POINTER_HIGH8);
638
639 ppdu_info->cfr_info.chan_capture_status =
640 HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv);
641
642 ppdu_info->cfr_info.rx_start_ts =
643 HAL_RX_GET_64(rx_tlv,
644 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
645 RX_START_TS);
646
647 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t)
648 HAL_RX_GET_64(rx_tlv,
649 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
650 RTT_CFO_MEASUREMENT);
651
652 ppdu_info->cfr_info.agc_gain_info0 =
653 HAL_RX_GET_64(rx_tlv,
654 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
655 GAIN_CHAIN0);
656
657 ppdu_info->cfr_info.agc_gain_info0 |=
658 (((uint32_t)HAL_RX_GET_64(rx_tlv,
659 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
660 GAIN_CHAIN1)) << 16);
661
662 ppdu_info->cfr_info.agc_gain_info1 =
663 HAL_RX_GET_64(rx_tlv,
664 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
665 GAIN_CHAIN2);
666
667 ppdu_info->cfr_info.agc_gain_info1 |=
668 (((uint32_t)HAL_RX_GET_64(rx_tlv,
669 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
670 GAIN_CHAIN3)) << 16);
671
672 ppdu_info->cfr_info.agc_gain_info2 = 0;
673
674 ppdu_info->cfr_info.agc_gain_info3 = 0;
675
676 ppdu_info->cfr_info.mcs_rate =
677 HAL_RX_GET_64(rx_tlv,
678 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
679 RTT_MCS_RATE);
680 ppdu_info->cfr_info.gi_type =
681 HAL_RX_GET_64(rx_tlv,
682 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
683 RTT_GI_TYPE);
684 }
685 #endif
686
687 #ifdef CONFIG_WORD_BASED_TLV
688 /**
689 * hal_rx_dump_mpdu_start_tlv_9224() - dump RX mpdu_start TLV in structured
690 * human readable format.
691 * @mpdustart: pointer the rx_attention TLV in pkt.
692 * @dbg_level: log level.
693 *
694 * Return: void
695 */
hal_rx_dump_mpdu_start_tlv_9224(void * mpdustart,uint8_t dbg_level)696 static inline void hal_rx_dump_mpdu_start_tlv_9224(void *mpdustart,
697 uint8_t dbg_level)
698 {
699 struct rx_mpdu_start_compact *mpdu_info =
700 (struct rx_mpdu_start_compact *)mpdustart;
701
702 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
703 "rx_mpdu_start tlv (1/5) - "
704 "rx_reo_queue_desc_addr_39_32 :%x"
705 "receive_queue_number:%x "
706 "pre_delim_err_warning:%x "
707 "first_delim_err:%x "
708 "pn_31_0:%x "
709 "pn_63_32:%x "
710 "pn_95_64:%x ",
711 mpdu_info->rx_reo_queue_desc_addr_39_32,
712 mpdu_info->receive_queue_number,
713 mpdu_info->pre_delim_err_warning,
714 mpdu_info->first_delim_err,
715 mpdu_info->pn_31_0,
716 mpdu_info->pn_63_32,
717 mpdu_info->pn_95_64);
718
719 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
720 "rx_mpdu_start tlv (2/5) - "
721 "ast_index:%x "
722 "sw_peer_id:%x "
723 "mpdu_frame_control_valid:%x "
724 "mpdu_duration_valid:%x "
725 "mac_addr_ad1_valid:%x "
726 "mac_addr_ad2_valid:%x "
727 "mac_addr_ad3_valid:%x "
728 "mac_addr_ad4_valid:%x "
729 "mpdu_sequence_control_valid :%x"
730 "mpdu_qos_control_valid:%x "
731 "mpdu_ht_control_valid:%x "
732 "frame_encryption_info_valid :%x",
733 mpdu_info->ast_index,
734 mpdu_info->sw_peer_id,
735 mpdu_info->mpdu_frame_control_valid,
736 mpdu_info->mpdu_duration_valid,
737 mpdu_info->mac_addr_ad1_valid,
738 mpdu_info->mac_addr_ad2_valid,
739 mpdu_info->mac_addr_ad3_valid,
740 mpdu_info->mac_addr_ad4_valid,
741 mpdu_info->mpdu_sequence_control_valid,
742 mpdu_info->mpdu_qos_control_valid,
743 mpdu_info->mpdu_ht_control_valid,
744 mpdu_info->frame_encryption_info_valid);
745
746 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
747 "rx_mpdu_start tlv (3/5) - "
748 "mpdu_fragment_number:%x "
749 "more_fragment_flag:%x "
750 "fr_ds:%x "
751 "to_ds:%x "
752 "encrypted:%x "
753 "mpdu_retry:%x "
754 "mpdu_sequence_number:%x ",
755 mpdu_info->mpdu_fragment_number,
756 mpdu_info->more_fragment_flag,
757 mpdu_info->fr_ds,
758 mpdu_info->to_ds,
759 mpdu_info->encrypted,
760 mpdu_info->mpdu_retry,
761 mpdu_info->mpdu_sequence_number);
762
763 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
764 "rx_mpdu_start tlv (4/5) - "
765 "mpdu_frame_control_field:%x "
766 "mpdu_duration_field:%x ",
767 mpdu_info->mpdu_frame_control_field,
768 mpdu_info->mpdu_duration_field);
769
770 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
771 "rx_mpdu_start tlv (5/5) - "
772 "mac_addr_ad1_31_0:%x "
773 "mac_addr_ad1_47_32:%x "
774 "mac_addr_ad2_15_0:%x "
775 "mac_addr_ad2_47_16:%x "
776 "mac_addr_ad3_31_0:%x "
777 "mac_addr_ad3_47_32:%x "
778 "mpdu_sequence_control_field :%x",
779 mpdu_info->mac_addr_ad1_31_0,
780 mpdu_info->mac_addr_ad1_47_32,
781 mpdu_info->mac_addr_ad2_15_0,
782 mpdu_info->mac_addr_ad2_47_16,
783 mpdu_info->mac_addr_ad3_31_0,
784 mpdu_info->mac_addr_ad3_47_32,
785 mpdu_info->mpdu_sequence_control_field);
786 }
787
788 /**
789 * hal_rx_dump_msdu_end_tlv_9224() - dump RX msdu_end TLV in structured human
790 * readable format.
791 * @msduend: pointer the msdu_end TLV in pkt.
792 * @dbg_level: log level.
793 *
794 * Return: void
795 */
hal_rx_dump_msdu_end_tlv_9224(void * msduend,uint8_t dbg_level)796 static void hal_rx_dump_msdu_end_tlv_9224(void *msduend,
797 uint8_t dbg_level)
798 {
799 struct rx_msdu_end_compact *msdu_end =
800 (struct rx_msdu_end_compact *)msduend;
801
802 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
803 "rx_msdu_end tlv - "
804 "key_id_octet: %d "
805 "tcp_udp_chksum: %d "
806 "sa_idx_timeout: %d "
807 "da_idx_timeout: %d "
808 "msdu_limit_error: %d "
809 "flow_idx_timeout: %d "
810 "flow_idx_invalid: %d "
811 "wifi_parser_error: %d "
812 "sa_is_valid: %d "
813 "da_is_valid: %d "
814 "da_is_mcbc: %d "
815 "tkip_mic_err: %d "
816 "l3_header_padding: %d "
817 "first_msdu: %d "
818 "last_msdu: %d "
819 "sa_idx: %d "
820 "msdu_drop: %d "
821 "reo_destination_indication: %d "
822 "flow_idx: %d "
823 "fse_metadata: %d "
824 "cce_metadata: %d "
825 "sa_sw_peer_id: %d ",
826 msdu_end->key_id_octet,
827 msdu_end->tcp_udp_chksum,
828 msdu_end->sa_idx_timeout,
829 msdu_end->da_idx_timeout,
830 msdu_end->msdu_limit_error,
831 msdu_end->flow_idx_timeout,
832 msdu_end->flow_idx_invalid,
833 msdu_end->wifi_parser_error,
834 msdu_end->sa_is_valid,
835 msdu_end->da_is_valid,
836 msdu_end->da_is_mcbc,
837 msdu_end->tkip_mic_err,
838 msdu_end->l3_header_padding,
839 msdu_end->first_msdu,
840 msdu_end->last_msdu,
841 msdu_end->sa_idx,
842 msdu_end->msdu_drop,
843 msdu_end->reo_destination_indication,
844 msdu_end->flow_idx,
845 msdu_end->fse_metadata,
846 msdu_end->cce_metadata,
847 msdu_end->sa_sw_peer_id);
848 }
849 #else
hal_rx_dump_mpdu_start_tlv_9224(void * mpdustart,uint8_t dbg_level)850 static inline void hal_rx_dump_mpdu_start_tlv_9224(void *mpdustart,
851 uint8_t dbg_level)
852 {
853 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart;
854 struct rx_mpdu_info *mpdu_info =
855 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details;
856
857 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
858 "rx_mpdu_start tlv (1/5) - "
859 "rx_reo_queue_desc_addr_31_0 :%x"
860 "rx_reo_queue_desc_addr_39_32 :%x"
861 "receive_queue_number:%x "
862 "pre_delim_err_warning:%x "
863 "first_delim_err:%x "
864 "reserved_2a:%x "
865 "pn_31_0:%x "
866 "pn_63_32:%x "
867 "pn_95_64:%x "
868 "pn_127_96:%x "
869 "epd_en:%x "
870 "all_frames_shall_be_encrypted :%x"
871 "encrypt_type:%x "
872 "wep_key_width_for_variable_key :%x"
873 "mesh_sta:%x "
874 "bssid_hit:%x "
875 "bssid_number:%x "
876 "tid:%x "
877 "reserved_7a:%x ",
878 mpdu_info->rx_reo_queue_desc_addr_31_0,
879 mpdu_info->rx_reo_queue_desc_addr_39_32,
880 mpdu_info->receive_queue_number,
881 mpdu_info->pre_delim_err_warning,
882 mpdu_info->first_delim_err,
883 mpdu_info->reserved_2a,
884 mpdu_info->pn_31_0,
885 mpdu_info->pn_63_32,
886 mpdu_info->pn_95_64,
887 mpdu_info->pn_127_96,
888 mpdu_info->epd_en,
889 mpdu_info->all_frames_shall_be_encrypted,
890 mpdu_info->encrypt_type,
891 mpdu_info->wep_key_width_for_variable_key,
892 mpdu_info->mesh_sta,
893 mpdu_info->bssid_hit,
894 mpdu_info->bssid_number,
895 mpdu_info->tid,
896 mpdu_info->reserved_7a);
897
898 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
899 "rx_mpdu_start tlv (2/5) - "
900 "ast_index:%x "
901 "sw_peer_id:%x "
902 "mpdu_frame_control_valid:%x "
903 "mpdu_duration_valid:%x "
904 "mac_addr_ad1_valid:%x "
905 "mac_addr_ad2_valid:%x "
906 "mac_addr_ad3_valid:%x "
907 "mac_addr_ad4_valid:%x "
908 "mpdu_sequence_control_valid :%x"
909 "mpdu_qos_control_valid:%x "
910 "mpdu_ht_control_valid:%x "
911 "frame_encryption_info_valid :%x",
912 mpdu_info->ast_index,
913 mpdu_info->sw_peer_id,
914 mpdu_info->mpdu_frame_control_valid,
915 mpdu_info->mpdu_duration_valid,
916 mpdu_info->mac_addr_ad1_valid,
917 mpdu_info->mac_addr_ad2_valid,
918 mpdu_info->mac_addr_ad3_valid,
919 mpdu_info->mac_addr_ad4_valid,
920 mpdu_info->mpdu_sequence_control_valid,
921 mpdu_info->mpdu_qos_control_valid,
922 mpdu_info->mpdu_ht_control_valid,
923 mpdu_info->frame_encryption_info_valid);
924
925 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
926 "rx_mpdu_start tlv (3/5) - "
927 "mpdu_fragment_number:%x "
928 "more_fragment_flag:%x "
929 "reserved_11a:%x "
930 "fr_ds:%x "
931 "to_ds:%x "
932 "encrypted:%x "
933 "mpdu_retry:%x "
934 "mpdu_sequence_number:%x ",
935 mpdu_info->mpdu_fragment_number,
936 mpdu_info->more_fragment_flag,
937 mpdu_info->reserved_11a,
938 mpdu_info->fr_ds,
939 mpdu_info->to_ds,
940 mpdu_info->encrypted,
941 mpdu_info->mpdu_retry,
942 mpdu_info->mpdu_sequence_number);
943
944 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
945 "rx_mpdu_start tlv (4/5) - "
946 "mpdu_frame_control_field:%x "
947 "mpdu_duration_field:%x ",
948 mpdu_info->mpdu_frame_control_field,
949 mpdu_info->mpdu_duration_field);
950
951 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
952 "rx_mpdu_start tlv (5/5) - "
953 "mac_addr_ad1_31_0:%x "
954 "mac_addr_ad1_47_32:%x "
955 "mac_addr_ad2_15_0:%x "
956 "mac_addr_ad2_47_16:%x "
957 "mac_addr_ad3_31_0:%x "
958 "mac_addr_ad3_47_32:%x "
959 "mpdu_sequence_control_field :%x"
960 "mac_addr_ad4_31_0:%x "
961 "mac_addr_ad4_47_32:%x "
962 "mpdu_qos_control_field:%x ",
963 mpdu_info->mac_addr_ad1_31_0,
964 mpdu_info->mac_addr_ad1_47_32,
965 mpdu_info->mac_addr_ad2_15_0,
966 mpdu_info->mac_addr_ad2_47_16,
967 mpdu_info->mac_addr_ad3_31_0,
968 mpdu_info->mac_addr_ad3_47_32,
969 mpdu_info->mpdu_sequence_control_field,
970 mpdu_info->mac_addr_ad4_31_0,
971 mpdu_info->mac_addr_ad4_47_32,
972 mpdu_info->mpdu_qos_control_field);
973 }
974
hal_rx_dump_msdu_end_tlv_9224(void * msduend,uint8_t dbg_level)975 static void hal_rx_dump_msdu_end_tlv_9224(void *msduend,
976 uint8_t dbg_level)
977 {
978 struct rx_msdu_end *msdu_end =
979 (struct rx_msdu_end *)msduend;
980
981 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
982 "rx_msdu_end tlv - "
983 "key_id_octet: %d "
984 "cce_super_rule: %d "
985 "cce_classify_not_done_truncat: %d "
986 "cce_classify_not_done_cce_dis: %d "
987 "rule_indication_31_0: %d "
988 "tcp_udp_chksum: %d "
989 "sa_idx_timeout: %d "
990 "da_idx_timeout: %d "
991 "msdu_limit_error: %d "
992 "flow_idx_timeout: %d "
993 "flow_idx_invalid: %d "
994 "wifi_parser_error: %d "
995 "sa_is_valid: %d "
996 "da_is_valid: %d "
997 "da_is_mcbc: %d "
998 "tkip_mic_err: %d "
999 "l3_header_padding: %d "
1000 "first_msdu: %d "
1001 "last_msdu: %d "
1002 "sa_idx: %d "
1003 "msdu_drop: %d "
1004 "reo_destination_indication: %d "
1005 "flow_idx: %d "
1006 "fse_metadata: %d "
1007 "cce_metadata: %d "
1008 "sa_sw_peer_id: %d ",
1009 msdu_end->key_id_octet,
1010 msdu_end->cce_super_rule,
1011 msdu_end->cce_classify_not_done_truncate,
1012 msdu_end->cce_classify_not_done_cce_dis,
1013 msdu_end->rule_indication_31_0,
1014 msdu_end->tcp_udp_chksum,
1015 msdu_end->sa_idx_timeout,
1016 msdu_end->da_idx_timeout,
1017 msdu_end->msdu_limit_error,
1018 msdu_end->flow_idx_timeout,
1019 msdu_end->flow_idx_invalid,
1020 msdu_end->wifi_parser_error,
1021 msdu_end->sa_is_valid,
1022 msdu_end->da_is_valid,
1023 msdu_end->da_is_mcbc,
1024 msdu_end->tkip_mic_err,
1025 msdu_end->l3_header_padding,
1026 msdu_end->first_msdu,
1027 msdu_end->last_msdu,
1028 msdu_end->sa_idx,
1029 msdu_end->msdu_drop,
1030 msdu_end->reo_destination_indication,
1031 msdu_end->flow_idx,
1032 msdu_end->fse_metadata,
1033 msdu_end->cce_metadata,
1034 msdu_end->sa_sw_peer_id);
1035 }
1036 #endif
1037
1038 /**
1039 * hal_reo_status_get_header_9224() - Process reo desc info
1040 * @ring_desc: Pointer to reo descriptor
1041 * @b: tlv type info
1042 * @h1: Pointer to hal_reo_status_header where info to be stored
1043 *
1044 * Return: none.
1045 *
1046 */
hal_reo_status_get_header_9224(hal_ring_desc_t ring_desc,int b,void * h1)1047 static void hal_reo_status_get_header_9224(hal_ring_desc_t ring_desc,
1048 int b, void *h1)
1049 {
1050 uint64_t *d = (uint64_t *)ring_desc;
1051 uint64_t val1 = 0;
1052 struct hal_reo_status_header *h =
1053 (struct hal_reo_status_header *)h1;
1054
1055 /* Offsets of descriptor fields defined in HW headers start
1056 * from the field after TLV header
1057 */
1058 d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
1059
1060 switch (b) {
1061 case HAL_REO_QUEUE_STATS_STATUS_TLV:
1062 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
1063 STATUS_HEADER_REO_STATUS_NUMBER)];
1064 break;
1065 case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
1066 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS,
1067 STATUS_HEADER_REO_STATUS_NUMBER)];
1068 break;
1069 case HAL_REO_FLUSH_CACHE_STATUS_TLV:
1070 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
1071 STATUS_HEADER_REO_STATUS_NUMBER)];
1072 break;
1073 case HAL_REO_UNBLK_CACHE_STATUS_TLV:
1074 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
1075 STATUS_HEADER_REO_STATUS_NUMBER)];
1076 break;
1077 case HAL_REO_TIMOUT_LIST_STATUS_TLV:
1078 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
1079 STATUS_HEADER_REO_STATUS_NUMBER)];
1080 break;
1081 case HAL_REO_DESC_THRES_STATUS_TLV:
1082 val1 =
1083 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
1084 STATUS_HEADER_REO_STATUS_NUMBER)];
1085 break;
1086 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
1087 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS,
1088 STATUS_HEADER_REO_STATUS_NUMBER)];
1089 break;
1090 default:
1091 qdf_nofl_err("ERROR: Unknown tlv\n");
1092 break;
1093 }
1094 h->cmd_num =
1095 HAL_GET_FIELD(
1096 UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER,
1097 val1);
1098 h->exec_time =
1099 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER,
1100 CMD_EXECUTION_TIME, val1);
1101 h->status =
1102 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER,
1103 REO_CMD_EXECUTION_STATUS, val1);
1104 switch (b) {
1105 case HAL_REO_QUEUE_STATS_STATUS_TLV:
1106 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
1107 STATUS_HEADER_TIMESTAMP)];
1108 break;
1109 case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
1110 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS,
1111 STATUS_HEADER_TIMESTAMP)];
1112 break;
1113 case HAL_REO_FLUSH_CACHE_STATUS_TLV:
1114 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
1115 STATUS_HEADER_TIMESTAMP)];
1116 break;
1117 case HAL_REO_UNBLK_CACHE_STATUS_TLV:
1118 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
1119 STATUS_HEADER_TIMESTAMP)];
1120 break;
1121 case HAL_REO_TIMOUT_LIST_STATUS_TLV:
1122 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
1123 STATUS_HEADER_TIMESTAMP)];
1124 break;
1125 case HAL_REO_DESC_THRES_STATUS_TLV:
1126 val1 =
1127 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
1128 STATUS_HEADER_TIMESTAMP)];
1129 break;
1130 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
1131 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS,
1132 STATUS_HEADER_TIMESTAMP)];
1133 break;
1134 default:
1135 qdf_nofl_err("ERROR: Unknown tlv\n");
1136 break;
1137 }
1138 h->tstamp =
1139 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1);
1140 }
1141
1142 static
hal_rx_msdu0_buffer_addr_lsb_9224(void * link_desc_va)1143 void *hal_rx_msdu0_buffer_addr_lsb_9224(void *link_desc_va)
1144 {
1145 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
1146 }
1147
1148 static
hal_rx_msdu_desc_info_ptr_get_9224(void * msdu0)1149 void *hal_rx_msdu_desc_info_ptr_get_9224(void *msdu0)
1150 {
1151 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
1152 }
1153
1154 static
hal_ent_mpdu_desc_info_9224(void * ent_ring_desc)1155 void *hal_ent_mpdu_desc_info_9224(void *ent_ring_desc)
1156 {
1157 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
1158 }
1159
1160 static
hal_dst_mpdu_desc_info_9224(void * dst_ring_desc)1161 void *hal_dst_mpdu_desc_info_9224(void *dst_ring_desc)
1162 {
1163 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
1164 }
1165
1166 /**
1167 * hal_reo_config_9224() - Set reo config parameters
1168 * @soc: hal soc handle
1169 * @reg_val: value to be set
1170 * @reo_params: reo parameters
1171 *
1172 * Return: void
1173 */
1174 static void
hal_reo_config_9224(struct hal_soc * soc,uint32_t reg_val,struct hal_reo_params * reo_params)1175 hal_reo_config_9224(struct hal_soc *soc,
1176 uint32_t reg_val,
1177 struct hal_reo_params *reo_params)
1178 {
1179 HAL_REO_R0_CONFIG(soc, reg_val, reo_params);
1180 }
1181
1182 /**
1183 * hal_rx_msdu_desc_info_get_ptr_9224() - Get msdu desc info ptr
1184 * @msdu_details_ptr: Pointer to msdu_details_ptr
1185 *
1186 * Return: Pointer to rx_msdu_desc_info structure.
1187 *
1188 */
hal_rx_msdu_desc_info_get_ptr_9224(void * msdu_details_ptr)1189 static void *hal_rx_msdu_desc_info_get_ptr_9224(void *msdu_details_ptr)
1190 {
1191 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
1192 }
1193
1194 /**
1195 * hal_rx_link_desc_msdu0_ptr_9224() - Get pointer to rx_msdu details
1196 * @link_desc: Pointer to link desc
1197 *
1198 * Return: Pointer to rx_msdu_details structure
1199 *
1200 */
hal_rx_link_desc_msdu0_ptr_9224(void * link_desc)1201 static void *hal_rx_link_desc_msdu0_ptr_9224(void *link_desc)
1202 {
1203 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
1204 }
1205
1206 /**
1207 * hal_get_window_address_9224() - Function to get hp/tp address
1208 * @hal_soc: Pointer to hal_soc
1209 * @addr: address offset of register
1210 *
1211 * Return: modified address offset of register
1212 */
1213
hal_get_window_address_9224(struct hal_soc * hal_soc,qdf_iomem_t addr)1214 static inline qdf_iomem_t hal_get_window_address_9224(struct hal_soc *hal_soc,
1215 qdf_iomem_t addr)
1216 {
1217 uint32_t offset = addr - hal_soc->dev_base_addr;
1218 qdf_iomem_t new_offset;
1219
1220 /*
1221 * If offset lies within DP register range, use 3rd window to write
1222 * into DP region.
1223 */
1224 if ((offset ^ UMAC_BASE) < WINDOW_RANGE_MASK) {
1225 new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) +
1226 (offset & WINDOW_RANGE_MASK));
1227 /*
1228 * If offset lies within CE register range, use 2nd window to write
1229 * into CE region.
1230 */
1231 } else if ((offset ^ CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) {
1232 new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) +
1233 (offset & WINDOW_RANGE_MASK));
1234 } else {
1235 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
1236 "%s: ERROR: Accessing Wrong register\n", __func__);
1237 qdf_assert_always(0);
1238 return 0;
1239 }
1240 return new_offset;
1241 }
1242
hal_write_window_register(struct hal_soc * hal_soc)1243 static inline void hal_write_window_register(struct hal_soc *hal_soc)
1244 {
1245 /* Write value into window configuration register */
1246 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
1247 WINDOW_CONFIGURATION_VALUE_9224);
1248 }
1249
1250 static
hal_compute_reo_remap_ix2_ix3_9224(uint32_t * ring,uint32_t num_rings,uint32_t * remap1,uint32_t * remap2)1251 void hal_compute_reo_remap_ix2_ix3_9224(uint32_t *ring, uint32_t num_rings,
1252 uint32_t *remap1, uint32_t *remap2)
1253 {
1254 switch (num_rings) {
1255 case 1:
1256 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1257 HAL_REO_REMAP_IX2(ring[0], 17) |
1258 HAL_REO_REMAP_IX2(ring[0], 18) |
1259 HAL_REO_REMAP_IX2(ring[0], 19) |
1260 HAL_REO_REMAP_IX2(ring[0], 20) |
1261 HAL_REO_REMAP_IX2(ring[0], 21) |
1262 HAL_REO_REMAP_IX2(ring[0], 22) |
1263 HAL_REO_REMAP_IX2(ring[0], 23);
1264
1265 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
1266 HAL_REO_REMAP_IX3(ring[0], 25) |
1267 HAL_REO_REMAP_IX3(ring[0], 26) |
1268 HAL_REO_REMAP_IX3(ring[0], 27) |
1269 HAL_REO_REMAP_IX3(ring[0], 28) |
1270 HAL_REO_REMAP_IX3(ring[0], 29) |
1271 HAL_REO_REMAP_IX3(ring[0], 30) |
1272 HAL_REO_REMAP_IX3(ring[0], 31);
1273 break;
1274 case 2:
1275 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1276 HAL_REO_REMAP_IX2(ring[0], 17) |
1277 HAL_REO_REMAP_IX2(ring[1], 18) |
1278 HAL_REO_REMAP_IX2(ring[1], 19) |
1279 HAL_REO_REMAP_IX2(ring[0], 20) |
1280 HAL_REO_REMAP_IX2(ring[0], 21) |
1281 HAL_REO_REMAP_IX2(ring[1], 22) |
1282 HAL_REO_REMAP_IX2(ring[1], 23);
1283
1284 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
1285 HAL_REO_REMAP_IX3(ring[0], 25) |
1286 HAL_REO_REMAP_IX3(ring[1], 26) |
1287 HAL_REO_REMAP_IX3(ring[1], 27) |
1288 HAL_REO_REMAP_IX3(ring[0], 28) |
1289 HAL_REO_REMAP_IX3(ring[0], 29) |
1290 HAL_REO_REMAP_IX3(ring[1], 30) |
1291 HAL_REO_REMAP_IX3(ring[1], 31);
1292 break;
1293 case 3:
1294 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1295 HAL_REO_REMAP_IX2(ring[1], 17) |
1296 HAL_REO_REMAP_IX2(ring[2], 18) |
1297 HAL_REO_REMAP_IX2(ring[0], 19) |
1298 HAL_REO_REMAP_IX2(ring[1], 20) |
1299 HAL_REO_REMAP_IX2(ring[2], 21) |
1300 HAL_REO_REMAP_IX2(ring[0], 22) |
1301 HAL_REO_REMAP_IX2(ring[1], 23);
1302
1303 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) |
1304 HAL_REO_REMAP_IX3(ring[0], 25) |
1305 HAL_REO_REMAP_IX3(ring[1], 26) |
1306 HAL_REO_REMAP_IX3(ring[2], 27) |
1307 HAL_REO_REMAP_IX3(ring[0], 28) |
1308 HAL_REO_REMAP_IX3(ring[1], 29) |
1309 HAL_REO_REMAP_IX3(ring[2], 30) |
1310 HAL_REO_REMAP_IX3(ring[0], 31);
1311 break;
1312 case 4:
1313 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1314 HAL_REO_REMAP_IX2(ring[1], 17) |
1315 HAL_REO_REMAP_IX2(ring[2], 18) |
1316 HAL_REO_REMAP_IX2(ring[3], 19) |
1317 HAL_REO_REMAP_IX2(ring[0], 20) |
1318 HAL_REO_REMAP_IX2(ring[1], 21) |
1319 HAL_REO_REMAP_IX2(ring[2], 22) |
1320 HAL_REO_REMAP_IX2(ring[3], 23);
1321
1322 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
1323 HAL_REO_REMAP_IX3(ring[1], 25) |
1324 HAL_REO_REMAP_IX3(ring[2], 26) |
1325 HAL_REO_REMAP_IX3(ring[3], 27) |
1326 HAL_REO_REMAP_IX3(ring[0], 28) |
1327 HAL_REO_REMAP_IX3(ring[1], 29) |
1328 HAL_REO_REMAP_IX3(ring[2], 30) |
1329 HAL_REO_REMAP_IX3(ring[3], 31);
1330 break;
1331 }
1332 }
1333
1334 static
hal_compute_reo_remap_ix0_9224(struct hal_soc * soc)1335 void hal_compute_reo_remap_ix0_9224(struct hal_soc *soc)
1336 {
1337 uint32_t remap0;
1338
1339 remap0 = HAL_REG_READ(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR
1340 (REO_REG_REG_BASE));
1341
1342 remap0 &= ~(HAL_REO_REMAP_IX0(0xF, 6));
1343 remap0 |= HAL_REO_REMAP_IX0(REO2PPE_DST_RING, 6);
1344
1345 HAL_REG_WRITE(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR
1346 (REO_REG_REG_BASE), remap0);
1347
1348 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 0x%x",
1349 HAL_REG_READ(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR
1350 (REO_REG_REG_BASE)));
1351 }
1352
1353 /**
1354 * hal_rx_flow_setup_fse_9224() - Setup a flow search entry in HW FST
1355 * @rx_fst: Pointer to the Rx Flow Search Table
1356 * @table_offset: offset into the table where the flow is to be setup
1357 * @rx_flow: Flow Parameters
1358 *
1359 * Return: Success/Failure
1360 */
1361 static void *
hal_rx_flow_setup_fse_9224(uint8_t * rx_fst,uint32_t table_offset,uint8_t * rx_flow)1362 hal_rx_flow_setup_fse_9224(uint8_t *rx_fst, uint32_t table_offset,
1363 uint8_t *rx_flow)
1364 {
1365 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
1366 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
1367 uint8_t *fse;
1368 bool fse_valid;
1369
1370 if (table_offset >= fst->max_entries) {
1371 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
1372 "HAL FSE table offset %u exceeds max entries %u",
1373 table_offset, fst->max_entries);
1374 return NULL;
1375 }
1376
1377 fse = (uint8_t *)fst->base_vaddr +
1378 (table_offset * HAL_RX_FST_ENTRY_SIZE);
1379
1380 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
1381
1382 if (fse_valid) {
1383 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
1384 "HAL FSE %pK already valid", fse);
1385 return NULL;
1386 }
1387
1388 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) =
1389 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96,
1390 qdf_htonl(flow->tuple_info.src_ip_127_96));
1391
1392 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) =
1393 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64,
1394 qdf_htonl(flow->tuple_info.src_ip_95_64));
1395
1396 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) =
1397 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32,
1398 qdf_htonl(flow->tuple_info.src_ip_63_32));
1399
1400 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) =
1401 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0,
1402 qdf_htonl(flow->tuple_info.src_ip_31_0));
1403
1404 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) =
1405 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96,
1406 qdf_htonl(flow->tuple_info.dest_ip_127_96));
1407
1408 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) =
1409 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64,
1410 qdf_htonl(flow->tuple_info.dest_ip_95_64));
1411
1412 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) =
1413 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32,
1414 qdf_htonl(flow->tuple_info.dest_ip_63_32));
1415
1416 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) =
1417 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0,
1418 qdf_htonl(flow->tuple_info.dest_ip_31_0));
1419
1420 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT);
1421 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |=
1422 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT,
1423 (flow->tuple_info.dest_port));
1424
1425 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT);
1426 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |=
1427 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT,
1428 (flow->tuple_info.src_port));
1429
1430 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL);
1431 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |=
1432 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL,
1433 flow->tuple_info.l4_protocol);
1434
1435 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, USE_PPE);
1436 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, USE_PPE) |=
1437 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, USE_PPE, flow->use_ppe_ds);
1438
1439 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, PRIORITY_VALID);
1440 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, PRIORITY_VALID) |=
1441 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, PRIORITY_VALID,
1442 flow->priority_vld);
1443
1444 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SERVICE_CODE);
1445 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SERVICE_CODE) |=
1446 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SERVICE_CODE,
1447 flow->service_code);
1448
1449 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER);
1450 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |=
1451 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER,
1452 flow->reo_destination_handler);
1453
1454 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
1455 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |=
1456 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1);
1457
1458 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA);
1459 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) =
1460 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA,
1461 flow->fse_metadata);
1462
1463 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION);
1464 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |=
1465 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY,
1466 REO_DESTINATION_INDICATION,
1467 flow->reo_destination_indication);
1468
1469 /* Reset all the other fields in FSE */
1470 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9);
1471 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP);
1472 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT);
1473 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT);
1474 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP);
1475
1476 return fse;
1477 }
1478
1479 /**
1480 * hal_rx_dump_pkt_hdr_tlv_9224() - dump RX pkt header TLV in hex format
1481 * @pkt_tlvs: pointer the pkt_hdr_tlv in pkt.
1482 * @dbg_level: log level.
1483 *
1484 * Return: void
1485 */
1486 #ifndef NO_RX_PKT_HDR_TLV
hal_rx_dump_pkt_hdr_tlv_9224(struct rx_pkt_tlvs * pkt_tlvs,uint8_t dbg_level)1487 static inline void hal_rx_dump_pkt_hdr_tlv_9224(struct rx_pkt_tlvs *pkt_tlvs,
1488 uint8_t dbg_level)
1489 {
1490 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv;
1491
1492 hal_verbose_debug("\n---------------\n"
1493 "rx_pkt_hdr_tlv\n"
1494 "---------------\n"
1495 "phy_ppdu_id 0x%x ",
1496 pkt_hdr_tlv->phy_ppdu_id);
1497
1498 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr,
1499 sizeof(pkt_hdr_tlv->rx_pkt_hdr));
1500 }
1501 #else
hal_rx_dump_pkt_hdr_tlv_9224(struct rx_pkt_tlvs * pkt_tlvs,uint8_t dbg_level)1502 static inline void hal_rx_dump_pkt_hdr_tlv_9224(struct rx_pkt_tlvs *pkt_tlvs,
1503 uint8_t dbg_level)
1504 {
1505 }
1506 #endif
1507
1508 /**
1509 * hal_tx_dump_ppe_vp_entry_9224() - API to print PPE VP entries
1510 * @hal_soc_hdl: HAL SoC handle
1511 *
1512 * Return: void
1513 */
1514 static inline
hal_tx_dump_ppe_vp_entry_9224(hal_soc_handle_t hal_soc_hdl)1515 void hal_tx_dump_ppe_vp_entry_9224(hal_soc_handle_t hal_soc_hdl)
1516 {
1517 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
1518 uint32_t reg_addr, reg_val = 0, i;
1519
1520 for (i = 0; i < HAL_PPE_VP_ENTRIES_MAX; i++) {
1521 reg_addr =
1522 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(
1523 MAC_TCL_REG_REG_BASE,
1524 i);
1525 reg_val = HAL_REG_READ(soc, reg_addr);
1526 hal_verbose_debug("%d: 0x%x\n", i, reg_val);
1527 }
1528 }
1529
1530 /**
1531 * hal_rx_dump_pkt_tlvs_9224() - API to print RX Pkt TLVS QCN9224
1532 * @hal_soc_hdl: hal_soc handle
1533 * @buf: pointer the pkt buffer
1534 * @dbg_level: log level
1535 *
1536 * Return: void
1537 */
1538 #ifdef CONFIG_WORD_BASED_TLV
hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl,uint8_t * buf,uint8_t dbg_level)1539 static void hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl,
1540 uint8_t *buf, uint8_t dbg_level)
1541 {
1542 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1543 struct rx_msdu_end_compact *msdu_end =
1544 &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1545 struct rx_mpdu_start_compact *mpdu_start =
1546 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1547
1548 hal_rx_dump_msdu_end_tlv_9224(msdu_end, dbg_level);
1549 hal_rx_dump_mpdu_start_tlv_9224(mpdu_start, dbg_level);
1550 hal_rx_dump_pkt_hdr_tlv_9224(pkt_tlvs, dbg_level);
1551 }
1552 #else
hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl,uint8_t * buf,uint8_t dbg_level)1553 static void hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl,
1554 uint8_t *buf, uint8_t dbg_level)
1555 {
1556 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1557 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1558 struct rx_mpdu_start *mpdu_start =
1559 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1560
1561 hal_rx_dump_msdu_end_tlv_9224(msdu_end, dbg_level);
1562 hal_rx_dump_mpdu_start_tlv_9224(mpdu_start, dbg_level);
1563 hal_rx_dump_pkt_hdr_tlv_9224(pkt_tlvs, dbg_level);
1564 }
1565 #endif
1566
1567 #define HAL_NUM_TCL_BANKS_9224 48
1568
1569 /**
1570 * hal_cmem_write_9224() - function for CMEM buffer writing
1571 * @hal_soc_hdl: HAL SOC handle
1572 * @offset: CMEM address
1573 * @value: value to write
1574 *
1575 * Return: None.
1576 */
hal_cmem_write_9224(hal_soc_handle_t hal_soc_hdl,uint32_t offset,uint32_t value)1577 static void hal_cmem_write_9224(hal_soc_handle_t hal_soc_hdl,
1578 uint32_t offset,
1579 uint32_t value)
1580 {
1581 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
1582
1583 pld_reg_write(hal->qdf_dev->dev, offset, value, NULL);
1584 }
1585
1586 /**
1587 * hal_tx_get_num_tcl_banks_9224() - Get number of banks in target
1588 *
1589 * Return: number of bank
1590 */
hal_tx_get_num_tcl_banks_9224(void)1591 static uint8_t hal_tx_get_num_tcl_banks_9224(void)
1592 {
1593 return HAL_NUM_TCL_BANKS_9224;
1594 }
1595
hal_reo_setup_9224(struct hal_soc * soc,void * reoparams,int qref_reset)1596 static void hal_reo_setup_9224(struct hal_soc *soc, void *reoparams,
1597 int qref_reset)
1598 {
1599 uint32_t reg_val;
1600 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams;
1601
1602 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR(
1603 REO_REG_REG_BASE));
1604
1605 hal_reo_config_9224(soc, reg_val, reo_params);
1606 /* Other ring enable bits and REO_ENABLE will be set by FW */
1607
1608 /* TODO: Setup destination ring mapping if enabled */
1609
1610 /* TODO: Error destination ring setting is left to default.
1611 * Default setting is to send all errors to release ring.
1612 */
1613
1614 /* Set the reo descriptor swap bits in case of BIG endian platform */
1615 hal_setup_reo_swap(soc);
1616
1617 HAL_REG_WRITE(soc,
1618 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(REO_REG_REG_BASE),
1619 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000);
1620
1621 HAL_REG_WRITE(soc,
1622 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(REO_REG_REG_BASE),
1623 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
1624
1625 HAL_REG_WRITE(soc,
1626 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(REO_REG_REG_BASE),
1627 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
1628
1629 HAL_REG_WRITE(soc,
1630 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(REO_REG_REG_BASE),
1631 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000));
1632
1633 /*
1634 * When hash based routing is enabled, routing of the rx packet
1635 * is done based on the following value: 1 _ _ _ _ The last 4
1636 * bits are based on hash[3:0]. This means the possible values
1637 * are 0x10 to 0x1f. This value is used to look-up the
1638 * ring ID configured in Destination_Ring_Ctrl_IX_* register.
1639 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3
1640 * registers need to be configured to set-up the 16 entries to
1641 * map the hash values to a ring number. There are 3 bits per
1642 * hash entry – which are mapped as follows:
1643 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI),
1644 * 7: NOT_USED.
1645 */
1646 if (reo_params->rx_hash_enabled) {
1647 hal_compute_reo_remap_ix0_9224(soc);
1648
1649 HAL_REG_WRITE(soc,
1650 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR
1651 (REO_REG_REG_BASE), reo_params->remap0);
1652
1653 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x",
1654 HAL_REG_READ(soc,
1655 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(
1656 REO_REG_REG_BASE)));
1657
1658 HAL_REG_WRITE(soc,
1659 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR
1660 (REO_REG_REG_BASE), reo_params->remap1);
1661
1662 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x",
1663 HAL_REG_READ(soc,
1664 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
1665 REO_REG_REG_BASE)));
1666
1667 HAL_REG_WRITE(soc,
1668 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR
1669 (REO_REG_REG_BASE), reo_params->remap2);
1670
1671 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x",
1672 HAL_REG_READ(soc,
1673 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
1674 REO_REG_REG_BASE)));
1675 }
1676
1677 /* TODO: Check if the following registers shoould be setup by host:
1678 * AGING_CONTROL
1679 * HIGH_MEMORY_THRESHOLD
1680 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2]
1681 * GLOBAL_LINK_DESC_COUNT_CTRL
1682 */
1683
1684 soc->reo_qref = *reo_params->reo_qref;
1685 hal_reo_shared_qaddr_init((hal_soc_handle_t)soc, qref_reset);
1686 }
1687
hal_get_rx_max_ba_window_qcn9224(int tid)1688 static uint16_t hal_get_rx_max_ba_window_qcn9224(int tid)
1689 {
1690 return HAL_RX_BA_WINDOW_1024;
1691 }
1692
1693 /**
1694 * hal_qcn9224_get_reo_qdesc_size() - Get the reo queue descriptor size from the
1695 * given Block-Ack window size
1696 * @ba_window_size: Block-Ack window size
1697 * @tid: Traffic id
1698 *
1699 * Return: reo queue descriptor size
1700 */
hal_qcn9224_get_reo_qdesc_size(uint32_t ba_window_size,int tid)1701 static uint32_t hal_qcn9224_get_reo_qdesc_size(uint32_t ba_window_size, int tid)
1702 {
1703 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for
1704 * NON_QOS_TID until HW issues are resolved.
1705 */
1706 if (tid != HAL_NON_QOS_TID)
1707 ba_window_size = hal_get_rx_max_ba_window_qcn9224(tid);
1708
1709 /* Return descriptor size corresponding to window size of 2 since
1710 * we set ba_window_size to 2 while setting up REO descriptors as
1711 * a WAR to get 2k jump exception aggregates are received without
1712 * a BA session.
1713 */
1714 if (ba_window_size <= 1) {
1715 if (tid != HAL_NON_QOS_TID)
1716 return sizeof(struct rx_reo_queue) +
1717 sizeof(struct rx_reo_queue_ext);
1718 else
1719 return sizeof(struct rx_reo_queue);
1720 }
1721
1722 if (ba_window_size <= 105)
1723 return sizeof(struct rx_reo_queue) +
1724 sizeof(struct rx_reo_queue_ext);
1725
1726 if (ba_window_size <= 210)
1727 return sizeof(struct rx_reo_queue) +
1728 (2 * sizeof(struct rx_reo_queue_ext));
1729
1730 if (ba_window_size <= 256)
1731 return sizeof(struct rx_reo_queue) +
1732 (3 * sizeof(struct rx_reo_queue_ext));
1733
1734 return sizeof(struct rx_reo_queue) +
1735 (10 * sizeof(struct rx_reo_queue_ext)) +
1736 sizeof(struct rx_reo_queue_1k);
1737 }
1738
1739 /**
1740 * hal_tx_get_num_ppe_vp_tbl_entries_9224() - get number of PPE VP entries
1741 * @hal_soc_hdl: HAL SoC handle
1742 *
1743 * Return: Number of PPE VP entries
1744 */
1745 static
hal_tx_get_num_ppe_vp_tbl_entries_9224(hal_soc_handle_t hal_soc_hdl)1746 uint32_t hal_tx_get_num_ppe_vp_tbl_entries_9224(hal_soc_handle_t hal_soc_hdl)
1747 {
1748 return HAL_PPE_VP_ENTRIES_MAX;
1749 }
1750
1751 /**
1752 * hal_tx_get_num_ppe_vp_search_idx_reg_entries_9224() - get number of PPE VP
1753 * search index registers
1754 * @hal_soc_hdl: HAL SoC handle
1755 *
1756 * Return: Number of PPE VP search index registers
1757 */
1758 static
hal_tx_get_num_ppe_vp_search_idx_reg_entries_9224(hal_soc_handle_t hal_soc_hdl)1759 uint32_t hal_tx_get_num_ppe_vp_search_idx_reg_entries_9224(hal_soc_handle_t hal_soc_hdl)
1760 {
1761 return HAL_PPE_VP_SEARCH_IDX_REG_MAX;
1762 }
1763
1764 /**
1765 * hal_rx_tlv_msdu_done_copy_get_9224() - Get msdu done copy bit from rx_tlv
1766 * @buf: pointer the RX TLV
1767 *
1768 * Return: msdu done copy bit
1769 */
hal_rx_tlv_msdu_done_copy_get_9224(uint8_t * buf)1770 static inline uint32_t hal_rx_tlv_msdu_done_copy_get_9224(uint8_t *buf)
1771 {
1772 return HAL_RX_TLV_MSDU_DONE_COPY_GET(buf);
1773 }
1774
hal_hw_txrx_ops_attach_qcn9224(struct hal_soc * hal_soc)1775 static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
1776 {
1777 /* init and setup */
1778 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
1779 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
1780 hal_soc->ops->hal_srng_hw_disable = hal_srng_hw_disable_generic;
1781 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
1782 hal_soc->ops->hal_get_window_address = hal_get_window_address_9224;
1783 hal_soc->ops->hal_cmem_write = hal_cmem_write_9224;
1784
1785 /* tx */
1786 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_9224;
1787 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_9224;
1788 hal_soc->ops->hal_tx_comp_get_status =
1789 hal_tx_comp_get_status_generic_be;
1790 hal_soc->ops->hal_tx_init_cmd_credit_ring =
1791 hal_tx_init_cmd_credit_ring_9224;
1792 hal_soc->ops->hal_tx_set_ppe_cmn_cfg =
1793 hal_tx_set_ppe_cmn_config_9224;
1794 hal_soc->ops->hal_tx_set_ppe_vp_entry =
1795 hal_tx_set_ppe_vp_entry_9224;
1796 hal_soc->ops->hal_ppeds_cfg_ast_override_map_reg =
1797 hal_ppeds_cfg_ast_override_map_reg_9224;
1798 hal_soc->ops->hal_tx_set_ppe_pri2tid =
1799 hal_tx_set_ppe_pri2tid_map_9224;
1800 hal_soc->ops->hal_tx_update_ppe_pri2tid =
1801 hal_tx_update_ppe_pri2tid_9224;
1802 hal_soc->ops->hal_tx_dump_ppe_vp_entry =
1803 hal_tx_dump_ppe_vp_entry_9224;
1804 hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries =
1805 hal_tx_get_num_ppe_vp_tbl_entries_9224;
1806 hal_soc->ops->hal_tx_enable_pri2tid_map =
1807 hal_tx_enable_pri2tid_map_9224;
1808 hal_soc->ops->hal_tx_config_rbm_mapping_be =
1809 hal_tx_config_rbm_mapping_be_9224;
1810
1811 /* rx */
1812 hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be;
1813 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
1814 hal_rx_mon_hw_desc_get_mpdu_status_be;
1815 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_9224;
1816 hal_soc->ops->hal_rx_parse_eht_sig_hdr =
1817 hal_rx_parse_eht_sig_hdr_9224;
1818 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
1819 hal_rx_proc_phyrx_other_receive_info_tlv_9224;
1820
1821 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_9224;
1822 hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
1823 hal_rx_dump_mpdu_start_tlv_9224;
1824 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_9224;
1825
1826 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_9224;
1827 hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be;
1828 hal_soc->ops->hal_rx_msdu_start_reception_type_get =
1829 hal_rx_tlv_reception_type_get_be;
1830 hal_soc->ops->hal_rx_msdu_end_da_idx_get =
1831 hal_rx_msdu_end_da_idx_get_be;
1832 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
1833 hal_rx_msdu_desc_info_get_ptr_9224;
1834 hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
1835 hal_rx_link_desc_msdu0_ptr_9224;
1836 hal_soc->ops->hal_reo_status_get_header =
1837 hal_reo_status_get_header_9224;
1838 #ifdef WLAN_PKT_CAPTURE_RX_2_0
1839 hal_soc->ops->hal_rx_status_get_tlv_info =
1840 hal_rx_status_get_tlv_info_wrapper_be;
1841 #endif
1842 hal_soc->ops->hal_rx_wbm_err_info_get =
1843 hal_rx_wbm_err_info_get_generic_be;
1844 hal_soc->ops->hal_tx_set_pcp_tid_map =
1845 hal_tx_set_pcp_tid_map_generic_be;
1846 hal_soc->ops->hal_tx_update_pcp_tid_map =
1847 hal_tx_update_pcp_tid_generic_be;
1848 hal_soc->ops->hal_tx_set_tidmap_prty =
1849 hal_tx_update_tidmap_prty_generic_be;
1850 hal_soc->ops->hal_rx_get_rx_fragment_number =
1851 hal_rx_get_rx_fragment_number_be,
1852 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
1853 hal_rx_tlv_da_is_mcbc_get_be;
1854 hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err =
1855 hal_rx_tlv_is_tkip_mic_err_get_be;
1856 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
1857 hal_rx_tlv_sa_is_valid_get_be;
1858 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be;
1859 hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be;
1860 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
1861 hal_rx_tlv_l3_hdr_padding_get_be;
1862 hal_soc->ops->hal_rx_encryption_info_valid =
1863 hal_rx_encryption_info_valid_be;
1864 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be;
1865 hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
1866 hal_rx_tlv_first_msdu_get_be;
1867 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
1868 hal_rx_tlv_da_is_valid_get_be;
1869 hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
1870 hal_rx_tlv_last_msdu_get_be;
1871 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
1872 hal_rx_get_mpdu_mac_ad4_valid_be;
1873 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
1874 hal_rx_mpdu_start_sw_peer_id_get_be;
1875 hal_soc->ops->hal_rx_tlv_peer_meta_data_get =
1876 hal_rx_msdu_peer_meta_data_get_be;
1877 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be;
1878 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be;
1879 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
1880 hal_rx_get_mpdu_frame_control_valid_be;
1881 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be;
1882 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be;
1883 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be;
1884 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
1885 hal_rx_get_mpdu_sequence_control_valid_be;
1886 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be;
1887 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be;
1888 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
1889 hal_rx_mpdu_start_mpdu_qos_control_valid_get_be;
1890 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
1891 hal_rx_msdu_end_sa_sw_peer_id_get_be;
1892 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
1893 hal_rx_msdu0_buffer_addr_lsb_9224;
1894 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
1895 hal_rx_msdu_desc_info_ptr_get_9224;
1896 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_9224;
1897 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_9224;
1898 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be;
1899 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be;
1900 hal_soc->ops->hal_rx_get_mac_addr2_valid =
1901 hal_rx_get_mac_addr2_valid_be;
1902 hal_soc->ops->hal_reo_config = hal_reo_config_9224;
1903 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be;
1904 hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
1905 hal_rx_msdu_flow_idx_invalid_be;
1906 hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
1907 hal_rx_msdu_flow_idx_timeout_be;
1908 hal_soc->ops->hal_rx_msdu_fse_metadata_get =
1909 hal_rx_msdu_fse_metadata_get_be;
1910 hal_soc->ops->hal_rx_msdu_cce_match_get =
1911 hal_rx_msdu_cce_match_get_be;
1912 hal_soc->ops->hal_rx_msdu_cce_metadata_get =
1913 hal_rx_msdu_cce_metadata_get_be;
1914 hal_soc->ops->hal_rx_msdu_get_flow_params =
1915 hal_rx_msdu_get_flow_params_be;
1916 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_be;
1917 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be;
1918
1919 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
1920 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_9224;
1921 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_9224;
1922 #else
1923 hal_soc->ops->hal_rx_get_bb_info = NULL;
1924 hal_soc->ops->hal_rx_get_rtt_info = NULL;
1925 #endif
1926
1927 /* rx - msdu fast path info fields */
1928 hal_soc->ops->hal_rx_msdu_packet_metadata_get =
1929 hal_rx_msdu_packet_metadata_get_generic_be;
1930 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
1931 hal_rx_mpdu_start_tlv_tag_valid_be;
1932 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get =
1933 hal_rx_wbm_err_msdu_continuation_get_9224;
1934
1935 /* rx - TLV struct offsets */
1936 hal_soc->ops->hal_rx_msdu_end_offset_get =
1937 hal_rx_msdu_end_offset_get_generic;
1938 hal_soc->ops->hal_rx_mpdu_start_offset_get =
1939 hal_rx_mpdu_start_offset_get_generic;
1940 #ifndef NO_RX_PKT_HDR_TLV
1941 hal_soc->ops->hal_rx_pkt_tlv_offset_get =
1942 hal_rx_pkt_tlv_offset_get_generic;
1943 #endif
1944 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_9224;
1945
1946 hal_soc->ops->hal_rx_flow_get_tuple_info =
1947 hal_rx_flow_get_tuple_info_be;
1948 hal_soc->ops->hal_rx_flow_delete_entry =
1949 hal_rx_flow_delete_entry_be;
1950 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be;
1951 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
1952 hal_compute_reo_remap_ix2_ix3_9224;
1953
1954 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication =
1955 hal_rx_msdu_get_reo_destination_indication_be;
1956 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be;
1957 hal_soc->ops->hal_rx_msdu_is_wlan_mcast =
1958 hal_rx_msdu_is_wlan_mcast_generic_be;
1959 hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_9224;
1960 hal_soc->ops->hal_rx_tlv_decap_format_get =
1961 hal_rx_tlv_decap_format_get_be;
1962 #ifdef RECEIVE_OFFLOAD
1963 hal_soc->ops->hal_rx_tlv_get_offload_info =
1964 hal_rx_tlv_get_offload_info_be;
1965 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be;
1966 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be;
1967 #endif
1968 hal_soc->ops->hal_rx_tlv_msdu_done_get =
1969 hal_rx_tlv_msdu_done_copy_get_9224;
1970 hal_soc->ops->hal_rx_tlv_msdu_len_get =
1971 hal_rx_msdu_start_msdu_len_get_be;
1972 hal_soc->ops->hal_rx_get_frame_ctrl_field =
1973 hal_rx_get_frame_ctrl_field_be;
1974 hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be;
1975 #ifndef CONFIG_WORD_BASED_TLV
1976 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get =
1977 hal_rx_mpdu_info_ampdu_flag_get_be;
1978 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be;
1979 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
1980 hal_rx_hw_desc_get_ppduid_get_be;
1981 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get =
1982 hal_rx_attn_phy_ppdu_id_get_be;
1983 hal_soc->ops->hal_rx_get_filter_category =
1984 hal_rx_get_filter_category_be;
1985 #endif
1986 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be;
1987 hal_soc->ops->hal_rx_tlv_msdu_len_set =
1988 hal_rx_msdu_start_msdu_len_set_be;
1989 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be;
1990 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be;
1991 hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be;
1992 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be;
1993 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be;
1994 hal_soc->ops->hal_rx_tlv_decrypt_err_get =
1995 hal_rx_tlv_decrypt_err_get_be;
1996 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be;
1997 hal_soc->ops->hal_rx_tlv_get_is_decrypted =
1998 hal_rx_tlv_get_is_decrypted_be;
1999 hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be;
2000 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be;
2001 hal_soc->ops->hal_rx_priv_info_set_in_tlv =
2002 hal_rx_priv_info_set_in_tlv_be;
2003 hal_soc->ops->hal_rx_priv_info_get_from_tlv =
2004 hal_rx_priv_info_get_from_tlv_be;
2005 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be;
2006 hal_soc->ops->hal_reo_setup = hal_reo_setup_9224;
2007 hal_soc->ops->hal_reo_config_reo2ppe_dest_info = NULL;
2008 #ifdef REO_SHARED_QREF_TABLE_EN
2009 hal_soc->ops->hal_reo_shared_qaddr_setup = hal_reo_shared_qaddr_setup_be;
2010 hal_soc->ops->hal_reo_shared_qaddr_init = hal_reo_shared_qaddr_init_be;
2011 hal_soc->ops->hal_reo_shared_qaddr_detach = hal_reo_shared_qaddr_detach_be;
2012 hal_soc->ops->hal_reo_shared_qaddr_write = hal_reo_shared_qaddr_write_be;
2013 hal_soc->ops->hal_reo_shared_qaddr_cache_clear = hal_reo_shared_qaddr_cache_clear_be;
2014 #endif
2015 /* Overwrite the default BE ops */
2016 hal_soc->ops->hal_get_rx_max_ba_window =
2017 hal_get_rx_max_ba_window_qcn9224;
2018 hal_soc->ops->hal_get_reo_qdesc_size = hal_qcn9224_get_reo_qdesc_size;
2019 /* TX MONITOR */
2020 #ifdef WLAN_PKT_CAPTURE_TX_2_0
2021 hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv =
2022 hal_txmon_is_mon_buf_addr_tlv_generic_be;
2023 hal_soc->ops->hal_txmon_populate_packet_info =
2024 hal_txmon_populate_packet_info_generic_be;
2025 hal_soc->ops->hal_txmon_status_parse_tlv =
2026 hal_txmon_status_parse_tlv_generic_be;
2027 hal_soc->ops->hal_txmon_status_get_num_users =
2028 hal_txmon_status_get_num_users_generic_be;
2029 #if defined(TX_MONITOR_WORD_MASK)
2030 hal_soc->ops->hal_txmon_get_word_mask =
2031 hal_txmon_get_word_mask_qcn9224;
2032 #else
2033 hal_soc->ops->hal_txmon_get_word_mask =
2034 hal_txmon_get_word_mask_generic_be;
2035 #endif /* TX_MONITOR_WORD_MASK */
2036 #endif /* WLAN_PKT_CAPTURE_TX_2_0 */
2037 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL;
2038 hal_soc->ops->hal_tx_vdev_mismatch_routing_set =
2039 hal_tx_vdev_mismatch_routing_set_generic_be;
2040 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set =
2041 hal_tx_mcast_mlo_reinject_routing_set_generic_be;
2042 hal_soc->ops->hal_get_ba_aging_timeout =
2043 hal_get_ba_aging_timeout_be_generic;
2044 hal_soc->ops->hal_setup_link_idle_list =
2045 hal_setup_link_idle_list_generic_be;
2046 hal_soc->ops->hal_cookie_conversion_reg_cfg_be =
2047 hal_cookie_conversion_reg_cfg_generic_be;
2048 hal_soc->ops->hal_set_ba_aging_timeout =
2049 hal_set_ba_aging_timeout_be_generic;
2050 hal_soc->ops->hal_tx_populate_bank_register =
2051 hal_tx_populate_bank_register_be;
2052 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set =
2053 hal_tx_vdev_mcast_ctrl_set_be;
2054 #ifdef CONFIG_WORD_BASED_TLV
2055 hal_soc->ops->hal_rx_mpdu_start_wmask_get =
2056 hal_rx_mpdu_start_wmask_get_be;
2057 hal_soc->ops->hal_rx_msdu_end_wmask_get =
2058 hal_rx_msdu_end_wmask_get_be;
2059 #endif
2060 hal_soc->ops->hal_get_tsf2_scratch_reg =
2061 hal_get_tsf2_scratch_reg_qcn9224;
2062 hal_soc->ops->hal_get_tqm_scratch_reg =
2063 hal_get_tqm_scratch_reg_qcn9224;
2064 hal_soc->ops->hal_tx_ring_halt_set = hal_tx_ppe2tcl_ring_halt_set_9224;
2065 hal_soc->ops->hal_tx_ring_halt_reset =
2066 hal_tx_ppe2tcl_ring_halt_reset_9224;
2067 hal_soc->ops->hal_tx_ring_halt_poll =
2068 hal_tx_ppe2tcl_ring_halt_done_9224;
2069 hal_soc->ops->hal_tx_get_num_ppe_vp_search_idx_tbl_entries =
2070 hal_tx_get_num_ppe_vp_search_idx_reg_entries_9224;
2071 hal_soc->ops->hal_tx_ring_halt_get = hal_tx_ppe2tcl_ring_halt_get_9224;
2072 };
2073
2074 /**
2075 * hal_srng_hw_reg_offset_init_qcn9224() - Initialize the HW srng reg offset
2076 * applicable only for QCN9224
2077 * @hal_soc: HAL Soc handle
2078 *
2079 * Return: None
2080 */
hal_srng_hw_reg_offset_init_qcn9224(struct hal_soc * hal_soc)2081 static inline void hal_srng_hw_reg_offset_init_qcn9224(struct hal_soc *hal_soc)
2082 {
2083 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset;
2084
2085 hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB),
2086 hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB),
2087 hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA),
2088 hw_reg_offset[DST_PRODUCER_INT2_SETUP] =
2089 REG_OFFSET(DST, PRODUCER_INT2_SETUP);
2090 }
2091