1 /*
2 * Copyright (c) 2021 The Linux Foundation. All rights reserved.
3 * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
16 */
17 #ifndef _HAL_6432_TX_H_
18 #define _HAL_6432_TX_H_
19
20 #include "tcl_data_cmd.h"
21 #include "phyrx_rssi_legacy.h"
22 #include "hal_internal.h"
23 #include "qdf_trace.h"
24 #include "hal_rx.h"
25 #include "hal_tx.h"
26 #include "hal_api_mon.h"
27 #include <hal_be_tx.h>
28
29 #define DSCP_TID_TABLE_SIZE 24
30 #define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4)
31 #define HAL_TX_NUM_DSCP_REGISTER_SIZE 32
32 #define HAL_PPE_VP_ENTRIES_MAX 32
33 #define HAL_PPE_VP_SEARCH_IDX_REG_MAX 8
34
35 /**
36 * hal_tx_get_num_ppe_vp_search_idx_reg_entries_6432() - get number of PPE VP
37 * search index registers
38 * @hal_soc_hdl: HAL SoC handle
39 *
40 * Return: Number of PPE VP search index registers
41 */
42 static uint32_t
hal_tx_get_num_ppe_vp_search_idx_reg_entries_6432(hal_soc_handle_t hal_soc_hdl)43 hal_tx_get_num_ppe_vp_search_idx_reg_entries_6432(hal_soc_handle_t hal_soc_hdl)
44 {
45 return HAL_PPE_VP_SEARCH_IDX_REG_MAX;
46 }
47
48 /**
49 * hal_tx_set_dscp_tid_map_6432() - Configure default DSCP to TID map table
50 * @hal_soc: HAL SoC context
51 * @map: DSCP-TID mapping table
52 * @id: mapping table ID - 0-31
53 *
54 * DSCP are mapped to 8 TID values using TID values programmed
55 * in any of the 32 DSCP_TID_MAPS (id = 0-31).
56 *
57 * Return: none
58 */
hal_tx_set_dscp_tid_map_6432(struct hal_soc * hal_soc,uint8_t * map,uint8_t id)59 static void hal_tx_set_dscp_tid_map_6432(struct hal_soc *hal_soc, uint8_t *map,
60 uint8_t id)
61 {
62 int i;
63 uint32_t addr, cmn_reg_addr;
64 uint32_t value = 0, regval;
65 uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0;
66
67 struct hal_soc *soc = (struct hal_soc *)hal_soc;
68
69 if (id >= HAL_MAX_HW_DSCP_TID_V2_MAPS_6432)
70 return;
71
72 cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
73 MAC_TCL_REG_REG_BASE);
74
75 addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
76 MAC_TCL_REG_REG_BASE,
77 id * NUM_WORDS_PER_DSCP_TID_TABLE);
78
79 /* Enable read/write access */
80 regval = HAL_REG_READ(soc, cmn_reg_addr);
81 regval |=
82 (1 <<
83 HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
84
85 HAL_REG_WRITE(soc, cmn_reg_addr, regval);
86
87 /* Write 8 (24 bits) DSCP-TID mappings in each iteration */
88 for (i = 0; i < 64; i += 8) {
89 value = (map[i] |
90 (map[i + 1] << 0x3) |
91 (map[i + 2] << 0x6) |
92 (map[i + 3] << 0x9) |
93 (map[i + 4] << 0xc) |
94 (map[i + 5] << 0xf) |
95 (map[i + 6] << 0x12) |
96 (map[i + 7] << 0x15));
97
98 qdf_mem_copy(&val[cnt], (void *)&value, 3);
99 cnt += 3;
100 }
101
102 for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) {
103 regval = *(uint32_t *)(val + i);
104 HAL_REG_WRITE(soc, addr,
105 (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
106 addr += 4;
107 }
108
109 /* Disable read/write access */
110 regval = HAL_REG_READ(soc, cmn_reg_addr);
111 regval &=
112 ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
113
114 HAL_REG_WRITE(soc, cmn_reg_addr, regval);
115 }
116
117 /**
118 * hal_tx_update_dscp_tid_6432() - Update the dscp tid map table as updated
119 * by the user
120 * @soc: HAL SoC context
121 * @tid: DSCP-TID mapping table
122 * @id : MAP ID
123 * @dscp: DSCP_TID map index
124 *
125 * Return: void
126 */
hal_tx_update_dscp_tid_6432(struct hal_soc * soc,uint8_t tid,uint8_t id,uint8_t dscp)127 static void hal_tx_update_dscp_tid_6432(struct hal_soc *soc, uint8_t tid,
128 uint8_t id, uint8_t dscp)
129 {
130 uint32_t addr, addr1, cmn_reg_addr;
131 uint32_t start_value = 0, end_value = 0;
132 uint32_t regval;
133 uint8_t end_bits = 0;
134 uint8_t start_bits = 0;
135 uint32_t start_index, end_index;
136
137 cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
138 MAC_TCL_REG_REG_BASE);
139
140 addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
141 MAC_TCL_REG_REG_BASE,
142 id * NUM_WORDS_PER_DSCP_TID_TABLE);
143
144 start_index = dscp * HAL_TX_BITS_PER_TID;
145 end_index = (start_index + (HAL_TX_BITS_PER_TID - 1))
146 % HAL_TX_NUM_DSCP_REGISTER_SIZE;
147 start_index = start_index % HAL_TX_NUM_DSCP_REGISTER_SIZE;
148 addr += (4 * ((dscp * HAL_TX_BITS_PER_TID) /
149 HAL_TX_NUM_DSCP_REGISTER_SIZE));
150
151 if (end_index < start_index) {
152 end_bits = end_index + 1;
153 start_bits = HAL_TX_BITS_PER_TID - end_bits;
154 start_value = tid << start_index;
155 end_value = tid >> start_bits;
156 addr1 = addr + 4;
157 } else {
158 start_bits = HAL_TX_BITS_PER_TID - end_bits;
159 start_value = tid << start_index;
160 addr1 = 0;
161 }
162
163 /* Enable read/write access */
164 regval = HAL_REG_READ(soc, cmn_reg_addr);
165 regval |=
166 (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
167
168 HAL_REG_WRITE(soc, cmn_reg_addr, regval);
169
170 regval = HAL_REG_READ(soc, addr);
171
172 if (end_index < start_index)
173 regval &= (~0) >> start_bits;
174 else
175 regval &= ~(7 << start_index);
176
177 regval |= start_value;
178
179 HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
180
181 if (addr1) {
182 regval = HAL_REG_READ(soc, addr1);
183 regval &= (~0) << end_bits;
184 regval |= end_value;
185
186 HAL_REG_WRITE(soc, addr1, (regval &
187 HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
188 }
189
190 /* Disable read/write access */
191 regval = HAL_REG_READ(soc, cmn_reg_addr);
192 regval &=
193 ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
194 HAL_REG_WRITE(soc, cmn_reg_addr, regval);
195 }
196
197 #ifdef DP_TX_IMPLICIT_RBM_MAPPING
198
199 #define RBM_MAPPING_BMSK HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK
200 #define RBM_MAPPING_SHFT HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT
201
202 #define RBM_TCL_CMD_CREDIT_OFFSET \
203 (HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT >> 2)
204
205 /**
206 * hal_tx_config_rbm_mapping_be_6432() - Update return buffer manager ring id
207 * @hal_soc_hdl: HAL SoC context
208 * @hal_ring_hdl: Source ring pointer
209 * @rbm_id: return buffer manager ring id
210 *
211 * Return: void
212 */
213 static inline void
hal_tx_config_rbm_mapping_be_6432(hal_soc_handle_t hal_soc_hdl,hal_ring_handle_t hal_ring_hdl,uint8_t rbm_id)214 hal_tx_config_rbm_mapping_be_6432(hal_soc_handle_t hal_soc_hdl,
215 hal_ring_handle_t hal_ring_hdl,
216 uint8_t rbm_id)
217 {
218 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
219 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
220 uint32_t reg_addr = 0;
221 uint32_t reg_val = 0;
222 uint32_t val = 0;
223 uint8_t ring_num;
224 enum hal_ring_type ring_type;
225
226 ring_type = srng->ring_type;
227 ring_num = hal_soc->hw_srng_table[ring_type].start_ring_id;
228 ring_num = srng->ring_id - ring_num;
229
230 reg_addr = HWIO_TCL_R0_RBM_MAPPING0_ADDR(MAC_TCL_REG_REG_BASE);
231
232 if (ring_type == PPE2TCL)
233 ring_num = ring_num + RBM_PPE2TCL_OFFSET;
234 else if (ring_type == TCL_CMD_CREDIT)
235 ring_num = ring_num + RBM_TCL_CMD_CREDIT_OFFSET;
236
237 /* get current value stored in register address */
238 val = HAL_REG_READ(hal_soc, reg_addr);
239
240 /* mask out other stored value */
241 val &= (~(RBM_MAPPING_BMSK << (RBM_MAPPING_SHFT * ring_num)));
242
243 reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) <<
244 (RBM_MAPPING_SHFT * ring_num));
245
246 /* write rbm mapped value to register address */
247 HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
248 }
249 #else
250 static inline void
hal_tx_config_rbm_mapping_be_6432(hal_soc_handle_t hal_soc_hdl,hal_ring_handle_t hal_ring_hdl,uint8_t rbm_id)251 hal_tx_config_rbm_mapping_be_6432(hal_soc_handle_t hal_soc_hdl,
252 hal_ring_handle_t hal_ring_hdl,
253 uint8_t rbm_id)
254 {
255 }
256 #endif
257
258 /**
259 * hal_tx_init_cmd_credit_ring_6432() - Initialize command/credit SRNG
260 * @hal_soc_hdl: Handle to HAL SoC structure
261 * @hal_ring_hdl: Handle to HAL SRNG structure
262 *
263 * Return: none
264 */
265 static inline void
hal_tx_init_cmd_credit_ring_6432(hal_soc_handle_t hal_soc_hdl,hal_ring_handle_t hal_ring_hdl)266 hal_tx_init_cmd_credit_ring_6432(hal_soc_handle_t hal_soc_hdl,
267 hal_ring_handle_t hal_ring_hdl)
268 {
269 }
270
271 /* TX MONITOR */
272 #if defined(WLAN_PKT_CAPTURE_TX_2_0) && defined(TX_MONITOR_WORD_MASK)
273
274 #define TX_FES_SETUP_MASK 0x3
275 typedef struct tx_fes_setup_compact_6432 hal_tx_fes_setup_t;
276 struct tx_fes_setup_compact_6432 {
277 /* DWORD - 0 */
278 uint32_t schedule_id;
279 /* DWORD - 1 */
280 uint32_t reserved_1a : 7, // [0: 6]
281 transmit_start_reason : 3, // [7: 9]
282 reserved_1b : 13, // [10: 22]
283 number_of_users : 6, // [28: 23]
284 mu_type : 1, // [29]
285 reserved_1c : 2; // [30]
286 /* DWORD - 2 */
287 uint32_t reserved_2a : 4, // [0: 3]
288 ndp_frame : 2, // [4: 5]
289 txbf : 1, // [6]
290 reserved_2b : 3, // [7: 9]
291 static_bandwidth : 3, // [12: 10]
292 reserved_2c : 1, // [13]
293 transmission_contains_mu_rts : 1, // [14]
294 reserved_2d : 17; // [15: 31]
295 /* DWORD - 3 */
296 uint32_t reserved_3a : 15, // [0: 14]
297 mu_ndp : 1, // [15]
298 reserved_3b : 11, // [16: 26]
299 ndpa : 1, // [27]
300 reserved_3c : 4; // [28: 31]
301 };
302
303 #define TX_PEER_ENTRY_MASK 0x103
304 typedef struct tx_peer_entry_compact_6432 hal_tx_peer_entry_t;
305 struct tx_peer_entry_compact_6432 {
306 /* DWORD - 0 */
307 uint32_t mac_addr_a_31_0 : 32;
308 /* DWORD - 1 */
309 uint32_t mac_addr_a_47_32 : 16,
310 mac_addr_b_15_0 : 16;
311 /* DWORD - 2 */
312 uint32_t mac_addr_b_47_16 : 32;
313 /* DWORD - 3 */
314 uint32_t reserved_3 : 32;
315 /* DWORD - 16 */
316 uint32_t reserved_16 : 32;
317 /* DWORD - 17 */
318 uint32_t multi_link_addr_crypto_enable : 1,
319 reserved_17_a : 15,
320 sw_peer_id : 16;
321 };
322
323 #define TX_QUEUE_EXT_MASK 0x1
324 typedef struct tx_queue_ext_compact_6432 hal_tx_queue_ext_t;
325 struct tx_queue_ext_compact_6432 {
326 /* DWORD - 0 */
327 uint32_t frame_ctl : 16,
328 qos_ctl : 16;
329 /* DWORD - 1 */
330 uint32_t ampdu_flag : 1,
331 reserved_1 : 31;
332 };
333
334 #define TX_MSDU_START_MASK 0x1
335 typedef struct tx_msdu_start_compact_6432 hal_tx_msdu_start_t;
336 struct tx_msdu_start_compact_6432 {
337 /* DWORD - 0 */
338 uint32_t reserved_0 : 32;
339 /* DWORD - 1 */
340 uint32_t reserved_1 : 32;
341 };
342
343 #define TX_MPDU_START_MASK 0x3
344 typedef struct tx_mpdu_start_compact_6432 hal_tx_mpdu_start_t;
345 struct tx_mpdu_start_compact_6432 {
346 /* DWORD - 0 */
347 uint32_t mpdu_length : 14,
348 frame_not_from_tqm : 1,
349 vht_control_present : 1,
350 mpdu_header_length : 8,
351 retry_count : 7,
352 wds : 1;
353 /* DWORD - 1 */
354 uint32_t pn_31_0 : 32;
355 /* DWORD - 2 */
356 uint32_t pn_47_32 : 16,
357 mpdu_sequence_number : 12,
358 raw_already_encrypted : 1,
359 frame_type : 2,
360 txdma_dropped_mpdu_warning : 1;
361 /* DWORD - 3 */
362 uint32_t reserved_3 : 32;
363 };
364
365 typedef struct rxpcu_user_setup_compact_6432 hal_rxpcu_user_setup_t;
366 struct rxpcu_user_setup_compact_6432 {
367 };
368
369 #define TX_FES_STATUS_END_MASK 0x7
370 typedef struct tx_fes_status_end_compact_6432 hal_tx_fes_status_end_t;
371 struct tx_fes_status_end_compact_6432 {
372 /* DWORD - 0 */
373 uint32_t reserved_0 : 32;
374 /* DWORD - 1 */
375 struct {
376 uint16_t phytx_abort_reason : 8,
377 user_number : 6,
378 reserved_1a : 2;
379 } phytx_abort_request_info_details;
380 uint16_t reserved_1b : 12,
381 phytx_abort_request_info_valid : 1,
382 reserved_1c : 3;
383 /* DWORD - 2 */
384 uint32_t start_of_frame_timestamp_15_0 : 16,
385 start_of_frame_timestamp_31_16 : 16;
386 /* DWORD - 3 */
387 uint32_t end_of_frame_timestamp_15_0 : 16,
388 end_of_frame_timestamp_31_16 : 16;
389 /* DWORD - 4 */
390 uint32_t terminate_ranging_sequence : 1,
391 reserved_4a : 7,
392 timing_status : 2,
393 response_type : 5,
394 r2r_end_status_to_follow : 1,
395 transmit_delay : 16;
396 /* DWORD - 5 */
397 uint32_t reserved_5 : 32;
398 };
399
400 #define RESPONSE_END_STATUS_MASK 0xD
401 typedef struct response_end_status_compact_6432 hal_response_end_status_t;
402 struct response_end_status_compact_6432 {
403 /* DWORD - 0 */
404 uint32_t coex_bt_tx_while_wlan_tx : 1,
405 coex_wan_tx_while_wlan_tx : 1,
406 coex_wlan_tx_while_wlan_tx : 1,
407 global_data_underflow_warning : 1,
408 response_transmit_status : 4,
409 phytx_pkt_end_info_valid : 1,
410 phytx_abort_request_info_valid : 1,
411 generated_response : 3,
412 mba_user_count : 7,
413 mba_fake_bitmap_count : 7,
414 coex_based_tx_bw : 3,
415 trig_response_related : 1,
416 dpdtrain_done : 1;
417 /* DWORD - 1 */
418 uint32_t reserved_1 : 32;
419 /* DWORD - 4 */
420 uint32_t reserved_4 : 32;
421 /* DWORD - 5 */
422 uint32_t start_of_frame_timestamp_15_0 : 16,
423 start_of_frame_timestamp_31_16 : 16;
424 /* DWORD - 6 */
425 uint32_t end_of_frame_timestamp_15_0 : 16,
426 end_of_frame_timestamp_31_16 : 16;
427 /* DWORD - 7 */
428 uint32_t reserved_7 : 32;
429 };
430
431 #define TX_FES_STATUS_PROT_MASK 0x2
432 typedef struct tx_fes_status_prot_compact_6432 hal_tx_fes_status_prot_t;
433 struct tx_fes_status_prot_compact_6432 {
434 /* DWORD - 2 */
435 uint32_t start_of_frame_timestamp_15_0 : 16,
436 start_of_frame_timestamp_31_16 : 16;
437 /* DWROD - 3 */
438 uint32_t end_of_frame_timestamp_15_0 : 16,
439 end_of_frame_timestamp_31_16 : 16;
440 };
441
442 #define PCU_PPDU_SETUP_INIT_MASK 0x1E800000
443 typedef struct pcu_ppdu_setup_init_compact_6432 hal_pcu_ppdu_setup_t;
444 struct pcu_ppdu_setup_init_compact_6432 {
445 /* DWORD - 46 */
446 uint32_t reserved_46 : 32;
447 /* DWORD - 47 */
448 uint32_t r2r_group_id : 6,
449 r2r_response_frame_type : 4,
450 r2r_sta_partial_aid : 11,
451 use_address_fields_for_protection : 1,
452 r2r_set_required_response_time : 1,
453 reserved_47 : 9;
454 /* DWORD - 50 */
455 uint32_t reserved_50 : 32;
456 /* DWORD - 51 */
457 uint32_t protection_frame_ad1_31_0 : 32;
458 /* DWORD - 52 */
459 uint32_t protection_frame_ad1_47_32 : 16,
460 protection_frame_ad2_15_0 : 16;
461 /* DWORD - 53 */
462 uint32_t protection_frame_ad2_47_16 : 32;
463 /* DWORD - 54 */
464 uint32_t reserved_54 : 32;
465 /* DWORD - 55 */
466 uint32_t protection_frame_ad3_31_0 : 32;
467 /* DWORD - 56 */
468 uint32_t protection_frame_ad3_47_32 : 16,
469 protection_frame_ad4_15_0 : 16;
470 /* DWORD - 57 */
471 uint32_t protection_frame_ad4_47_16 : 32;
472 };
473
474 /**
475 * hal_txmon_get_word_mask_qcn6432() - api to get word mask for tx monitor
476 * @wmask: pointer to hal_txmon_word_mask_config_t
477 *
478 * Return: void
479 */
480 static inline
hal_txmon_get_word_mask_qcn6432(void * wmask)481 void hal_txmon_get_word_mask_qcn6432(void *wmask)
482 {
483 hal_txmon_word_mask_config_t *word_mask = NULL;
484
485 word_mask = (hal_txmon_word_mask_config_t *)wmask;
486
487 word_mask->compaction_enable = 1;
488 word_mask->tx_fes_setup = TX_FES_SETUP_MASK;
489 word_mask->tx_peer_entry = TX_PEER_ENTRY_MASK;
490 word_mask->tx_queue_ext = TX_QUEUE_EXT_MASK;
491 word_mask->tx_msdu_start = TX_MSDU_START_MASK;
492 word_mask->pcu_ppdu_setup_init = PCU_PPDU_SETUP_INIT_MASK;
493 word_mask->tx_mpdu_start = TX_MPDU_START_MASK;
494 word_mask->rxpcu_user_setup = 0xFF;
495 word_mask->tx_fes_status_end = TX_FES_STATUS_END_MASK;
496 word_mask->response_end_status = RESPONSE_END_STATUS_MASK;
497 word_mask->tx_fes_status_prot = TX_FES_STATUS_PROT_MASK;
498 }
499 #endif
500
501 /**
502 * hal_tx_set_ppe_cmn_config_6432() - Set the PPE common config register
503 * @hal_soc_hdl: HAL SoC handle
504 * @cmn_cfg: Common PPE config
505 *
506 * Based on the PPE2TCL descriptor below errors, if the below register
507 * values are set then the packets are forward to Tx rule handler if 1'0b
508 * or to TCL exit base if 1'1b.
509 *
510 * Return: void
511 */
512 static inline
hal_tx_set_ppe_cmn_config_6432(hal_soc_handle_t hal_soc_hdl,union hal_tx_cmn_config_ppe * cmn_cfg)513 void hal_tx_set_ppe_cmn_config_6432(hal_soc_handle_t hal_soc_hdl,
514 union hal_tx_cmn_config_ppe *cmn_cfg)
515 {
516 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
517 union hal_tx_cmn_config_ppe *cfg =
518 (union hal_tx_cmn_config_ppe *)cmn_cfg;
519 uint32_t reg_addr, reg_val = 0;
520
521 reg_addr = HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(MAC_TCL_REG_REG_BASE);
522
523 reg_val = HAL_REG_READ(soc, reg_addr);
524
525 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK;
526 reg_val |=
527 (cfg->drop_prec_err &
528 HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK) <<
529 HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_SHFT;
530
531 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK;
532 reg_val |=
533 (cfg->fake_mac_hdr &
534 HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK) <<
535 HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_SHFT;
536
537 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK;
538 reg_val |=
539 (cfg->cpu_code_inv &
540 HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK) <<
541 HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_SHFT;
542
543 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK;
544 reg_val |=
545 (cfg->l3_l4_err &
546 HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK) <<
547 HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_SHFT;
548
549 HAL_REG_WRITE(soc, reg_addr, reg_val);
550 }
551
552 /**
553 * hal_tx_set_ppe_vp_entry_6432() - Set the PPE VP entry
554 * @hal_soc_hdl: HAL SoC handle
555 * @cfg: PPE VP config
556 * @ppe_vp_idx: PPE VP index to the table
557 *
558 * Return: void
559 */
560 static inline
hal_tx_set_ppe_vp_entry_6432(hal_soc_handle_t hal_soc_hdl,union hal_tx_ppe_vp_config * cfg,int ppe_vp_idx)561 void hal_tx_set_ppe_vp_entry_6432(hal_soc_handle_t hal_soc_hdl,
562 union hal_tx_ppe_vp_config *cfg,
563 int ppe_vp_idx)
564 {
565 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
566 uint32_t reg_addr;
567
568 reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE,
569 ppe_vp_idx);
570
571 HAL_REG_WRITE(soc, reg_addr, cfg->val);
572 }
573
574 /**
575 * hal_ppeds_cfg_ast_override_map_reg_6432() - Set the PPE index mapping table
576 * @hal_soc_hdl: HAL SoC context
577 * @idx: index into the table
578 * @idx_map: HAL PPE INDESX MAPPING config
579 *
580 * Return: void
581 */
582 static inline void
hal_ppeds_cfg_ast_override_map_reg_6432(hal_soc_handle_t hal_soc_hdl,uint8_t idx,union hal_tx_ppe_idx_map_config * idx_map)583 hal_ppeds_cfg_ast_override_map_reg_6432(hal_soc_handle_t hal_soc_hdl,
584 uint8_t idx,
585 union hal_tx_ppe_idx_map_config *idx_map)
586 {
587 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
588 uint32_t reg_addr;
589
590 reg_addr =
591 HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE,
592 idx);
593
594 HAL_REG_WRITE(soc, reg_addr, idx_map->val);
595 }
596
597 /**
598 * hal_tx_set_ppe_pri2tid_map_6432()
599 * @hal_soc_hdl: HAL SoC handle
600 * @val : PRI to TID value
601 * @map_no: Map number
602 *
603 * Return: void
604 */
605 static inline
hal_tx_set_ppe_pri2tid_map_6432(hal_soc_handle_t hal_soc_hdl,uint32_t val,uint8_t map_no)606 void hal_tx_set_ppe_pri2tid_map_6432(hal_soc_handle_t hal_soc_hdl,
607 uint32_t val, uint8_t map_no)
608 {
609 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
610 uint32_t reg_addr, reg_val = 0;
611
612 if (map_no == 0)
613 reg_addr =
614 HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE);
615 else
616 reg_addr =
617 HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE);
618
619 reg_val |= val;
620 HAL_REG_WRITE(soc, reg_addr, reg_val);
621 }
622
623 /**
624 * hal_tx_enable_pri2tid_map_6432()
625 * @hal_soc_hdl: HAL SoC handle
626 * @val : PRI to TID value
627 * @ppe_vp_idx: Map number
628 *
629 * Return: void
630 */
631
632 static inline
hal_tx_enable_pri2tid_map_6432(hal_soc_handle_t hal_soc_hdl,bool val,uint8_t ppe_vp_idx)633 void hal_tx_enable_pri2tid_map_6432(hal_soc_handle_t hal_soc_hdl,
634 bool val, uint8_t ppe_vp_idx)
635 {
636 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
637 uint32_t reg_addr, reg_val = 0;
638
639 reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE,
640 ppe_vp_idx);
641
642 /*
643 * Drop precedence is enabled by default.
644 */
645 reg_val = HAL_REG_READ(soc, reg_addr);
646
647 reg_val &=
648 ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK;
649
650 reg_val |=
651 (val &
652 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK) <<
653 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_SHFT;
654
655 HAL_REG_WRITE(soc, reg_addr, reg_val);
656 }
657
658 /**
659 * hal_tx_update_ppe_pri2tid_6432()
660 * @hal_soc_hdl: HAL SoC handle
661 * @pri: INT_PRI
662 * @tid: Wi-Fi TID
663 *
664 * Return: void
665 */
666
667 static inline
hal_tx_update_ppe_pri2tid_6432(hal_soc_handle_t hal_soc_hdl,uint8_t pri,uint8_t tid)668 void hal_tx_update_ppe_pri2tid_6432(hal_soc_handle_t hal_soc_hdl,
669 uint8_t pri, uint8_t tid)
670 {
671 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
672 uint32_t reg_addr, reg_val = 0, mask, shift;
673
674 /*
675 * INT_PRI 0..9 is in MAP0 register and INT_PRI 10..15
676 * is in MAP1 register.
677 */
678 switch (pri) {
679 case 0 ... 9:
680 reg_addr =
681 HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE);
682 mask =
683 (HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_BMSK << (0x3 * pri));
684 shift = HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_SHFT + (pri * 0x3);
685 break;
686 case 10 ... 15:
687 pri = pri - 10;
688 reg_addr =
689 HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE);
690 mask =
691 (HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_BMSK << (0x3 * pri));
692 shift =
693 HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_SHFT + (pri * 0x3);
694 break;
695 default:
696 return;
697 }
698
699 reg_val = HAL_REG_READ(soc, reg_addr);
700 reg_val &= ~mask;
701 reg_val |= (pri << shift) & mask;
702
703 HAL_REG_WRITE(soc, reg_addr, reg_val);
704 }
705
706 /*
707 * hal_tx_dump_ppe_vp_entry_6432()
708 * @hal_soc_hdl: HAL SoC handle
709 *
710 * Return: void
711 */
712 static inline
hal_tx_dump_ppe_vp_entry_6432(hal_soc_handle_t hal_soc_hdl)713 void hal_tx_dump_ppe_vp_entry_6432(hal_soc_handle_t hal_soc_hdl)
714 {
715 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
716 uint32_t reg_addr, reg_val = 0, i;
717
718 for (i = 0; i < HAL_PPE_VP_ENTRIES_MAX; i++) {
719 reg_addr =
720 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(
721 MAC_TCL_REG_REG_BASE,
722 i);
723 reg_val = HAL_REG_READ(soc, reg_addr);
724 hal_verbose_debug("%d: 0x%x\n", i, reg_val);
725 }
726 }
727
728 /*
729 * hal_tx_get_num_ppe_vp_tbl_entries_6432()
730 * @hal_soc_hdl: HAL SoC handle
731 *
732 * Return: Number of PPE VP entries
733 */
734 static
hal_tx_get_num_ppe_vp_tbl_entries_6432(hal_soc_handle_t hal_soc_hdl)735 uint32_t hal_tx_get_num_ppe_vp_tbl_entries_6432(hal_soc_handle_t hal_soc_hdl)
736 {
737 return HAL_PPE_VP_ENTRIES_MAX;
738 }
739
740 /**
741 * hal_tx_ppe2tcl_ring_halt_set_6432() - Enable ring halt for the ppe2tcl ring
742 * @hal_soc: HAL SoC context
743 *
744 * Return: none
745 */
hal_tx_ppe2tcl_ring_halt_set_6432(hal_soc_handle_t hal_soc)746 static void hal_tx_ppe2tcl_ring_halt_set_6432(hal_soc_handle_t hal_soc)
747 {
748 uint32_t cmn_reg_addr;
749 uint32_t regval;
750 struct hal_soc *soc = (struct hal_soc *)hal_soc;
751
752 cmn_reg_addr =
753 HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(MAC_TCL_REG_REG_BASE);
754
755 /* Enable RING_HALT */
756 regval = HAL_REG_READ(soc, cmn_reg_addr);
757 regval |=
758 (1 <<
759 HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_SHFT);
760
761 HAL_REG_WRITE(soc, cmn_reg_addr, regval);
762 }
763
764 /**
765 * hal_tx_ppe2tcl_ring_halt_reset_6432() - Disable ring halt for the ppe2tcl ring
766 * @hal_soc: HAL SoC context
767 *
768 * Return: none
769 */
hal_tx_ppe2tcl_ring_halt_reset_6432(hal_soc_handle_t hal_soc)770 static void hal_tx_ppe2tcl_ring_halt_reset_6432(hal_soc_handle_t hal_soc)
771 {
772 uint32_t cmn_reg_addr;
773 uint32_t regval;
774 struct hal_soc *soc = (struct hal_soc *)hal_soc;
775
776 cmn_reg_addr =
777 HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(MAC_TCL_REG_REG_BASE);
778
779 /* Disable RING_HALT */
780 regval = HAL_REG_READ(soc, cmn_reg_addr);
781 regval &= ~(1 <<
782 HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_SHFT);
783
784 HAL_REG_WRITE(soc, cmn_reg_addr, regval);
785 }
786
787 /**
788 * hal_tx_ppe2tcl_ring_halt_done_6432() - Check if ring halt is done for ppe2tcl ring
789 * @hal_soc: HAL SoC context
790 *
791 * Return: true if halt done
792 */
hal_tx_ppe2tcl_ring_halt_done_6432(hal_soc_handle_t hal_soc)793 static bool hal_tx_ppe2tcl_ring_halt_done_6432(hal_soc_handle_t hal_soc)
794 {
795 uint32_t cmn_reg_addr;
796 uint32_t regval;
797 struct hal_soc *soc = (struct hal_soc *)hal_soc;
798
799 cmn_reg_addr =
800 HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(MAC_TCL_REG_REG_BASE);
801
802 regval = HAL_REG_READ(soc, cmn_reg_addr);
803 regval &= (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_STAT_SHFT);
804
805 return(!!regval);
806 }
807
808 #endif /* _HAL_6432_TX_H_ */
809