1 /*
2  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #include "hal_hw_headers.h"
18 #include "hal_internal.h"
19 #include "cdp_txrx_mon_struct.h"
20 #include "qdf_trace.h"
21 #include "sw_monitor_ring.h"
22 #include "hal_rx.h"
23 #include "hal_api_mon.h"
24 
25 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va)      \
26 	((uint8_t *)(link_desc_va) +			\
27 	RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET)
28 
29 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0)			\
30 	((uint8_t *)(msdu0) +				\
31 	RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)
32 
33 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc)		\
34 	((uint8_t *)(ent_ring_desc) +			\
35 	RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET)
36 
37 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc)		\
38 	((uint8_t *)(dst_ring_desc) +			\
39 	REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET)
40 
41 #define HAL_RX_GET_FC_VALID(rx_mpdu_start)	\
42 	HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MPDU_FRAME_CONTROL_VALID)
43 
44 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start)	\
45 	HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, TO_DS)
46 
47 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \
48 	HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD1_VALID)
49 
50 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \
51 	HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD2_VALID)
52 
53 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \
54 	HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, RXPCU_MPDU_FILTER_IN_CATEGORY)
55 
56 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start)	\
57 	HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, PHY_PPDU_ID)
58 
59 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start)	\
60 	HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, SW_FRAME_GROUP_ID)
61 
62 #define HAL_RX_GET_SW_PEER_ID(rx_mpdu_start)	\
63 	HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_10, SW_PEER_ID)
64 
65 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params)		\
66 	do { \
67 		(reg_val) &= \
68 			~(HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | \
69 			HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \
70 		(reg_val) |= \
71 			HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
72 			       AGING_LIST_ENABLE, 1) |\
73 			HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
74 			       AGING_FLUSH_ENABLE, 1);\
75 		HAL_REG_WRITE((soc), \
76 			      HWIO_REO_R0_GENERAL_ENABLE_ADDR( \
77 			      SEQ_WCSS_UMAC_REO_REG_OFFSET), \
78 			      (reg_val)); \
79 		(reg_val) = \
80 			HAL_REG_READ((soc), \
81 				     HWIO_REO_R0_MISC_CTL_ADDR(	\
82 				     SEQ_WCSS_UMAC_REO_REG_OFFSET)); \
83 		(reg_val) &= \
84 			~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \
85 		(reg_val) |= \
86 			HAL_SM(HWIO_REO_R0_MISC_CTL,	\
87 			       FRAGMENT_DEST_RING, \
88 			       (reo_params)->frag_dst_ring); \
89 		HAL_REG_WRITE((soc), \
90 			      HWIO_REO_R0_MISC_CTL_ADDR( \
91 			      SEQ_WCSS_UMAC_REO_REG_OFFSET), \
92 			      (reg_val)); \
93 		(reg_val) = \
94 		HAL_REG_READ((soc), \
95 		     HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(	\
96 			     SEQ_WCSS_UMAC_REO_REG_OFFSET)); \
97 		(reg_val) &= \
98 			~(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK); \
99 		(reg_val) |= \
100 			HAL_SM(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0, \
101 			       DEST_RING_ALT_MAPPING_0, \
102 			       (reo_params)->alt_dst_ind_0); \
103 		HAL_REG_WRITE((soc), \
104 			      HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR( \
105 			      SEQ_WCSS_UMAC_REO_REG_OFFSET), \
106 			      (reg_val)); \
107 	} while (0)
108 
109 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \
110 	((struct rx_msdu_desc_info *) \
111 	_OFFSET_TO_BYTE_PTR((msdu_details_ptr), \
112 	UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET))
113 
114 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc)   \
115 	((struct rx_msdu_details *) \
116 	 _OFFSET_TO_BYTE_PTR((link_desc),\
117 	UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET))
118 
119 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \
120 	(_HAL_MS( \
121 		 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
122 			 msdu_end_tlv.rx_msdu_end), \
123 			 RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET)), \
124 		RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK, \
125 		RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB))
126 
127 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end)	\
128 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end,	\
129 		RX_MSDU_END_10_FIRST_MSDU_OFFSET)),	\
130 		RX_MSDU_END_10_FIRST_MSDU_MASK,		\
131 		RX_MSDU_END_10_FIRST_MSDU_LSB))
132 
133 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end)	\
134 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end,	\
135 		RX_MSDU_END_10_LAST_MSDU_OFFSET)),	\
136 		RX_MSDU_END_10_LAST_MSDU_MASK,		\
137 		RX_MSDU_END_10_LAST_MSDU_LSB))
138 
139 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end)	\
140 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end,	\
141 		RX_MSDU_END_10_SA_IS_VALID_OFFSET)),	\
142 		RX_MSDU_END_10_SA_IS_VALID_MASK,		\
143 		RX_MSDU_END_10_SA_IS_VALID_LSB))
144 
145 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end)	\
146 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end,	\
147 		RX_MSDU_END_10_DA_IS_VALID_OFFSET)),	\
148 		RX_MSDU_END_10_DA_IS_VALID_MASK,		\
149 		RX_MSDU_END_10_DA_IS_VALID_LSB))
150 
151 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end)	\
152 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end,	\
153 		RX_MSDU_END_10_DA_IS_MCBC_OFFSET)),	\
154 		RX_MSDU_END_10_DA_IS_MCBC_MASK,		\
155 		RX_MSDU_END_10_DA_IS_MCBC_LSB))
156 
157 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end)	\
158 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end,		\
159 		RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET)),	\
160 		RX_MSDU_END_10_L3_HEADER_PADDING_MASK,		\
161 		RX_MSDU_END_10_L3_HEADER_PADDING_LSB))
162 
163 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end)	\
164 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end,	\
165 		RX_MSDU_END_11_SA_IDX_OFFSET)),	\
166 		RX_MSDU_END_11_SA_IDX_MASK,		\
167 		RX_MSDU_END_11_SA_IDX_LSB))
168 
169 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end)		\
170 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end,		\
171 		RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET)),		\
172 		RX_MSDU_END_14_SA_SW_PEER_ID_MASK,		\
173 		RX_MSDU_END_14_SA_SW_PEER_ID_LSB))
174 
175 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end)	\
176 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end,	\
177 		RX_MSDU_END_14_CCE_METADATA_OFFSET)),	\
178 		RX_MSDU_END_14_CCE_METADATA_MASK,	\
179 		RX_MSDU_END_14_CCE_METADATA_LSB))
180 
181 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end)		\
182 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end,		\
183 		RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET)),	\
184 		RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK,	\
185 		RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB))
186 
187 #define HAL_RX_MPDU_SW_FRAME_GROUP_ID_GET(_rx_mpdu_info) \
188 	(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info),  \
189 	RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)),       \
190 	RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK,           \
191 	RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB))           \
192 
193 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \
194 	(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info),	\
195 		RX_MPDU_INFO_10_SW_PEER_ID_OFFSET)),	\
196 		RX_MPDU_INFO_10_SW_PEER_ID_MASK,		\
197 		RX_MPDU_INFO_10_SW_PEER_ID_LSB))
198 
199 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info)	\
200 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info,	\
201 		RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET)),	\
202 		RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK,	\
203 		RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB))
204 
205 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \
206 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
207 		RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET)), \
208 		RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK,	\
209 		RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB))
210 
211 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info)	\
212 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
213 		RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \
214 		RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK,	\
215 		RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB))
216 
217 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info)	\
218 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
219 		RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \
220 		RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK,	\
221 		RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB))
222 
223 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \
224 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
225 		RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET)), \
226 		RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK,	\
227 		RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB))
228 
229 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info)	\
230 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
231 		RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \
232 		RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK,	\
233 		RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB))
234 
235 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info)	\
236 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
237 		RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \
238 		RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK,	\
239 		RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB))
240 
241 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \
242 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
243 		RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET)), \
244 		RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK,	\
245 		RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB))
246 
247 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info)	\
248 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
249 		RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \
250 		RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK,	\
251 		RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB))
252 
253 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info)	\
254 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
255 		RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \
256 		RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK,	\
257 		RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB))
258 
259 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \
260 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
261 		RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET)), \
262 		RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK,	\
263 		RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB))
264 
265 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info)	\
266 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
267 		RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \
268 		RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK,	\
269 		RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB))
270 
271 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info)	\
272 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
273 		RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \
274 		RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK,	\
275 		RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB))
276 
277 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info)	\
278 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info,	\
279 		RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)),	\
280 		RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK,	\
281 		RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB))
282 
283 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \
284 	(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info),		\
285 		RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)),	\
286 		RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK,	\
287 		RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB))
288 
289 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info)	\
290 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info,		\
291 	RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET)),	\
292 	RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK,	\
293 	RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB))
294 
295 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info)	\
296 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info,	\
297 		RX_MPDU_INFO_11_FR_DS_OFFSET)),	\
298 		RX_MPDU_INFO_11_FR_DS_MASK,	\
299 		RX_MPDU_INFO_11_FR_DS_LSB))
300 
301 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info)	\
302 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info,	\
303 		RX_MPDU_INFO_11_TO_DS_OFFSET)),	\
304 		RX_MPDU_INFO_11_TO_DS_MASK,	\
305 		RX_MPDU_INFO_11_TO_DS_LSB))
306 
307 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info)	\
308 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info,	\
309 		RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET)),	\
310 		RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK,	\
311 		RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB))
312 
313 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info)		\
314 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info,	\
315 	RX_MPDU_INFO_3_PN_31_0_OFFSET)),		\
316 	RX_MPDU_INFO_3_PN_31_0_MASK,			\
317 	RX_MPDU_INFO_3_PN_31_0_LSB))
318 
319 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info)		\
320 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info,	\
321 	RX_MPDU_INFO_4_PN_63_32_OFFSET)),		\
322 	RX_MPDU_INFO_4_PN_63_32_MASK,			\
323 	RX_MPDU_INFO_4_PN_63_32_LSB))
324 
325 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info)		\
326 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info,	\
327 	RX_MPDU_INFO_5_PN_95_64_OFFSET)),		\
328 	RX_MPDU_INFO_5_PN_95_64_MASK,			\
329 	RX_MPDU_INFO_5_PN_95_64_LSB))
330 
331 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info)	\
332 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info,	\
333 	RX_MPDU_INFO_6_PN_127_96_OFFSET)),		\
334 	RX_MPDU_INFO_6_PN_127_96_MASK,			\
335 	RX_MPDU_INFO_6_PN_127_96_LSB))
336 
337 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end)  \
338 		(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end,  \
339 		RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET)),  \
340 		RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK,    \
341 		RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB))
342 
343 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end)  \
344 		(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end,  \
345 		RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET)),  \
346 		RX_MSDU_END_10_FLOW_IDX_INVALID_MASK,    \
347 		RX_MSDU_END_10_FLOW_IDX_INVALID_LSB))
348 
349 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end)  \
350 		(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end,  \
351 		RX_MSDU_END_12_FLOW_IDX_OFFSET)),  \
352 		RX_MSDU_END_12_FLOW_IDX_MASK,    \
353 		RX_MSDU_END_12_FLOW_IDX_LSB))
354 
355 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end)  \
356 		(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end,  \
357 		RX_MSDU_END_13_FSE_METADATA_OFFSET)),	\
358 		RX_MSDU_END_13_FSE_METADATA_MASK,    \
359 		RX_MSDU_END_13_FSE_METADATA_LSB))
360 
361 #define HAL_RX_MPDU_GET_PHY_PPDU_ID(_rx_mpdu_info)	\
362 	(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info),	\
363 	RX_MPDU_INFO_9_PHY_PPDU_ID_OFFSET)),		\
364 	RX_MPDU_INFO_9_PHY_PPDU_ID_MASK,		\
365 	RX_MPDU_INFO_9_PHY_PPDU_ID_LSB))		\
366 
367 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
368 	(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
369 	RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)),	\
370 	RX_MSDU_START_5_MIMO_SS_BITMAP_MASK,		\
371 	RX_MSDU_START_5_MIMO_SS_BITMAP_LSB))
372 
373 #ifdef GET_MSDU_AGGREGATION
374 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\
375 {\
376 	struct rx_msdu_end *rx_msdu_end;\
377 	bool first_msdu, last_msdu; \
378 	rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\
379 	first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_10, FIRST_MSDU);\
380 	last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_10, LAST_MSDU);\
381 	if (first_msdu && last_msdu)\
382 		rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\
383 	else\
384 		rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \
385 } \
386 
387 #else
388 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)
389 #endif
390 
391 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \
392 	(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info),	\
393 		RX_MPDU_INFO_7_TID_OFFSET)),		\
394 		RX_MPDU_INFO_7_TID_MASK,		\
395 		RX_MPDU_INFO_7_TID_LSB))
396 
397 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start)	\
398 	(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),	\
399 	RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)),		\
400 	RX_MSDU_START_5_RECEPTION_TYPE_MASK,			\
401 	RX_MSDU_START_5_RECEPTION_TYPE_LSB))
402