1 /*
2 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for
6 * any purpose with or without fee is hereby granted, provided that the
7 * above copyright notice and this permission notice appear in all
8 * copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17 * PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #include "qdf_types.h"
21 #include "qdf_util.h"
22 #include "qdf_types.h"
23 #include "qdf_lock.h"
24 #include "qdf_mem.h"
25 #include "qdf_nbuf.h"
26 #include "hal_li_hw_headers.h"
27 #include "hal_internal.h"
28 #include "hal_api.h"
29 #include "target_type.h"
30 #include "wcss_version.h"
31 #include "qdf_module.h"
32 #include "hal_flow.h"
33 #include "rx_flow_search_entry.h"
34 #include "hal_rx_flow_info.h"
35
36 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
37 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET
38 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
39 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK
40 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \
41 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB
42 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET \
43 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET
44 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK \
45 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK
46 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB \
47 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB
48 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \
49 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET
50 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \
51 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET
52 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \
53 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET
54 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \
55 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET
56 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \
57 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET
58 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \
59 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET
60 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \
61 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET
62 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \
63 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET
64 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \
65 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET
66
67 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \
68 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET
69 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \
70 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET
71 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
72 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET
73 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
74 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
75 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
76 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
77 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
78 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
79 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
80 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
81 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
82 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER
83 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
84 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
85 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
86 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
87 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
88 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET
89 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
90 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET
91 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
92 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET
93 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
94 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB
95 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
96 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK
97 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
98 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB
99 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
100 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK
101 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
102 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB
103 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
104 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK
105 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
106 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB
107 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
108 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK
109 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
110 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB
111 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
112 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK
113 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
114 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK
115 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
116 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET
117 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
118 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB
119
120 #include "hal_6750_tx.h"
121 #include "hal_6750_rx.h"
122 #include <hal_generic_api.h>
123 #include "hal_li_rx.h"
124 #include "hal_li_api.h"
125 #include "hal_li_generic_api.h"
126
127 /**
128 * hal_rx_msdu_start_nss_get_6750() - API to get the NSS Interval from
129 * rx_msdu_start
130 * @buf: pointer to the start of RX PKT TLV header
131 *
132 * Return: uint32_t(nss)
133 */
134 static uint32_t
hal_rx_msdu_start_nss_get_6750(uint8_t * buf)135 hal_rx_msdu_start_nss_get_6750(uint8_t *buf)
136 {
137 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
138 struct rx_msdu_start *msdu_start =
139 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
140 uint8_t mimo_ss_bitmap;
141
142 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start);
143
144 return qdf_get_hweight8(mimo_ss_bitmap);
145 }
146
147 /**
148 * hal_rx_msdu_start_get_len_6750() - API to get the MSDU length from
149 * rx_msdu_start TLV
150 * @buf: pointer to the start of RX PKT TLV headers
151 *
152 * Return: (uint32_t)msdu length
153 */
hal_rx_msdu_start_get_len_6750(uint8_t * buf)154 static uint32_t hal_rx_msdu_start_get_len_6750(uint8_t *buf)
155 {
156 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
157 struct rx_msdu_start *msdu_start =
158 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
159 uint32_t msdu_len;
160
161 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start);
162
163 return msdu_len;
164 }
165
166 /**
167 * hal_rx_mon_hw_desc_get_mpdu_status_6750() - Retrieve MPDU status
168 * @hw_desc_addr: Start address of Rx HW TLVs
169 * @rs: Status for monitor mode
170 *
171 * Return: void
172 */
hal_rx_mon_hw_desc_get_mpdu_status_6750(void * hw_desc_addr,struct mon_rx_status * rs)173 static void hal_rx_mon_hw_desc_get_mpdu_status_6750(void *hw_desc_addr,
174 struct mon_rx_status *rs)
175 {
176 struct rx_msdu_start *rx_msdu_start;
177 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
178 uint32_t reg_value;
179 const uint32_t sgi_hw_to_cdp[] = {
180 CDP_SGI_0_8_US,
181 CDP_SGI_0_4_US,
182 CDP_SGI_1_6_US,
183 CDP_SGI_3_2_US,
184 };
185
186 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
187
188 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs);
189
190 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start,
191 RX_MSDU_START_5, USER_RSSI);
192 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC);
193
194 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI);
195 rs->sgi = sgi_hw_to_cdp[reg_value];
196
197 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE);
198 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0;
199 /* TODO: rs->beamformed should be set for SU beamforming also */
200 }
201
202 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
203
hal_get_link_desc_size_6750(void)204 static uint32_t hal_get_link_desc_size_6750(void)
205 {
206 return LINK_DESC_SIZE;
207 }
208
209 /**
210 * hal_rx_get_tlv_6750() - API to get the tlv
211 * @rx_tlv: TLV data extracted from the rx packet
212 *
213 * Return: uint8_t
214 */
hal_rx_get_tlv_6750(void * rx_tlv)215 static uint8_t hal_rx_get_tlv_6750(void *rx_tlv)
216 {
217 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH);
218 }
219
220 /**
221 * hal_rx_proc_phyrx_other_receive_info_tlv_6750()
222 * - process other receive info TLV
223 * @rx_tlv_hdr: pointer to TLV header
224 * @ppdu_info_handle: pointer to ppdu_info
225 *
226 * Return: None
227 */
228 static
hal_rx_proc_phyrx_other_receive_info_tlv_6750(void * rx_tlv_hdr,void * ppdu_info_handle)229 void hal_rx_proc_phyrx_other_receive_info_tlv_6750(void *rx_tlv_hdr,
230 void *ppdu_info_handle)
231 {
232 uint32_t tlv_tag, tlv_len;
233 uint32_t temp_len, other_tlv_len, other_tlv_tag;
234 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
235 void *other_tlv_hdr = NULL;
236 void *other_tlv = NULL;
237
238 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
239 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
240 temp_len = 0;
241
242 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE;
243
244 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr);
245 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr);
246 temp_len += other_tlv_len;
247 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
248
249 switch (other_tlv_tag) {
250 default:
251 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
252 "%s unhandled TLV type: %d, TLV len:%d",
253 __func__, other_tlv_tag, other_tlv_len);
254 break;
255 }
256 }
257
258 /**
259 * hal_rx_dump_msdu_start_tlv_6750() - dump RX msdu_start TLV in structured
260 * human readable format.
261 * @pkttlvs: pointer to the pkttlvs.
262 * @dbg_level: log level.
263 *
264 * Return: void
265 */
hal_rx_dump_msdu_start_tlv_6750(void * pkttlvs,uint8_t dbg_level)266 static void hal_rx_dump_msdu_start_tlv_6750(void *pkttlvs, uint8_t dbg_level)
267 {
268 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
269 struct rx_msdu_start *msdu_start =
270 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
271
272 hal_verbose_debug(
273 "rx_msdu_start tlv (1/2) - "
274 "rxpcu_mpdu_filter_in_category: %x "
275 "sw_frame_group_id: %x "
276 "phy_ppdu_id: %x "
277 "msdu_length: %x "
278 "ipsec_esp: %x "
279 "l3_offset: %x "
280 "ipsec_ah: %x "
281 "l4_offset: %x "
282 "msdu_number: %x "
283 "decap_format: %x "
284 "ipv4_proto: %x "
285 "ipv6_proto: %x "
286 "tcp_proto: %x "
287 "udp_proto: %x "
288 "ip_frag: %x "
289 "tcp_only_ack: %x "
290 "da_is_bcast_mcast: %x "
291 "ip4_protocol_ip6_next_header: %x "
292 "toeplitz_hash_2_or_4: %x "
293 "flow_id_toeplitz: %x "
294 "user_rssi: %x "
295 "pkt_type: %x "
296 "stbc: %x "
297 "sgi: %x "
298 "rate_mcs: %x "
299 "receive_bandwidth: %x "
300 "reception_type: %x "
301 "ppdu_start_timestamp: %u ",
302 msdu_start->rxpcu_mpdu_filter_in_category,
303 msdu_start->sw_frame_group_id,
304 msdu_start->phy_ppdu_id,
305 msdu_start->msdu_length,
306 msdu_start->ipsec_esp,
307 msdu_start->l3_offset,
308 msdu_start->ipsec_ah,
309 msdu_start->l4_offset,
310 msdu_start->msdu_number,
311 msdu_start->decap_format,
312 msdu_start->ipv4_proto,
313 msdu_start->ipv6_proto,
314 msdu_start->tcp_proto,
315 msdu_start->udp_proto,
316 msdu_start->ip_frag,
317 msdu_start->tcp_only_ack,
318 msdu_start->da_is_bcast_mcast,
319 msdu_start->ip4_protocol_ip6_next_header,
320 msdu_start->toeplitz_hash_2_or_4,
321 msdu_start->flow_id_toeplitz,
322 msdu_start->user_rssi,
323 msdu_start->pkt_type,
324 msdu_start->stbc,
325 msdu_start->sgi,
326 msdu_start->rate_mcs,
327 msdu_start->receive_bandwidth,
328 msdu_start->reception_type,
329 msdu_start->ppdu_start_timestamp);
330
331 hal_verbose_debug(
332 "rx_msdu_start tlv (2/2) - "
333 "sw_phy_meta_data: %x ",
334 msdu_start->sw_phy_meta_data);
335 }
336
337 /**
338 * hal_rx_dump_msdu_end_tlv_6750() - dump RX msdu_end TLV in structured
339 * human readable format.
340 * @pkttlvs: pointer to the pkttlvs.
341 * @dbg_level: log level.
342 *
343 * Return: void
344 */
hal_rx_dump_msdu_end_tlv_6750(void * pkttlvs,uint8_t dbg_level)345 static void hal_rx_dump_msdu_end_tlv_6750(void *pkttlvs,
346 uint8_t dbg_level)
347 {
348 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
349 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
350
351 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP,
352 "rx_msdu_end tlv (1/3) - "
353 "rxpcu_mpdu_filter_in_category: %x "
354 "sw_frame_group_id: %x "
355 "phy_ppdu_id: %x "
356 "ip_hdr_chksum: %x "
357 "tcp_udp_chksum: %x "
358 "key_id_octet: %x "
359 "cce_super_rule: %x "
360 "cce_classify_not_done_truncat: %x "
361 "cce_classify_not_done_cce_dis: %x "
362 "reported_mpdu_length: %x "
363 "first_msdu: %x "
364 "last_msdu: %x "
365 "sa_idx_timeout: %x "
366 "da_idx_timeout: %x "
367 "msdu_limit_error: %x "
368 "flow_idx_timeout: %x "
369 "flow_idx_invalid: %x "
370 "wifi_parser_error: %x "
371 "amsdu_parser_error: %x",
372 msdu_end->rxpcu_mpdu_filter_in_category,
373 msdu_end->sw_frame_group_id,
374 msdu_end->phy_ppdu_id,
375 msdu_end->ip_hdr_chksum,
376 msdu_end->tcp_udp_chksum,
377 msdu_end->key_id_octet,
378 msdu_end->cce_super_rule,
379 msdu_end->cce_classify_not_done_truncate,
380 msdu_end->cce_classify_not_done_cce_dis,
381 msdu_end->reported_mpdu_length,
382 msdu_end->first_msdu,
383 msdu_end->last_msdu,
384 msdu_end->sa_idx_timeout,
385 msdu_end->da_idx_timeout,
386 msdu_end->msdu_limit_error,
387 msdu_end->flow_idx_timeout,
388 msdu_end->flow_idx_invalid,
389 msdu_end->wifi_parser_error,
390 msdu_end->amsdu_parser_error);
391
392 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP,
393 "rx_msdu_end tlv (2/3)- "
394 "sa_is_valid: %x "
395 "da_is_valid: %x "
396 "da_is_mcbc: %x "
397 "l3_header_padding: %x "
398 "ipv6_options_crc: %x "
399 "tcp_seq_number: %x "
400 "tcp_ack_number: %x "
401 "tcp_flag: %x "
402 "lro_eligible: %x "
403 "window_size: %x "
404 "da_offset: %x "
405 "sa_offset: %x "
406 "da_offset_valid: %x "
407 "sa_offset_valid: %x "
408 "rule_indication_31_0: %x "
409 "rule_indication_63_32: %x "
410 "sa_idx: %x "
411 "da_idx: %x "
412 "msdu_drop: %x "
413 "reo_destination_indication: %x "
414 "flow_idx: %x "
415 "fse_metadata: %x "
416 "cce_metadata: %x "
417 "sa_sw_peer_id: %x ",
418 msdu_end->sa_is_valid,
419 msdu_end->da_is_valid,
420 msdu_end->da_is_mcbc,
421 msdu_end->l3_header_padding,
422 msdu_end->ipv6_options_crc,
423 msdu_end->tcp_seq_number,
424 msdu_end->tcp_ack_number,
425 msdu_end->tcp_flag,
426 msdu_end->lro_eligible,
427 msdu_end->window_size,
428 msdu_end->da_offset,
429 msdu_end->sa_offset,
430 msdu_end->da_offset_valid,
431 msdu_end->sa_offset_valid,
432 msdu_end->rule_indication_31_0,
433 msdu_end->rule_indication_63_32,
434 msdu_end->sa_idx,
435 msdu_end->da_idx_or_sw_peer_id,
436 msdu_end->msdu_drop,
437 msdu_end->reo_destination_indication,
438 msdu_end->flow_idx,
439 msdu_end->fse_metadata,
440 msdu_end->cce_metadata,
441 msdu_end->sa_sw_peer_id);
442 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP,
443 "rx_msdu_end tlv (3/3)"
444 "aggregation_count %x "
445 "flow_aggregation_continuation %x "
446 "fisa_timeout %x "
447 "cumulative_l4_checksum %x "
448 "cumulative_ip_length %x",
449 msdu_end->aggregation_count,
450 msdu_end->flow_aggregation_continuation,
451 msdu_end->fisa_timeout,
452 msdu_end->cumulative_l4_checksum,
453 msdu_end->cumulative_ip_length);
454 }
455
456 /*
457 * Get tid from RX_MPDU_START
458 */
459 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \
460 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
461 RX_MPDU_INFO_7_TID_OFFSET)), \
462 RX_MPDU_INFO_7_TID_MASK, \
463 RX_MPDU_INFO_7_TID_LSB))
464
hal_rx_mpdu_start_tid_get_6750(uint8_t * buf)465 static uint32_t hal_rx_mpdu_start_tid_get_6750(uint8_t *buf)
466 {
467 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
468 struct rx_mpdu_start *mpdu_start =
469 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
470 uint32_t tid;
471
472 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details);
473
474 return tid;
475 }
476
477 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \
478 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \
479 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \
480 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \
481 RX_MSDU_START_5_RECEPTION_TYPE_LSB))
482
483 /**
484 * hal_rx_msdu_start_reception_type_get_6750() - API to get the reception type
485 * Interval from rx_msdu_start
486 * @buf: pointer to the start of RX PKT TLV header
487 *
488 * Return: uint32_t(reception_type)
489 */
490 static
hal_rx_msdu_start_reception_type_get_6750(uint8_t * buf)491 uint32_t hal_rx_msdu_start_reception_type_get_6750(uint8_t *buf)
492 {
493 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
494 struct rx_msdu_start *msdu_start =
495 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
496 uint32_t reception_type;
497
498 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start);
499
500 return reception_type;
501 }
502
503 /**
504 * hal_rx_msdu_end_da_idx_get_6750() - API to get da_idx from rx_msdu_end TLV
505 * @buf: pointer to the start of RX PKT TLV headers
506 *
507 * Return: da index
508 */
hal_rx_msdu_end_da_idx_get_6750(uint8_t * buf)509 static uint16_t hal_rx_msdu_end_da_idx_get_6750(uint8_t *buf)
510 {
511 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
512 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
513 uint16_t da_idx;
514
515 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
516
517 return da_idx;
518 }
519
520 /**
521 * hal_rx_get_rx_fragment_number_6750() - API to retrieve rx fragment number
522 * @buf: Network buffer
523 *
524 * Return: rx fragment number
525 */
526 static
hal_rx_get_rx_fragment_number_6750(uint8_t * buf)527 uint8_t hal_rx_get_rx_fragment_number_6750(uint8_t *buf)
528 {
529 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
530 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
531
532 /* Return first 4 bits as fragment number */
533 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) &
534 DOT11_SEQ_FRAG_MASK);
535 }
536
537 /**
538 * hal_rx_msdu_end_da_is_mcbc_get_6750() - API to check if pkt is MCBC
539 * from rx_msdu_end TLV
540 * @buf: pointer to the start of RX PKT TLV headers
541 *
542 * Return: da_is_mcbc
543 */
544 static uint8_t
hal_rx_msdu_end_da_is_mcbc_get_6750(uint8_t * buf)545 hal_rx_msdu_end_da_is_mcbc_get_6750(uint8_t *buf)
546 {
547 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
548 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
549
550 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
551 }
552
553 /**
554 * hal_rx_msdu_end_sa_is_valid_get_6750() - API to get_6750 the sa_is_valid bit
555 * from rx_msdu_end TLV
556 * @buf: pointer to the start of RX PKT TLV headers
557 *
558 * Return: sa_is_valid bit
559 */
560 static uint8_t
hal_rx_msdu_end_sa_is_valid_get_6750(uint8_t * buf)561 hal_rx_msdu_end_sa_is_valid_get_6750(uint8_t *buf)
562 {
563 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
564 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
565 uint8_t sa_is_valid;
566
567 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end);
568
569 return sa_is_valid;
570 }
571
572 /**
573 * hal_rx_msdu_end_sa_idx_get_6750() - API to get_6750 the sa_idx from
574 * rx_msdu_end TLV
575 * @buf: pointer to the start of RX PKT TLV headers
576 *
577 * Return: sa_idx (SA AST index)
578 */
579 static
hal_rx_msdu_end_sa_idx_get_6750(uint8_t * buf)580 uint16_t hal_rx_msdu_end_sa_idx_get_6750(uint8_t *buf)
581 {
582 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
583 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
584 uint16_t sa_idx;
585
586 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
587
588 return sa_idx;
589 }
590
591 /**
592 * hal_rx_desc_is_first_msdu_6750() - Check if first msdu
593 * @hw_desc_addr: hardware descriptor address
594 *
595 * Return: 0 - success/ non-zero failure
596 */
hal_rx_desc_is_first_msdu_6750(void * hw_desc_addr)597 static uint32_t hal_rx_desc_is_first_msdu_6750(void *hw_desc_addr)
598 {
599 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
600 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
601
602 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU);
603 }
604
605 /**
606 * hal_rx_msdu_end_l3_hdr_padding_get_6750() - API to get the l3_header padding
607 * from rx_msdu_end TLV
608 * @buf: pointer to the start of RX PKT TLV headers
609 *
610 * Return: number of l3 header padding bytes
611 */
hal_rx_msdu_end_l3_hdr_padding_get_6750(uint8_t * buf)612 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6750(uint8_t *buf)
613 {
614 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
615 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
616 uint32_t l3_header_padding;
617
618 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
619
620 return l3_header_padding;
621 }
622
623 /**
624 * hal_rx_tlv_l3_type_get_6750: API to get the l3 type from
625 * from rx_msdu_end tlv
626 *
627 * @buf: pointer to the start of RX PKT TLV headers
628 * Return: uint32_t(l3 type)
629 */
630 static inline uint32_t
hal_rx_tlv_l3_type_get_6750(uint8_t * buf)631 hal_rx_tlv_l3_type_get_6750(uint8_t *buf)
632 {
633 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
634 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
635 uint32_t l3_type;
636
637 l3_type = HAL_RX_MSDU_END_L3_TYPE_GET(msdu_end);
638
639 return l3_type;
640 }
641
642 /**
643 * hal_rx_encryption_info_valid_6750() - Returns encryption type.
644 * @buf: rx_tlv_hdr of the received packet
645 *
646 * Return: encryption type
647 */
hal_rx_encryption_info_valid_6750(uint8_t * buf)648 static uint32_t hal_rx_encryption_info_valid_6750(uint8_t *buf)
649 {
650 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
651 struct rx_mpdu_start *mpdu_start =
652 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
653 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
654 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info);
655
656 return encryption_info;
657 }
658
659 /**
660 * hal_rx_print_pn_6750() - Prints the PN of rx packet.
661 * @buf: rx_tlv_hdr of the received packet
662 *
663 * Return: void
664 */
hal_rx_print_pn_6750(uint8_t * buf)665 static void hal_rx_print_pn_6750(uint8_t *buf)
666 {
667 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
668 struct rx_mpdu_start *mpdu_start =
669 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
670 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
671
672 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info);
673 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info);
674 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info);
675 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info);
676
677 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x",
678 pn_127_96, pn_95_64, pn_63_32, pn_31_0);
679 }
680
681 /**
682 * hal_rx_msdu_end_first_msdu_get_6750() - API to get first msdu status
683 * from rx_msdu_end TLV
684 * @buf: pointer to the start of RX PKT TLV headers
685 *
686 * Return: first_msdu
687 */
hal_rx_msdu_end_first_msdu_get_6750(uint8_t * buf)688 static uint8_t hal_rx_msdu_end_first_msdu_get_6750(uint8_t *buf)
689 {
690 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
691 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
692 uint8_t first_msdu;
693
694 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end);
695
696 return first_msdu;
697 }
698
699 /**
700 * hal_rx_msdu_end_da_is_valid_get_6750() - API to check if da is valid
701 * from rx_msdu_end TLV
702 * @buf: pointer to the start of RX PKT TLV headers
703 *
704 * Return: da_is_valid
705 */
hal_rx_msdu_end_da_is_valid_get_6750(uint8_t * buf)706 static uint8_t hal_rx_msdu_end_da_is_valid_get_6750(uint8_t *buf)
707 {
708 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
709 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
710 uint8_t da_is_valid;
711
712 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end);
713
714 return da_is_valid;
715 }
716
717 /**
718 * hal_rx_msdu_end_last_msdu_get_6750() - API to get last msdu status
719 * from rx_msdu_end TLV
720 * @buf: pointer to the start of RX PKT TLV headers
721 *
722 * Return: last_msdu
723 */
hal_rx_msdu_end_last_msdu_get_6750(uint8_t * buf)724 static uint8_t hal_rx_msdu_end_last_msdu_get_6750(uint8_t *buf)
725 {
726 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
727 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
728 uint8_t last_msdu;
729
730 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end);
731
732 return last_msdu;
733 }
734
735 /**
736 * hal_rx_get_mpdu_mac_ad4_valid_6750() - Retrieves if mpdu 4th addr is valid
737 * @buf: Network buffer
738 *
739 * Return: value of mpdu 4th address valid field
740 */
hal_rx_get_mpdu_mac_ad4_valid_6750(uint8_t * buf)741 static bool hal_rx_get_mpdu_mac_ad4_valid_6750(uint8_t *buf)
742 {
743 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
744 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
745 bool ad4_valid = 0;
746
747 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info);
748
749 return ad4_valid;
750 }
751
752 /**
753 * hal_rx_mpdu_start_sw_peer_id_get_6750() - Retrieve sw peer_id
754 * @buf: network buffer
755 *
756 * Return: sw peer_id
757 */
hal_rx_mpdu_start_sw_peer_id_get_6750(uint8_t * buf)758 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6750(uint8_t *buf)
759 {
760 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
761 struct rx_mpdu_start *mpdu_start =
762 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
763
764 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET(
765 &mpdu_start->rx_mpdu_info_details);
766 }
767
768 /**
769 * hal_rx_mpdu_get_to_ds_6750() - API to get the tods info from rx_mpdu_start
770 * @buf: pointer to the start of RX PKT TLV header
771 *
772 * Return: uint32_t(to_ds)
773 */
hal_rx_mpdu_get_to_ds_6750(uint8_t * buf)774 static uint32_t hal_rx_mpdu_get_to_ds_6750(uint8_t *buf)
775 {
776 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
777 struct rx_mpdu_start *mpdu_start =
778 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
779
780 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
781
782 return HAL_RX_MPDU_GET_TODS(mpdu_info);
783 }
784
785 /**
786 * hal_rx_mpdu_get_fr_ds_6750() - API to get the from ds info from rx_mpdu_start
787 * @buf: pointer to the start of RX PKT TLV header
788 *
789 * Return: uint32_t(fr_ds)
790 */
hal_rx_mpdu_get_fr_ds_6750(uint8_t * buf)791 static uint32_t hal_rx_mpdu_get_fr_ds_6750(uint8_t *buf)
792 {
793 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
794 struct rx_mpdu_start *mpdu_start =
795 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
796
797 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
798
799 return HAL_RX_MPDU_GET_FROMDS(mpdu_info);
800 }
801
802 /**
803 * hal_rx_get_mpdu_frame_control_valid_6750() - Retrieves mpdu
804 * frame control valid
805 * @buf: Network buffer
806 *
807 * Return: value of frame control valid field
808 */
hal_rx_get_mpdu_frame_control_valid_6750(uint8_t * buf)809 static uint8_t hal_rx_get_mpdu_frame_control_valid_6750(uint8_t *buf)
810 {
811 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
812 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
813
814 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info);
815 }
816
817 /**
818 * hal_rx_mpdu_get_addr1_6750() - API to check get address1 of the mpdu
819 * @buf: pointer to the start of RX PKT TLV headera
820 * @mac_addr: pointer to mac address
821 *
822 * Return: success/failure
823 */
hal_rx_mpdu_get_addr1_6750(uint8_t * buf,uint8_t * mac_addr)824 static QDF_STATUS hal_rx_mpdu_get_addr1_6750(uint8_t *buf, uint8_t *mac_addr)
825 {
826 struct __attribute__((__packed__)) hal_addr1 {
827 uint32_t ad1_31_0;
828 uint16_t ad1_47_32;
829 };
830
831 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
832 struct rx_mpdu_start *mpdu_start =
833 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
834
835 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
836 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr;
837 uint32_t mac_addr_ad1_valid;
838
839 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info);
840
841 if (mac_addr_ad1_valid) {
842 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info);
843 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info);
844 return QDF_STATUS_SUCCESS;
845 }
846
847 return QDF_STATUS_E_FAILURE;
848 }
849
850 /**
851 * hal_rx_mpdu_get_addr2_6750() - API to check get address2 of the mpdu
852 * in the packet
853 * @buf: pointer to the start of RX PKT TLV header
854 * @mac_addr: pointer to mac address
855 *
856 * Return: success/failure
857 */
hal_rx_mpdu_get_addr2_6750(uint8_t * buf,uint8_t * mac_addr)858 static QDF_STATUS hal_rx_mpdu_get_addr2_6750(uint8_t *buf,
859 uint8_t *mac_addr)
860 {
861 struct __attribute__((__packed__)) hal_addr2 {
862 uint16_t ad2_15_0;
863 uint32_t ad2_47_16;
864 };
865
866 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
867 struct rx_mpdu_start *mpdu_start =
868 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
869
870 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
871 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr;
872 uint32_t mac_addr_ad2_valid;
873
874 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info);
875
876 if (mac_addr_ad2_valid) {
877 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info);
878 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info);
879 return QDF_STATUS_SUCCESS;
880 }
881
882 return QDF_STATUS_E_FAILURE;
883 }
884
885 /**
886 * hal_rx_mpdu_get_addr3_6750() - API to get address3 of the mpdu
887 * in the packet
888 * @buf: pointer to the start of RX PKT TLV header
889 * @mac_addr: pointer to mac address
890 *
891 * Return: success/failure
892 */
hal_rx_mpdu_get_addr3_6750(uint8_t * buf,uint8_t * mac_addr)893 static QDF_STATUS hal_rx_mpdu_get_addr3_6750(uint8_t *buf, uint8_t *mac_addr)
894 {
895 struct __attribute__((__packed__)) hal_addr3 {
896 uint32_t ad3_31_0;
897 uint16_t ad3_47_32;
898 };
899
900 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
901 struct rx_mpdu_start *mpdu_start =
902 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
903
904 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
905 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr;
906 uint32_t mac_addr_ad3_valid;
907
908 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info);
909
910 if (mac_addr_ad3_valid) {
911 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info);
912 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info);
913 return QDF_STATUS_SUCCESS;
914 }
915
916 return QDF_STATUS_E_FAILURE;
917 }
918
919 /**
920 * hal_rx_mpdu_get_addr4_6750() - API to get address4 of the mpdu
921 * in the packet
922 * @buf: pointer to the start of RX PKT TLV header
923 * @mac_addr: pointer to mac address
924 *
925 * Return: success/failure
926 */
hal_rx_mpdu_get_addr4_6750(uint8_t * buf,uint8_t * mac_addr)927 static QDF_STATUS hal_rx_mpdu_get_addr4_6750(uint8_t *buf, uint8_t *mac_addr)
928 {
929 struct __attribute__((__packed__)) hal_addr4 {
930 uint32_t ad4_31_0;
931 uint16_t ad4_47_32;
932 };
933
934 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
935 struct rx_mpdu_start *mpdu_start =
936 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
937
938 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
939 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr;
940 uint32_t mac_addr_ad4_valid;
941
942 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info);
943
944 if (mac_addr_ad4_valid) {
945 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info);
946 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info);
947 return QDF_STATUS_SUCCESS;
948 }
949
950 return QDF_STATUS_E_FAILURE;
951 }
952
953 /**
954 * hal_rx_get_mpdu_sequence_control_valid_6750() - Get mpdu sequence
955 * control valid
956 * @buf: Network buffer
957 *
958 * Return: value of sequence control valid field
959 */
hal_rx_get_mpdu_sequence_control_valid_6750(uint8_t * buf)960 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6750(uint8_t *buf)
961 {
962 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
963 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
964
965 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
966 }
967
968 /**
969 * hal_rx_is_unicast_6750() - check packet is unicast frame or not.
970 * @buf: pointer to rx pkt TLV.
971 *
972 * Return: true on unicast.
973 */
hal_rx_is_unicast_6750(uint8_t * buf)974 static bool hal_rx_is_unicast_6750(uint8_t *buf)
975 {
976 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
977 struct rx_mpdu_start *mpdu_start =
978 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
979 uint32_t grp_id;
980 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
981
982 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
983 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)),
984 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK,
985 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB));
986
987 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
988 }
989
990 /**
991 * hal_rx_tid_get_6750() - get tid based on qos control valid.
992 * @hal_soc_hdl: hal_soc handle
993 * @buf: pointer to rx pkt TLV.
994 *
995 * Return: tid
996 */
hal_rx_tid_get_6750(hal_soc_handle_t hal_soc_hdl,uint8_t * buf)997 static uint32_t hal_rx_tid_get_6750(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
998 {
999 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1000 struct rx_mpdu_start *mpdu_start =
1001 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1002 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
1003 uint8_t qos_control_valid =
1004 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
1005 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)),
1006 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK,
1007 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB));
1008
1009 if (qos_control_valid)
1010 return hal_rx_mpdu_start_tid_get_6750(buf);
1011
1012 return HAL_RX_NON_QOS_TID;
1013 }
1014
1015 /**
1016 * hal_rx_hw_desc_get_ppduid_get_6750() - retrieve ppdu id
1017 * @rx_tlv_hdr: rx tlv header
1018 * @rxdma_dst_ring_desc: rxdma HW descriptor
1019 *
1020 * Return: ppdu id
1021 */
hal_rx_hw_desc_get_ppduid_get_6750(void * rx_tlv_hdr,void * rxdma_dst_ring_desc)1022 static uint32_t hal_rx_hw_desc_get_ppduid_get_6750(void *rx_tlv_hdr,
1023 void *rxdma_dst_ring_desc)
1024 {
1025 struct rx_mpdu_info *rx_mpdu_info;
1026 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr;
1027
1028 rx_mpdu_info =
1029 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
1030
1031 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_9, PHY_PPDU_ID);
1032 }
1033
1034 /**
1035 * hal_reo_status_get_header_6750() - Process reo desc info
1036 * @ring_desc: REO status ring descriptor
1037 * @b: tlv type info
1038 * @h1: Pointer to hal_reo_status_header where info to be stored
1039 *
1040 * Return - none.
1041 *
1042 */
hal_reo_status_get_header_6750(hal_ring_desc_t ring_desc,int b,void * h1)1043 static void hal_reo_status_get_header_6750(hal_ring_desc_t ring_desc, int b,
1044 void *h1)
1045 {
1046 uint32_t *d = (uint32_t *)ring_desc;
1047 uint32_t val1 = 0;
1048 struct hal_reo_status_header *h =
1049 (struct hal_reo_status_header *)h1;
1050
1051 /* Offsets of descriptor fields defined in HW headers start
1052 * from the field after TLV header
1053 */
1054 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr));
1055
1056 switch (b) {
1057 case HAL_REO_QUEUE_STATS_STATUS_TLV:
1058 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
1059 STATUS_HEADER_REO_STATUS_NUMBER)];
1060 break;
1061 case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
1062 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0,
1063 STATUS_HEADER_REO_STATUS_NUMBER)];
1064 break;
1065 case HAL_REO_FLUSH_CACHE_STATUS_TLV:
1066 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0,
1067 STATUS_HEADER_REO_STATUS_NUMBER)];
1068 break;
1069 case HAL_REO_UNBLK_CACHE_STATUS_TLV:
1070 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0,
1071 STATUS_HEADER_REO_STATUS_NUMBER)];
1072 break;
1073 case HAL_REO_TIMOUT_LIST_STATUS_TLV:
1074 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0,
1075 STATUS_HEADER_REO_STATUS_NUMBER)];
1076 break;
1077 case HAL_REO_DESC_THRES_STATUS_TLV:
1078 val1 =
1079 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0,
1080 STATUS_HEADER_REO_STATUS_NUMBER)];
1081 break;
1082 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
1083 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0,
1084 STATUS_HEADER_REO_STATUS_NUMBER)];
1085 break;
1086 default:
1087 qdf_nofl_err("ERROR: Unknown tlv\n");
1088 break;
1089 }
1090 h->cmd_num =
1091 HAL_GET_FIELD(
1092 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER,
1093 val1);
1094 h->exec_time =
1095 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
1096 CMD_EXECUTION_TIME, val1);
1097 h->status =
1098 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
1099 REO_CMD_EXECUTION_STATUS, val1);
1100 switch (b) {
1101 case HAL_REO_QUEUE_STATS_STATUS_TLV:
1102 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1,
1103 STATUS_HEADER_TIMESTAMP)];
1104 break;
1105 case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
1106 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1,
1107 STATUS_HEADER_TIMESTAMP)];
1108 break;
1109 case HAL_REO_FLUSH_CACHE_STATUS_TLV:
1110 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1,
1111 STATUS_HEADER_TIMESTAMP)];
1112 break;
1113 case HAL_REO_UNBLK_CACHE_STATUS_TLV:
1114 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1,
1115 STATUS_HEADER_TIMESTAMP)];
1116 break;
1117 case HAL_REO_TIMOUT_LIST_STATUS_TLV:
1118 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1,
1119 STATUS_HEADER_TIMESTAMP)];
1120 break;
1121 case HAL_REO_DESC_THRES_STATUS_TLV:
1122 val1 =
1123 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1,
1124 STATUS_HEADER_TIMESTAMP)];
1125 break;
1126 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
1127 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1,
1128 STATUS_HEADER_TIMESTAMP)];
1129 break;
1130 default:
1131 qdf_nofl_err("ERROR: Unknown tlv\n");
1132 break;
1133 }
1134 h->tstamp =
1135 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1);
1136 }
1137
1138 /**
1139 * hal_tx_desc_set_mesh_en_6750() - Set mesh_enable flag in Tx descriptor
1140 * @desc: Handle to Tx Descriptor
1141 * @en: For raw WiFi frames, this indicates transmission to a mesh STA,
1142 * enabling the interpretation of the 'Mesh Control Present' bit
1143 * (bit 8) of QoS Control (otherwise this bit is ignored),
1144 * For native WiFi frames, this indicates that a 'Mesh Control' field
1145 * is present between the header and the LLC.
1146 *
1147 * Return: void
1148 */
1149 static inline
hal_tx_desc_set_mesh_en_6750(void * desc,uint8_t en)1150 void hal_tx_desc_set_mesh_en_6750(void *desc, uint8_t en)
1151 {
1152 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |=
1153 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en);
1154 }
1155
1156 static
hal_rx_msdu0_buffer_addr_lsb_6750(void * link_desc_va)1157 void *hal_rx_msdu0_buffer_addr_lsb_6750(void *link_desc_va)
1158 {
1159 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
1160 }
1161
1162 static
hal_rx_msdu_desc_info_ptr_get_6750(void * msdu0)1163 void *hal_rx_msdu_desc_info_ptr_get_6750(void *msdu0)
1164 {
1165 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
1166 }
1167
1168 static
hal_ent_mpdu_desc_info_6750(void * ent_ring_desc)1169 void *hal_ent_mpdu_desc_info_6750(void *ent_ring_desc)
1170 {
1171 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
1172 }
1173
1174 static
hal_dst_mpdu_desc_info_6750(void * dst_ring_desc)1175 void *hal_dst_mpdu_desc_info_6750(void *dst_ring_desc)
1176 {
1177 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
1178 }
1179
1180 static
hal_rx_get_fc_valid_6750(uint8_t * buf)1181 uint8_t hal_rx_get_fc_valid_6750(uint8_t *buf)
1182 {
1183 return HAL_RX_GET_FC_VALID(buf);
1184 }
1185
hal_rx_get_to_ds_flag_6750(uint8_t * buf)1186 static uint8_t hal_rx_get_to_ds_flag_6750(uint8_t *buf)
1187 {
1188 return HAL_RX_GET_TO_DS_FLAG(buf);
1189 }
1190
hal_rx_get_mac_addr2_valid_6750(uint8_t * buf)1191 static uint8_t hal_rx_get_mac_addr2_valid_6750(uint8_t *buf)
1192 {
1193 return HAL_RX_GET_MAC_ADDR2_VALID(buf);
1194 }
1195
hal_rx_get_filter_category_6750(uint8_t * buf)1196 static uint8_t hal_rx_get_filter_category_6750(uint8_t *buf)
1197 {
1198 return HAL_RX_GET_FILTER_CATEGORY(buf);
1199 }
1200
1201 static uint32_t
hal_rx_get_ppdu_id_6750(uint8_t * buf)1202 hal_rx_get_ppdu_id_6750(uint8_t *buf)
1203 {
1204 return HAL_RX_GET_PPDU_ID(buf);
1205 }
1206
1207 /**
1208 * hal_reo_config_6750() - Set reo config parameters
1209 * @soc: hal soc handle
1210 * @reg_val: value to be set
1211 * @reo_params: reo parameters
1212 *
1213 * Return: void
1214 */
1215 static
hal_reo_config_6750(struct hal_soc * soc,uint32_t reg_val,struct hal_reo_params * reo_params)1216 void hal_reo_config_6750(struct hal_soc *soc,
1217 uint32_t reg_val,
1218 struct hal_reo_params *reo_params)
1219 {
1220 HAL_REO_R0_CONFIG(soc, reg_val, reo_params);
1221 }
1222
1223 /**
1224 * hal_rx_msdu_desc_info_get_ptr_6750() - Get msdu desc info ptr
1225 * @msdu_details_ptr: Pointer to msdu_details_ptr
1226 *
1227 * Return - Pointer to rx_msdu_desc_info structure.
1228 *
1229 */
hal_rx_msdu_desc_info_get_ptr_6750(void * msdu_details_ptr)1230 static void *hal_rx_msdu_desc_info_get_ptr_6750(void *msdu_details_ptr)
1231 {
1232 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
1233 }
1234
1235 /**
1236 * hal_rx_link_desc_msdu0_ptr_6750() - Get pointer to rx_msdu details
1237 * @link_desc: Pointer to link desc
1238 *
1239 * Return - Pointer to rx_msdu_details structure
1240 *
1241 */
hal_rx_link_desc_msdu0_ptr_6750(void * link_desc)1242 static void *hal_rx_link_desc_msdu0_ptr_6750(void *link_desc)
1243 {
1244 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
1245 }
1246
1247 /**
1248 * hal_rx_msdu_flow_idx_get_6750() - API to get flow index
1249 * from rx_msdu_end TLV
1250 * @buf: pointer to the start of RX PKT TLV headers
1251 *
1252 * Return: flow index value from MSDU END TLV
1253 */
hal_rx_msdu_flow_idx_get_6750(uint8_t * buf)1254 static inline uint32_t hal_rx_msdu_flow_idx_get_6750(uint8_t *buf)
1255 {
1256 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1257 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1258
1259 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
1260 }
1261
1262 /**
1263 * hal_rx_msdu_flow_idx_invalid_6750() - API to get flow index invalid
1264 * from rx_msdu_end TLV
1265 * @buf: pointer to the start of RX PKT TLV headers
1266 *
1267 * Return: flow index invalid value from MSDU END TLV
1268 */
hal_rx_msdu_flow_idx_invalid_6750(uint8_t * buf)1269 static bool hal_rx_msdu_flow_idx_invalid_6750(uint8_t *buf)
1270 {
1271 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1272 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1273
1274 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
1275 }
1276
1277 /**
1278 * hal_rx_msdu_flow_idx_timeout_6750() - API to get flow index timeout
1279 * from rx_msdu_end TLV
1280 * @buf: pointer to the start of RX PKT TLV headers
1281 *
1282 * Return: flow index timeout value from MSDU END TLV
1283 */
hal_rx_msdu_flow_idx_timeout_6750(uint8_t * buf)1284 static bool hal_rx_msdu_flow_idx_timeout_6750(uint8_t *buf)
1285 {
1286 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1287 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1288
1289 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
1290 }
1291
1292 /**
1293 * hal_rx_msdu_fse_metadata_get_6750() - API to get FSE metadata
1294 * from rx_msdu_end TLV
1295 * @buf: pointer to the start of RX PKT TLV headers
1296 *
1297 * Return: fse metadata value from MSDU END TLV
1298 */
hal_rx_msdu_fse_metadata_get_6750(uint8_t * buf)1299 static uint32_t hal_rx_msdu_fse_metadata_get_6750(uint8_t *buf)
1300 {
1301 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1302 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1303
1304 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end);
1305 }
1306
1307 /**
1308 * hal_rx_msdu_cce_metadata_get_6750() - API to get CCE metadata
1309 * from rx_msdu_end TLV
1310 * @buf: pointer to the start of RX PKT TLV headers
1311 *
1312 * Return: cce_metadata
1313 */
1314 static uint16_t
hal_rx_msdu_cce_metadata_get_6750(uint8_t * buf)1315 hal_rx_msdu_cce_metadata_get_6750(uint8_t *buf)
1316 {
1317 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1318 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1319
1320 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end);
1321 }
1322
1323 /**
1324 * hal_rx_msdu_get_flow_params_6750() - API to get flow index, flow index
1325 * invalid and flow index timeout from
1326 * rx_msdu_end TLV
1327 * @buf: pointer to the start of RX PKT TLV headers
1328 * @flow_invalid: pointer to return value of flow_idx_valid
1329 * @flow_timeout: pointer to return value of flow_idx_timeout
1330 * @flow_index: pointer to return value of flow_idx
1331 *
1332 * Return: none
1333 */
1334 static inline void
hal_rx_msdu_get_flow_params_6750(uint8_t * buf,bool * flow_invalid,bool * flow_timeout,uint32_t * flow_index)1335 hal_rx_msdu_get_flow_params_6750(uint8_t *buf,
1336 bool *flow_invalid,
1337 bool *flow_timeout,
1338 uint32_t *flow_index)
1339 {
1340 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1341 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1342
1343 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
1344 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
1345 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
1346 }
1347
1348 /**
1349 * hal_rx_tlv_get_tcp_chksum_6750() - API to get tcp checksum
1350 * @buf: rx_tlv_hdr
1351 *
1352 * Return: tcp checksum
1353 */
1354 static uint16_t
hal_rx_tlv_get_tcp_chksum_6750(uint8_t * buf)1355 hal_rx_tlv_get_tcp_chksum_6750(uint8_t *buf)
1356 {
1357 return HAL_RX_TLV_GET_TCP_CHKSUM(buf);
1358 }
1359
1360 /**
1361 * hal_rx_get_rx_sequence_6750() - Function to retrieve rx sequence number
1362 * @buf: Network buffer
1363 *
1364 * Return: rx sequence number
1365 */
1366 static
hal_rx_get_rx_sequence_6750(uint8_t * buf)1367 uint16_t hal_rx_get_rx_sequence_6750(uint8_t *buf)
1368 {
1369 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
1370 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
1371
1372 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info);
1373 }
1374
1375 #define UMAC_WINDOW_REMAP_RANGE 0x14
1376 #define CE_WINDOW_REMAP_RANGE 0x37
1377 #define CMEM_WINDOW_REMAP_RANGE 0x2
1378
1379 /**
1380 * hal_get_window_address_6750() - Function to get hp/tp address
1381 * @hal_soc: Pointer to hal_soc
1382 * @addr: address offset of register
1383 *
1384 * Return: modified address offset of register
1385 */
hal_get_window_address_6750(struct hal_soc * hal_soc,qdf_iomem_t addr)1386 static inline qdf_iomem_t hal_get_window_address_6750(struct hal_soc *hal_soc,
1387 qdf_iomem_t addr)
1388 {
1389 uint32_t offset;
1390 uint32_t window;
1391 uint8_t scale;
1392
1393 offset = addr - hal_soc->dev_base_addr;
1394 window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
1395
1396 /* UMAC: 2nd window, CE: 3rd window, CMEM: 4th window */
1397 switch (window) {
1398 case UMAC_WINDOW_REMAP_RANGE:
1399 scale = 1;
1400 break;
1401 case CE_WINDOW_REMAP_RANGE:
1402 scale = 2;
1403 break;
1404 case CMEM_WINDOW_REMAP_RANGE:
1405 scale = 3;
1406 break;
1407 default:
1408 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
1409 "%s: ERROR: Accessing Wrong register\n", __func__);
1410 qdf_assert_always(0);
1411 return 0;
1412 }
1413
1414 return hal_soc->dev_base_addr + (scale * WINDOW_START) +
1415 (offset & WINDOW_RANGE_MASK);
1416 }
1417
1418 /**
1419 * hal_rx_get_fisa_cumulative_l4_checksum_6750() - Retrieve cumulative
1420 * checksum
1421 * @buf: buffer pointer
1422 *
1423 * Return: cumulative checksum
1424 */
1425 static inline
hal_rx_get_fisa_cumulative_l4_checksum_6750(uint8_t * buf)1426 uint16_t hal_rx_get_fisa_cumulative_l4_checksum_6750(uint8_t *buf)
1427 {
1428 return HAL_RX_TLV_GET_FISA_CUMULATIVE_L4_CHECKSUM(buf);
1429 }
1430
1431 /**
1432 * hal_rx_get_fisa_cumulative_ip_length_6750() - Retrieve cumulative
1433 * ip length
1434 * @buf: buffer pointer
1435 *
1436 * Return: cumulative length
1437 */
1438 static inline
hal_rx_get_fisa_cumulative_ip_length_6750(uint8_t * buf)1439 uint16_t hal_rx_get_fisa_cumulative_ip_length_6750(uint8_t *buf)
1440 {
1441 return HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(buf);
1442 }
1443
1444 /**
1445 * hal_rx_get_udp_proto_6750() - Retrieve udp proto value
1446 * @buf: buffer
1447 *
1448 * Return: udp proto bit
1449 */
1450 static inline
hal_rx_get_udp_proto_6750(uint8_t * buf)1451 bool hal_rx_get_udp_proto_6750(uint8_t *buf)
1452 {
1453 return HAL_RX_TLV_GET_UDP_PROTO(buf);
1454 }
1455
1456 /**
1457 * hal_rx_get_flow_agg_continuation_6750() - retrieve flow agg
1458 * continuation
1459 * @buf: buffer
1460 *
1461 * Return: flow agg
1462 */
1463 static inline
hal_rx_get_flow_agg_continuation_6750(uint8_t * buf)1464 bool hal_rx_get_flow_agg_continuation_6750(uint8_t *buf)
1465 {
1466 return HAL_RX_TLV_GET_FLOW_AGGR_CONT(buf);
1467 }
1468
1469 /**
1470 * hal_rx_get_flow_agg_count_6750()- Retrieve flow agg count
1471 * @buf: buffer
1472 *
1473 * Return: flow agg count
1474 */
1475 static inline
hal_rx_get_flow_agg_count_6750(uint8_t * buf)1476 uint8_t hal_rx_get_flow_agg_count_6750(uint8_t *buf)
1477 {
1478 return HAL_RX_TLV_GET_FLOW_AGGR_COUNT(buf);
1479 }
1480
1481 /**
1482 * hal_rx_get_fisa_timeout_6750() - Retrieve fisa timeout
1483 * @buf: buffer
1484 *
1485 * Return: fisa timeout
1486 */
1487 static inline
hal_rx_get_fisa_timeout_6750(uint8_t * buf)1488 bool hal_rx_get_fisa_timeout_6750(uint8_t *buf)
1489 {
1490 return HAL_RX_TLV_GET_FISA_TIMEOUT(buf);
1491 }
1492
1493 /**
1494 * hal_rx_mpdu_start_tlv_tag_valid_6750() - API to check if RX_MPDU_START
1495 * tlv tag is valid
1496 * @rx_tlv_hdr: start address of rx_pkt_tlvs
1497 *
1498 * Return: true if RX_MPDU_START is valid, else false.
1499 */
hal_rx_mpdu_start_tlv_tag_valid_6750(void * rx_tlv_hdr)1500 static uint8_t hal_rx_mpdu_start_tlv_tag_valid_6750(void *rx_tlv_hdr)
1501 {
1502 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr;
1503 uint32_t tlv_tag;
1504
1505 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv);
1506
1507 return tlv_tag == WIFIRX_MPDU_START_E ? true : false;
1508 }
1509
1510 /**
1511 * hal_reo_set_err_dst_remap_6750() - Function to set REO error destination
1512 * ring remap register
1513 * @hal_soc: Pointer to hal_soc
1514 *
1515 * Return: none.
1516 */
1517 static void
hal_reo_set_err_dst_remap_6750(void * hal_soc)1518 hal_reo_set_err_dst_remap_6750(void *hal_soc)
1519 {
1520 /*
1521 * Set REO error 2k jump (error code 5) / OOR (error code 7)
1522 * frame routed to REO2TCL ring.
1523 */
1524 uint32_t dst_remap_ix0 =
1525 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 0) |
1526 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 1) |
1527 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 2) |
1528 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 3) |
1529 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 4) |
1530 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) |
1531 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 6) |
1532 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7);
1533
1534 uint32_t dst_remap_ix1 =
1535 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 14) |
1536 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 13) |
1537 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 12) |
1538 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 11) |
1539 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 10) |
1540 HAL_REO_ERR_REMAP_IX1(REO_REMAP_RELEASE, 9) |
1541 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 8);
1542
1543 HAL_REG_WRITE(hal_soc,
1544 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(
1545 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1546 dst_remap_ix0);
1547
1548 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x",
1549 HAL_REG_READ(
1550 hal_soc,
1551 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(
1552 SEQ_WCSS_UMAC_REO_REG_OFFSET)));
1553
1554 HAL_REG_WRITE(hal_soc,
1555 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(
1556 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1557 dst_remap_ix1);
1558
1559 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1 0x%x",
1560 HAL_REG_READ(
1561 hal_soc,
1562 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(
1563 SEQ_WCSS_UMAC_REO_REG_OFFSET)));
1564 }
1565
1566 /**
1567 * hal_rx_flow_setup_fse_6750() - Setup a flow search entry in HW FST
1568 * @rx_fst: Pointer to the Rx Flow Search Table
1569 * @table_offset: offset into the table where the flow is to be setup
1570 * @rx_flow: Flow Parameters
1571 *
1572 * Flow table entry fields are updated in host byte order, little endian order.
1573 *
1574 * Return: Success/Failure
1575 */
1576 static void *
hal_rx_flow_setup_fse_6750(uint8_t * rx_fst,uint32_t table_offset,uint8_t * rx_flow)1577 hal_rx_flow_setup_fse_6750(uint8_t *rx_fst, uint32_t table_offset,
1578 uint8_t *rx_flow)
1579 {
1580 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
1581 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
1582 uint8_t *fse;
1583 bool fse_valid;
1584
1585 if (table_offset >= fst->max_entries) {
1586 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
1587 "HAL FSE table offset %u exceeds max entries %u",
1588 table_offset, fst->max_entries);
1589 return NULL;
1590 }
1591
1592 fse = (uint8_t *)fst->base_vaddr +
1593 (table_offset * HAL_RX_FST_ENTRY_SIZE);
1594
1595 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
1596
1597 if (fse_valid) {
1598 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
1599 "HAL FSE %pK already valid", fse);
1600 return NULL;
1601 }
1602
1603 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) =
1604 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96,
1605 (flow->tuple_info.src_ip_127_96));
1606
1607 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) =
1608 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64,
1609 (flow->tuple_info.src_ip_95_64));
1610
1611 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) =
1612 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32,
1613 (flow->tuple_info.src_ip_63_32));
1614
1615 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) =
1616 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0,
1617 (flow->tuple_info.src_ip_31_0));
1618
1619 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) =
1620 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96,
1621 (flow->tuple_info.dest_ip_127_96));
1622
1623 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) =
1624 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64,
1625 (flow->tuple_info.dest_ip_95_64));
1626
1627 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) =
1628 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32,
1629 (flow->tuple_info.dest_ip_63_32));
1630
1631 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) =
1632 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0,
1633 (flow->tuple_info.dest_ip_31_0));
1634
1635 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT);
1636 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |=
1637 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT,
1638 (flow->tuple_info.dest_port));
1639
1640 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT);
1641 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |=
1642 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT,
1643 (flow->tuple_info.src_port));
1644
1645 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL);
1646 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |=
1647 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL,
1648 flow->tuple_info.l4_protocol);
1649
1650 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER);
1651 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |=
1652 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER,
1653 flow->reo_destination_handler);
1654
1655 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
1656 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |=
1657 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1);
1658
1659 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA);
1660 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) =
1661 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA,
1662 (flow->fse_metadata));
1663
1664 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION);
1665 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |=
1666 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9,
1667 REO_DESTINATION_INDICATION,
1668 flow->reo_destination_indication);
1669
1670 /* Reset all the other fields in FSE */
1671 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9);
1672 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP);
1673 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT);
1674 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT);
1675 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP);
1676
1677 return fse;
1678 }
1679
1680 /**
1681 * hal_rx_flow_setup_cmem_fse_6750() - Setup a flow search entry in HW CMEM FST
1682 * @hal_soc: hal_soc reference
1683 * @cmem_ba: CMEM base address
1684 * @table_offset: offset into the table where the flow is to be setup
1685 * @rx_flow: Flow Parameters
1686 *
1687 * Return: Success/Failure
1688 */
1689 static uint32_t
hal_rx_flow_setup_cmem_fse_6750(struct hal_soc * hal_soc,uint32_t cmem_ba,uint32_t table_offset,uint8_t * rx_flow)1690 hal_rx_flow_setup_cmem_fse_6750(struct hal_soc *hal_soc, uint32_t cmem_ba,
1691 uint32_t table_offset, uint8_t *rx_flow)
1692 {
1693 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
1694 uint32_t fse_offset;
1695 uint32_t value;
1696
1697 fse_offset = cmem_ba + (table_offset * HAL_RX_FST_ENTRY_SIZE);
1698
1699 /* Reset the Valid bit */
1700 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_9,
1701 VALID), 0);
1702
1703 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96,
1704 (flow->tuple_info.src_ip_127_96));
1705 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_0,
1706 SRC_IP_127_96), value);
1707
1708 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64,
1709 (flow->tuple_info.src_ip_95_64));
1710 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_1,
1711 SRC_IP_95_64), value);
1712
1713 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32,
1714 (flow->tuple_info.src_ip_63_32));
1715 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_2,
1716 SRC_IP_63_32), value);
1717
1718 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0,
1719 (flow->tuple_info.src_ip_31_0));
1720 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_3,
1721 SRC_IP_31_0), value);
1722
1723 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96,
1724 (flow->tuple_info.dest_ip_127_96));
1725 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_4,
1726 DEST_IP_127_96), value);
1727
1728 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64,
1729 (flow->tuple_info.dest_ip_95_64));
1730 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_5,
1731 DEST_IP_95_64), value);
1732
1733 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32,
1734 (flow->tuple_info.dest_ip_63_32));
1735 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_6,
1736 DEST_IP_63_32), value);
1737
1738 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0,
1739 (flow->tuple_info.dest_ip_31_0));
1740 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_7,
1741 DEST_IP_31_0), value);
1742
1743 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT,
1744 (flow->tuple_info.dest_port));
1745 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT,
1746 (flow->tuple_info.src_port));
1747 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_8,
1748 SRC_PORT), value);
1749
1750 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA,
1751 (flow->fse_metadata));
1752 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_10,
1753 METADATA), value);
1754
1755 /* Reset all the other fields in FSE */
1756 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_11,
1757 MSDU_COUNT), 0);
1758 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_12,
1759 MSDU_BYTE_COUNT), 0);
1760 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_13,
1761 TIMESTAMP), 0);
1762
1763 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL,
1764 flow->tuple_info.l4_protocol);
1765 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER,
1766 flow->reo_destination_handler);
1767 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9,
1768 REO_DESTINATION_INDICATION,
1769 flow->reo_destination_indication);
1770 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1);
1771 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_9,
1772 L4_PROTOCOL), value);
1773
1774 return fse_offset;
1775 }
1776
1777 /**
1778 * hal_rx_flow_get_cmem_fse_ts_6750() - Get timestamp field from CMEM FSE
1779 * @hal_soc: hal_soc reference
1780 * @fse_offset: CMEM FSE offset
1781 *
1782 * Return: Timestamp
1783 */
hal_rx_flow_get_cmem_fse_ts_6750(struct hal_soc * hal_soc,uint32_t fse_offset)1784 static uint32_t hal_rx_flow_get_cmem_fse_ts_6750(struct hal_soc *hal_soc,
1785 uint32_t fse_offset)
1786 {
1787 return HAL_CMEM_READ(hal_soc, fse_offset +
1788 HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP));
1789 }
1790
1791 /**
1792 * hal_rx_flow_get_cmem_fse_6750() - Get FSE from CMEM
1793 * @hal_soc: hal_soc reference
1794 * @fse_offset: CMEM FSE offset
1795 * @fse: reference where FSE will be copied
1796 * @len: length of FSE
1797 *
1798 * Return: If read is successful or not
1799 */
1800 static void
hal_rx_flow_get_cmem_fse_6750(struct hal_soc * hal_soc,uint32_t fse_offset,uint32_t * fse,qdf_size_t len)1801 hal_rx_flow_get_cmem_fse_6750(struct hal_soc *hal_soc, uint32_t fse_offset,
1802 uint32_t *fse, qdf_size_t len)
1803 {
1804 int i;
1805
1806 if (len != HAL_RX_FST_ENTRY_SIZE)
1807 return;
1808
1809 for (i = 0; i < NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY; i++)
1810 fse[i] = HAL_CMEM_READ(hal_soc, fse_offset + i * 4);
1811 }
1812
1813 /**
1814 * hal_rx_msdu_get_reo_destination_indication_6750() - API to get
1815 * reo_destination_indication from rx_msdu_end TLV
1816 * @buf: pointer to the start of RX PKT TLV headers
1817 * @reo_destination_indication: pointer to return value of reo_destination_indication
1818 *
1819 * Return: none
1820 */
1821 static void
hal_rx_msdu_get_reo_destination_indication_6750(uint8_t * buf,uint32_t * reo_destination_indication)1822 hal_rx_msdu_get_reo_destination_indication_6750(uint8_t *buf,
1823 uint32_t *reo_destination_indication)
1824 {
1825 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1826 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1827
1828 *reo_destination_indication = HAL_RX_MSDU_END_REO_DEST_IND_GET(msdu_end);
1829 }
1830
1831 static
hal_compute_reo_remap_ix2_ix3_6750(uint32_t * ring,uint32_t num_rings,uint32_t * remap1,uint32_t * remap2)1832 void hal_compute_reo_remap_ix2_ix3_6750(uint32_t *ring, uint32_t num_rings,
1833 uint32_t *remap1, uint32_t *remap2)
1834 {
1835 switch (num_rings) {
1836 case 3:
1837 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1838 HAL_REO_REMAP_IX2(ring[1], 17) |
1839 HAL_REO_REMAP_IX2(ring[2], 18) |
1840 HAL_REO_REMAP_IX2(ring[0], 19) |
1841 HAL_REO_REMAP_IX2(ring[1], 20) |
1842 HAL_REO_REMAP_IX2(ring[2], 21) |
1843 HAL_REO_REMAP_IX2(ring[0], 22) |
1844 HAL_REO_REMAP_IX2(ring[1], 23);
1845
1846 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) |
1847 HAL_REO_REMAP_IX3(ring[0], 25) |
1848 HAL_REO_REMAP_IX3(ring[1], 26) |
1849 HAL_REO_REMAP_IX3(ring[2], 27) |
1850 HAL_REO_REMAP_IX3(ring[0], 28) |
1851 HAL_REO_REMAP_IX3(ring[1], 29) |
1852 HAL_REO_REMAP_IX3(ring[2], 30) |
1853 HAL_REO_REMAP_IX3(ring[0], 31);
1854 break;
1855 case 4:
1856 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1857 HAL_REO_REMAP_IX2(ring[1], 17) |
1858 HAL_REO_REMAP_IX2(ring[2], 18) |
1859 HAL_REO_REMAP_IX2(ring[3], 19) |
1860 HAL_REO_REMAP_IX2(ring[0], 20) |
1861 HAL_REO_REMAP_IX2(ring[1], 21) |
1862 HAL_REO_REMAP_IX2(ring[2], 22) |
1863 HAL_REO_REMAP_IX2(ring[3], 23);
1864
1865 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
1866 HAL_REO_REMAP_IX3(ring[1], 25) |
1867 HAL_REO_REMAP_IX3(ring[2], 26) |
1868 HAL_REO_REMAP_IX3(ring[3], 27) |
1869 HAL_REO_REMAP_IX3(ring[0], 28) |
1870 HAL_REO_REMAP_IX3(ring[1], 29) |
1871 HAL_REO_REMAP_IX3(ring[2], 30) |
1872 HAL_REO_REMAP_IX3(ring[3], 31);
1873 break;
1874 }
1875 }
1876
1877 static
hal_compute_reo_remap_ix0_6750(uint32_t * remap0)1878 void hal_compute_reo_remap_ix0_6750(uint32_t *remap0)
1879 {
1880 *remap0 = HAL_REO_REMAP_IX0(REO_REMAP_SW1, 0) |
1881 HAL_REO_REMAP_IX0(REO_REMAP_SW1, 1) |
1882 HAL_REO_REMAP_IX0(REO_REMAP_SW2, 2) |
1883 HAL_REO_REMAP_IX0(REO_REMAP_SW3, 3) |
1884 HAL_REO_REMAP_IX0(REO_REMAP_SW2, 4) |
1885 HAL_REO_REMAP_IX0(REO_REMAP_RELEASE, 5) |
1886 HAL_REO_REMAP_IX0(REO_REMAP_FW, 6) |
1887 HAL_REO_REMAP_IX0(REO_REMAP_FW, 7);
1888 }
1889
1890 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
1891 /**
1892 * hal_get_first_wow_wakeup_packet_6750() - Function to retrieve
1893 * rx_msdu_end_1_reserved_1a
1894 * @buf: Network buffer
1895 *
1896 * reserved_1a is used by target to tag the first packet that wakes up host from
1897 * WoW
1898 *
1899 * Dummy function for QCA6750
1900 *
1901 * Return: 1 to indicate it is first packet received that wakes up host from
1902 * WoW. Otherwise 0
1903 */
hal_get_first_wow_wakeup_packet_6750(uint8_t * buf)1904 static inline uint8_t hal_get_first_wow_wakeup_packet_6750(uint8_t *buf)
1905 {
1906 return 0;
1907 }
1908 #endif
1909
hal_hw_txrx_ops_attach_qca6750(struct hal_soc * hal_soc)1910 static void hal_hw_txrx_ops_attach_qca6750(struct hal_soc *hal_soc)
1911 {
1912 /* init and setup */
1913 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
1914 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
1915 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
1916 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li;
1917 hal_soc->ops->hal_get_window_address = hal_get_window_address_6750;
1918 hal_soc->ops->hal_reo_set_err_dst_remap = hal_reo_set_err_dst_remap_6750;
1919
1920 /* tx */
1921 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
1922 hal_tx_desc_set_dscp_tid_table_id_6750;
1923 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6750;
1924 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6750;
1925 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6750;
1926 hal_soc->ops->hal_tx_desc_set_buf_addr =
1927 hal_tx_desc_set_buf_addr_generic_li;
1928 hal_soc->ops->hal_tx_desc_set_search_type =
1929 hal_tx_desc_set_search_type_generic_li;
1930 hal_soc->ops->hal_tx_desc_set_search_index =
1931 hal_tx_desc_set_search_index_generic_li;
1932 hal_soc->ops->hal_tx_desc_set_cache_set_num =
1933 hal_tx_desc_set_cache_set_num_generic_li;
1934 hal_soc->ops->hal_tx_comp_get_status =
1935 hal_tx_comp_get_status_generic_li;
1936 hal_soc->ops->hal_tx_comp_get_release_reason =
1937 hal_tx_comp_get_release_reason_generic_li;
1938 hal_soc->ops->hal_get_wbm_internal_error =
1939 hal_get_wbm_internal_error_generic_li;
1940 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6750;
1941 hal_soc->ops->hal_tx_init_cmd_credit_ring =
1942 hal_tx_init_cmd_credit_ring_6750;
1943
1944 /* rx */
1945 hal_soc->ops->hal_rx_msdu_start_nss_get =
1946 hal_rx_msdu_start_nss_get_6750;
1947 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
1948 hal_rx_mon_hw_desc_get_mpdu_status_6750;
1949 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6750;
1950 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
1951 hal_rx_proc_phyrx_other_receive_info_tlv_6750;
1952
1953 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6750;
1954 hal_soc->ops->hal_rx_dump_rx_attention_tlv =
1955 hal_rx_dump_rx_attention_tlv_generic_li;
1956 hal_soc->ops->hal_rx_dump_msdu_start_tlv =
1957 hal_rx_dump_msdu_start_tlv_6750;
1958 hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
1959 hal_rx_dump_mpdu_start_tlv_generic_li;
1960 hal_soc->ops->hal_rx_dump_mpdu_end_tlv =
1961 hal_rx_dump_mpdu_end_tlv_generic_li;
1962 hal_soc->ops->hal_rx_dump_pkt_hdr_tlv =
1963 hal_rx_dump_pkt_hdr_tlv_generic_li;
1964
1965 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6750;
1966 hal_soc->ops->hal_rx_mpdu_start_tid_get =
1967 hal_rx_mpdu_start_tid_get_6750;
1968 hal_soc->ops->hal_rx_msdu_start_reception_type_get =
1969 hal_rx_msdu_start_reception_type_get_6750;
1970 hal_soc->ops->hal_rx_msdu_end_da_idx_get =
1971 hal_rx_msdu_end_da_idx_get_6750;
1972 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
1973 hal_rx_msdu_desc_info_get_ptr_6750;
1974 hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
1975 hal_rx_link_desc_msdu0_ptr_6750;
1976 hal_soc->ops->hal_reo_status_get_header =
1977 hal_reo_status_get_header_6750;
1978 hal_soc->ops->hal_rx_status_get_tlv_info =
1979 hal_rx_status_get_tlv_info_generic_li;
1980 hal_soc->ops->hal_rx_wbm_err_info_get =
1981 hal_rx_wbm_err_info_get_generic_li;
1982
1983 hal_soc->ops->hal_tx_set_pcp_tid_map =
1984 hal_tx_set_pcp_tid_map_generic_li;
1985 hal_soc->ops->hal_tx_update_pcp_tid_map =
1986 hal_tx_update_pcp_tid_generic_li;
1987 hal_soc->ops->hal_tx_set_tidmap_prty =
1988 hal_tx_update_tidmap_prty_generic_li;
1989 hal_soc->ops->hal_rx_get_rx_fragment_number =
1990 hal_rx_get_rx_fragment_number_6750;
1991 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
1992 hal_rx_msdu_end_da_is_mcbc_get_6750;
1993 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
1994 hal_rx_msdu_end_sa_is_valid_get_6750;
1995 hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
1996 hal_rx_msdu_end_sa_idx_get_6750;
1997 hal_soc->ops->hal_rx_desc_is_first_msdu =
1998 hal_rx_desc_is_first_msdu_6750;
1999 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
2000 hal_rx_msdu_end_l3_hdr_padding_get_6750;
2001 hal_soc->ops->hal_rx_tlv_l3_type_get = hal_rx_tlv_l3_type_get_6750;
2002 hal_soc->ops->hal_rx_encryption_info_valid =
2003 hal_rx_encryption_info_valid_6750;
2004 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6750;
2005 hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
2006 hal_rx_msdu_end_first_msdu_get_6750;
2007 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
2008 hal_rx_msdu_end_da_is_valid_get_6750;
2009 hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
2010 hal_rx_msdu_end_last_msdu_get_6750;
2011 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
2012 hal_rx_get_mpdu_mac_ad4_valid_6750;
2013 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
2014 hal_rx_mpdu_start_sw_peer_id_get_6750;
2015 hal_soc->ops->hal_rx_tlv_peer_meta_data_get =
2016 hal_rx_mpdu_peer_meta_data_get_li;
2017 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6750;
2018 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6750;
2019 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
2020 hal_rx_get_mpdu_frame_control_valid_6750;
2021 hal_soc->ops->hal_rx_get_frame_ctrl_field =
2022 hal_rx_get_frame_ctrl_field_li;
2023 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6750;
2024 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6750;
2025 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6750;
2026 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6750;
2027 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
2028 hal_rx_get_mpdu_sequence_control_valid_6750;
2029 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6750;
2030 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6750;
2031 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
2032 hal_rx_hw_desc_get_ppduid_get_6750;
2033 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
2034 hal_rx_msdu0_buffer_addr_lsb_6750;
2035 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
2036 hal_rx_msdu_desc_info_ptr_get_6750;
2037 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6750;
2038 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6750;
2039 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6750;
2040 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6750;
2041 hal_soc->ops->hal_rx_get_mac_addr2_valid =
2042 hal_rx_get_mac_addr2_valid_6750;
2043 hal_soc->ops->hal_rx_get_filter_category =
2044 hal_rx_get_filter_category_6750;
2045 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6750;
2046 hal_soc->ops->hal_reo_config = hal_reo_config_6750;
2047 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6750;
2048 hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
2049 hal_rx_msdu_flow_idx_invalid_6750;
2050 hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
2051 hal_rx_msdu_flow_idx_timeout_6750;
2052 hal_soc->ops->hal_rx_msdu_fse_metadata_get =
2053 hal_rx_msdu_fse_metadata_get_6750;
2054 hal_soc->ops->hal_rx_msdu_cce_match_get =
2055 hal_rx_msdu_cce_match_get_li;
2056 hal_soc->ops->hal_rx_msdu_cce_metadata_get =
2057 hal_rx_msdu_cce_metadata_get_6750;
2058 hal_soc->ops->hal_rx_msdu_get_flow_params =
2059 hal_rx_msdu_get_flow_params_6750;
2060 hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
2061 hal_rx_tlv_get_tcp_chksum_6750;
2062 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6750;
2063 #if defined(QCA_WIFI_QCA6750) && defined(WLAN_CFR_ENABLE) && \
2064 defined(WLAN_ENH_CFR_ENABLE)
2065 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_6750;
2066 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_6750;
2067 #endif
2068 /* rx - msdu end fast path info fields */
2069 hal_soc->ops->hal_rx_msdu_packet_metadata_get =
2070 hal_rx_msdu_packet_metadata_get_generic_li;
2071 hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum =
2072 hal_rx_get_fisa_cumulative_l4_checksum_6750;
2073 hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length =
2074 hal_rx_get_fisa_cumulative_ip_length_6750;
2075 hal_soc->ops->hal_rx_get_udp_proto = hal_rx_get_udp_proto_6750;
2076 hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation =
2077 hal_rx_get_flow_agg_continuation_6750;
2078 hal_soc->ops->hal_rx_get_fisa_flow_agg_count =
2079 hal_rx_get_flow_agg_count_6750;
2080 hal_soc->ops->hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_6750;
2081 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
2082 hal_rx_mpdu_start_tlv_tag_valid_6750;
2083
2084 /* rx - TLV struct offsets */
2085 hal_soc->ops->hal_rx_msdu_end_offset_get =
2086 hal_rx_msdu_end_offset_get_generic;
2087 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
2088 hal_soc->ops->hal_rx_msdu_start_offset_get =
2089 hal_rx_msdu_start_offset_get_generic;
2090 hal_soc->ops->hal_rx_mpdu_start_offset_get =
2091 hal_rx_mpdu_start_offset_get_generic;
2092 hal_soc->ops->hal_rx_mpdu_end_offset_get =
2093 hal_rx_mpdu_end_offset_get_generic;
2094 #ifndef NO_RX_PKT_HDR_TLV
2095 hal_soc->ops->hal_rx_pkt_tlv_offset_get =
2096 hal_rx_pkt_tlv_offset_get_generic;
2097 #endif
2098 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6750;
2099 hal_soc->ops->hal_rx_flow_get_tuple_info =
2100 hal_rx_flow_get_tuple_info_li;
2101 hal_soc->ops->hal_rx_flow_delete_entry =
2102 hal_rx_flow_delete_entry_li;
2103 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li;
2104 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
2105 hal_compute_reo_remap_ix2_ix3_6750;
2106
2107 /* CMEM FSE */
2108 hal_soc->ops->hal_rx_flow_setup_cmem_fse =
2109 hal_rx_flow_setup_cmem_fse_6750;
2110 hal_soc->ops->hal_rx_flow_get_cmem_fse_ts =
2111 hal_rx_flow_get_cmem_fse_ts_6750;
2112 hal_soc->ops->hal_rx_flow_get_cmem_fse = hal_rx_flow_get_cmem_fse_6750;
2113 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication =
2114 hal_rx_msdu_get_reo_destination_indication_6750;
2115 hal_soc->ops->hal_setup_link_idle_list =
2116 hal_setup_link_idle_list_generic_li;
2117 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
2118 hal_soc->ops->hal_get_first_wow_wakeup_packet =
2119 hal_get_first_wow_wakeup_packet_6750;
2120 #endif
2121 hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_li;
2122 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_li;
2123 hal_soc->ops->hal_rx_tlv_decrypt_err_get =
2124 hal_rx_tlv_decrypt_err_get_li;
2125 hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags =
2126 hal_rx_tlv_get_pkt_capture_flags_li;
2127 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get =
2128 hal_rx_mpdu_info_ampdu_flag_get_li;
2129 hal_soc->ops->hal_compute_reo_remap_ix0 =
2130 hal_compute_reo_remap_ix0_6750;
2131 hal_soc->ops->hal_rx_tlv_msdu_len_get =
2132 hal_rx_msdu_start_get_len_6750;
2133 };
2134
2135 struct hal_hw_srng_config hw_srng_table_6750[] = {
2136 /* TODO: max_rings can populated by querying HW capabilities */
2137 { /* REO_DST */
2138 .start_ring_id = HAL_SRNG_REO2SW1,
2139 .max_rings = 4,
2140 .entry_size = sizeof(struct reo_destination_ring) >> 2,
2141 .lmac_ring = FALSE,
2142 .ring_dir = HAL_SRNG_DST_RING,
2143 .reg_start = {
2144 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
2145 SEQ_WCSS_UMAC_REO_REG_OFFSET),
2146 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
2147 SEQ_WCSS_UMAC_REO_REG_OFFSET)
2148 },
2149 .reg_size = {
2150 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
2151 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
2152 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
2153 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
2154 },
2155 .max_size =
2156 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
2157 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
2158 },
2159 { /* REO_EXCEPTION */
2160 /* Designating REO2TCL ring as exception ring. This ring is
2161 * similar to other REO2SW rings though it is named as REO2TCL.
2162 * Any of theREO2SW rings can be used as exception ring.
2163 */
2164 .start_ring_id = HAL_SRNG_REO2TCL,
2165 .max_rings = 1,
2166 .entry_size = sizeof(struct reo_destination_ring) >> 2,
2167 .lmac_ring = FALSE,
2168 .ring_dir = HAL_SRNG_DST_RING,
2169 .reg_start = {
2170 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(
2171 SEQ_WCSS_UMAC_REO_REG_OFFSET),
2172 HWIO_REO_R2_REO2TCL_RING_HP_ADDR(
2173 SEQ_WCSS_UMAC_REO_REG_OFFSET)
2174 },
2175 /* Single ring - provide ring size if multiple rings of this
2176 * type are supported
2177 */
2178 .reg_size = {},
2179 .max_size =
2180 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >>
2181 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT,
2182 },
2183 { /* REO_REINJECT */
2184 .start_ring_id = HAL_SRNG_SW2REO,
2185 .max_rings = 1,
2186 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
2187 .lmac_ring = FALSE,
2188 .ring_dir = HAL_SRNG_SRC_RING,
2189 .reg_start = {
2190 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
2191 SEQ_WCSS_UMAC_REO_REG_OFFSET),
2192 HWIO_REO_R2_SW2REO_RING_HP_ADDR(
2193 SEQ_WCSS_UMAC_REO_REG_OFFSET)
2194 },
2195 /* Single ring - provide ring size if multiple rings of this
2196 * type are supported
2197 */
2198 .reg_size = {},
2199 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
2200 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
2201 },
2202 { /* REO_CMD */
2203 .start_ring_id = HAL_SRNG_REO_CMD,
2204 .max_rings = 1,
2205 .entry_size = (sizeof(struct tlv_32_hdr) +
2206 sizeof(struct reo_get_queue_stats)) >> 2,
2207 .lmac_ring = FALSE,
2208 .ring_dir = HAL_SRNG_SRC_RING,
2209 .reg_start = {
2210 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
2211 SEQ_WCSS_UMAC_REO_REG_OFFSET),
2212 HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
2213 SEQ_WCSS_UMAC_REO_REG_OFFSET),
2214 },
2215 /* Single ring - provide ring size if multiple rings of this
2216 * type are supported
2217 */
2218 .reg_size = {},
2219 .max_size =
2220 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
2221 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
2222 },
2223 { /* REO_STATUS */
2224 .start_ring_id = HAL_SRNG_REO_STATUS,
2225 .max_rings = 1,
2226 .entry_size = (sizeof(struct tlv_32_hdr) +
2227 sizeof(struct reo_get_queue_stats_status)) >> 2,
2228 .lmac_ring = FALSE,
2229 .ring_dir = HAL_SRNG_DST_RING,
2230 .reg_start = {
2231 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
2232 SEQ_WCSS_UMAC_REO_REG_OFFSET),
2233 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
2234 SEQ_WCSS_UMAC_REO_REG_OFFSET),
2235 },
2236 /* Single ring - provide ring size if multiple rings of this
2237 * type are supported
2238 */
2239 .reg_size = {},
2240 .max_size =
2241 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
2242 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
2243 },
2244 { /* TCL_DATA */
2245 .start_ring_id = HAL_SRNG_SW2TCL1,
2246 .max_rings = 3,
2247 .entry_size = (sizeof(struct tlv_32_hdr) +
2248 sizeof(struct tcl_data_cmd)) >> 2,
2249 .lmac_ring = FALSE,
2250 .ring_dir = HAL_SRNG_SRC_RING,
2251 .reg_start = {
2252 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
2253 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
2254 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
2255 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
2256 },
2257 .reg_size = {
2258 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
2259 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
2260 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
2261 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
2262 },
2263 .max_size =
2264 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
2265 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
2266 },
2267 { /* TCL_CMD */
2268 .start_ring_id = HAL_SRNG_SW2TCL_CMD,
2269 .max_rings = 1,
2270 .entry_size = (sizeof(struct tlv_32_hdr) +
2271 sizeof(struct tcl_gse_cmd)) >> 2,
2272 .lmac_ring = FALSE,
2273 .ring_dir = HAL_SRNG_SRC_RING,
2274 .reg_start = {
2275 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(
2276 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
2277 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(
2278 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
2279 },
2280 /* Single ring - provide ring size if multiple rings of this
2281 * type are supported
2282 */
2283 .reg_size = {},
2284 .max_size =
2285 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >>
2286 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT,
2287 },
2288 { /* TCL_STATUS */
2289 .start_ring_id = HAL_SRNG_TCL_STATUS,
2290 .max_rings = 1,
2291 .entry_size = (sizeof(struct tlv_32_hdr) +
2292 sizeof(struct tcl_status_ring)) >> 2,
2293 .lmac_ring = FALSE,
2294 .ring_dir = HAL_SRNG_DST_RING,
2295 .reg_start = {
2296 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
2297 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
2298 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
2299 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
2300 },
2301 /* Single ring - provide ring size if multiple rings of this
2302 * type are supported
2303 */
2304 .reg_size = {},
2305 .max_size =
2306 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
2307 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
2308 },
2309 { /* CE_SRC */
2310 .start_ring_id = HAL_SRNG_CE_0_SRC,
2311 .max_rings = 12,
2312 .entry_size = sizeof(struct ce_src_desc) >> 2,
2313 .lmac_ring = FALSE,
2314 .ring_dir = HAL_SRNG_SRC_RING,
2315 .reg_start = {
2316 HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,
2317 HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,
2318 },
2319 .reg_size = {
2320 HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR -
2321 HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,
2322 HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR -
2323 HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,
2324 },
2325 .max_size =
2326 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
2327 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT
2328 },
2329 { /* CE_DST */
2330 .start_ring_id = HAL_SRNG_CE_0_DST,
2331 .max_rings = 12,
2332 .entry_size = 8 >> 2,
2333 /*TODO: entry_size above should actually be
2334 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
2335 * of struct ce_dst_desc in HW header files
2336 */
2337 .lmac_ring = FALSE,
2338 .ring_dir = HAL_SRNG_SRC_RING,
2339 .reg_start = {
2340 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,
2341 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,
2342 },
2343 .reg_size = {
2344 HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR -
2345 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,
2346 HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR -
2347 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR
2348 },
2349 .max_size =
2350 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
2351 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT
2352 },
2353 { /* CE_DST_STATUS */
2354 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
2355 .max_rings = 12,
2356 .entry_size = sizeof(struct ce_stat_desc) >> 2,
2357 .lmac_ring = FALSE,
2358 .ring_dir = HAL_SRNG_DST_RING,
2359 .reg_start = {
2360 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,
2361 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,
2362 },
2363 /* TODO: check destination status ring registers */
2364 .reg_size = {
2365 HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR -
2366 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,
2367 HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR -
2368 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR
2369 },
2370 .max_size =
2371 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
2372 HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
2373 },
2374 { /* WBM_IDLE_LINK */
2375 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
2376 .max_rings = 1,
2377 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
2378 .lmac_ring = FALSE,
2379 .ring_dir = HAL_SRNG_SRC_RING,
2380 .reg_start = {
2381 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2382 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2383 },
2384 /* Single ring - provide ring size if multiple rings of this
2385 * type are supported
2386 */
2387 .reg_size = {},
2388 .max_size =
2389 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
2390 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
2391 },
2392 { /* SW2WBM_RELEASE */
2393 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
2394 .max_rings = 1,
2395 .entry_size = sizeof(struct wbm_release_ring) >> 2,
2396 .lmac_ring = FALSE,
2397 .ring_dir = HAL_SRNG_SRC_RING,
2398 .reg_start = {
2399 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2400 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2401 },
2402 /* Single ring - provide ring size if multiple rings of this
2403 * type are supported
2404 */
2405 .reg_size = {},
2406 .max_size =
2407 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
2408 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
2409 },
2410 { /* WBM2SW_RELEASE */
2411 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
2412 #if defined(TX_MULTI_TCL) || defined(CONFIG_PLD_IPCIE_FW_SIM)
2413 .max_rings = 5,
2414 #else
2415 .max_rings = 4,
2416 #endif
2417 .entry_size = sizeof(struct wbm_release_ring) >> 2,
2418 .lmac_ring = FALSE,
2419 .ring_dir = HAL_SRNG_DST_RING,
2420 .reg_start = {
2421 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2422 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2423 },
2424 .reg_size = {
2425 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
2426 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2427 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
2428 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2429 },
2430 .max_size =
2431 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
2432 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
2433 },
2434 { /* RXDMA_BUF */
2435 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
2436 #ifdef IPA_OFFLOAD
2437 .max_rings = 3,
2438 #else
2439 .max_rings = 2,
2440 #endif
2441 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
2442 .lmac_ring = TRUE,
2443 .ring_dir = HAL_SRNG_SRC_RING,
2444 /* reg_start is not set because LMAC rings are not accessed
2445 * from host
2446 */
2447 .reg_start = {},
2448 .reg_size = {},
2449 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2450 },
2451 { /* RXDMA_DST */
2452 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
2453 .max_rings = 1,
2454 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
2455 .lmac_ring = TRUE,
2456 .ring_dir = HAL_SRNG_DST_RING,
2457 /* reg_start is not set because LMAC rings are not accessed
2458 * from host
2459 */
2460 .reg_start = {},
2461 .reg_size = {},
2462 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2463 },
2464 { /* RXDMA_MONITOR_BUF */
2465 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
2466 .max_rings = 1,
2467 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
2468 .lmac_ring = TRUE,
2469 .ring_dir = HAL_SRNG_SRC_RING,
2470 /* reg_start is not set because LMAC rings are not accessed
2471 * from host
2472 */
2473 .reg_start = {},
2474 .reg_size = {},
2475 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2476 },
2477 { /* RXDMA_MONITOR_STATUS */
2478 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
2479 .max_rings = 1,
2480 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
2481 .lmac_ring = TRUE,
2482 .ring_dir = HAL_SRNG_SRC_RING,
2483 /* reg_start is not set because LMAC rings are not accessed
2484 * from host
2485 */
2486 .reg_start = {},
2487 .reg_size = {},
2488 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2489 },
2490 { /* RXDMA_MONITOR_DST */
2491 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1,
2492 .max_rings = 1,
2493 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
2494 .lmac_ring = TRUE,
2495 .ring_dir = HAL_SRNG_DST_RING,
2496 /* reg_start is not set because LMAC rings are not accessed
2497 * from host
2498 */
2499 .reg_start = {},
2500 .reg_size = {},
2501 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2502 },
2503 { /* RXDMA_MONITOR_DESC */
2504 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
2505 .max_rings = 1,
2506 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
2507 .lmac_ring = TRUE,
2508 .ring_dir = HAL_SRNG_SRC_RING,
2509 /* reg_start is not set because LMAC rings are not accessed
2510 * from host
2511 */
2512 .reg_start = {},
2513 .reg_size = {},
2514 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2515 },
2516 { /* DIR_BUF_RX_DMA_SRC */
2517 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
2518 /*
2519 * one ring is for spectral scan
2520 * the other is for cfr
2521 */
2522 .max_rings = 2,
2523 .entry_size = 2,
2524 .lmac_ring = TRUE,
2525 .ring_dir = HAL_SRNG_SRC_RING,
2526 /* reg_start is not set because LMAC rings are not accessed
2527 * from host
2528 */
2529 .reg_start = {},
2530 .reg_size = {},
2531 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2532 },
2533 #ifdef WLAN_FEATURE_CIF_CFR
2534 { /* WIFI_POS_SRC */
2535 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
2536 .max_rings = 1,
2537 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
2538 .lmac_ring = TRUE,
2539 .ring_dir = HAL_SRNG_SRC_RING,
2540 /* reg_start is not set because LMAC rings are not accessed
2541 * from host
2542 */
2543 .reg_start = {},
2544 .reg_size = {},
2545 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2546 },
2547 #endif
2548 { /* REO2PPE */ 0},
2549 { /* PPE2TCL */ 0},
2550 { /* PPE_RELEASE */ 0},
2551 { /* TX_MONITOR_BUF */ 0},
2552 { /* TX_MONITOR_DST */ 0},
2553 { /* SW2RXDMA_NEW */ 0},
2554 { /* SW2RXDMA_LINK_RELEASE */ 0},
2555 };
2556
2557 /**
2558 * hal_qca6750_attach() - Attach 6750 target specific hal_soc ops,
2559 * offset and srng table
2560 * @hal_soc: HAL SoC context
2561 */
hal_qca6750_attach(struct hal_soc * hal_soc)2562 void hal_qca6750_attach(struct hal_soc *hal_soc)
2563 {
2564 hal_soc->hw_srng_table = hw_srng_table_6750;
2565 hal_srng_hw_reg_offset_init_generic(hal_soc);
2566 hal_hw_txrx_default_ops_attach_li(hal_soc);
2567 hal_hw_txrx_ops_attach_qca6750(hal_soc);
2568 }
2569