1 /*
2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for
6 * any purpose with or without fee is hereby granted, provided that the
7 * above copyright notice and this permission notice appear in all
8 * copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17 * PERFORMANCE OF THIS SOFTWARE.
18 */
19 #include "qdf_util.h"
20 #include "qdf_types.h"
21 #include "qdf_lock.h"
22 #include "qdf_mem.h"
23 #include "qdf_nbuf.h"
24 #include "tcl_data_cmd.h"
25 #include "mac_tcl_reg_seq_hwioreg.h"
26 #include "phyrx_rssi_legacy.h"
27 #include "rx_msdu_start.h"
28 #include "tlv_tag_def.h"
29 #include "hal_hw_headers.h"
30 #include "hal_internal.h"
31 #include "cdp_txrx_mon_struct.h"
32 #include "qdf_trace.h"
33 #include "hal_li_rx.h"
34 #include "hal_tx.h"
35 #include "dp_types.h"
36 #include "hal_api_mon.h"
37 #include "phyrx_other_receive_info_ru_details.h"
38
39 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \
40 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
41 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \
42 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \
43 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB))
44
45 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
46 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
47 RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \
48 RX_MSDU_END_5_DA_IS_MCBC_MASK, \
49 RX_MSDU_END_5_DA_IS_MCBC_LSB))
50
51 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \
52 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
53 RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \
54 RX_MSDU_END_5_SA_IS_VALID_MASK, \
55 RX_MSDU_END_5_SA_IS_VALID_LSB))
56
57 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \
58 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
59 RX_MSDU_END_13_SA_IDX_OFFSET)), \
60 RX_MSDU_END_13_SA_IDX_MASK, \
61 RX_MSDU_END_13_SA_IDX_LSB))
62
63 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \
64 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
65 RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \
66 RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \
67 RX_MSDU_END_5_L3_HEADER_PADDING_LSB))
68
69 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \
70 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
71 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \
72 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \
73 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB))
74
75 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \
76 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
77 RX_MPDU_INFO_4_PN_31_0_OFFSET)), \
78 RX_MPDU_INFO_4_PN_31_0_MASK, \
79 RX_MPDU_INFO_4_PN_31_0_LSB))
80
81 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \
82 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
83 RX_MPDU_INFO_5_PN_63_32_OFFSET)), \
84 RX_MPDU_INFO_5_PN_63_32_MASK, \
85 RX_MPDU_INFO_5_PN_63_32_LSB))
86
87 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \
88 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
89 RX_MPDU_INFO_6_PN_95_64_OFFSET)), \
90 RX_MPDU_INFO_6_PN_95_64_MASK, \
91 RX_MPDU_INFO_6_PN_95_64_LSB))
92
93 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \
94 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
95 RX_MPDU_INFO_7_PN_127_96_OFFSET)), \
96 RX_MPDU_INFO_7_PN_127_96_MASK, \
97 RX_MPDU_INFO_7_PN_127_96_LSB))
98
99 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \
100 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
101 RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \
102 RX_MSDU_END_5_FIRST_MSDU_MASK, \
103 RX_MSDU_END_5_FIRST_MSDU_LSB))
104
105 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \
106 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
107 RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \
108 RX_MSDU_END_5_DA_IS_VALID_MASK, \
109 RX_MSDU_END_5_DA_IS_VALID_LSB))
110
111 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \
112 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
113 RX_MSDU_END_5_LAST_MSDU_OFFSET)), \
114 RX_MSDU_END_5_LAST_MSDU_MASK, \
115 RX_MSDU_END_5_LAST_MSDU_LSB))
116
117 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \
118 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
119 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \
120 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \
121 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB))
122
123 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \
124 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
125 RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \
126 RX_MPDU_INFO_1_SW_PEER_ID_MASK, \
127 RX_MPDU_INFO_1_SW_PEER_ID_LSB))
128
129 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \
130 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
131 RX_MPDU_INFO_2_TO_DS_OFFSET)), \
132 RX_MPDU_INFO_2_TO_DS_MASK, \
133 RX_MPDU_INFO_2_TO_DS_LSB))
134
135 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \
136 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
137 RX_MPDU_INFO_2_FR_DS_OFFSET)), \
138 RX_MPDU_INFO_2_FR_DS_MASK, \
139 RX_MPDU_INFO_2_FR_DS_LSB))
140
141 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \
142 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
143 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \
144 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \
145 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB))
146
147 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \
148 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
149 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \
150 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \
151 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB))
152
153 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \
154 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
155 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \
156 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \
157 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB))
158
159 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \
160 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
161 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \
162 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \
163 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB))
164
165 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \
166 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
167 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \
168 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \
169 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB))
170
171 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \
172 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
173 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \
174 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \
175 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB))
176
177 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \
178 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
179 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \
180 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \
181 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB))
182
183 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \
184 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
185 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \
186 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \
187 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB))
188
189 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \
190 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
191 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \
192 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \
193 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB))
194
195 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \
196 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
197 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \
198 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \
199 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB))
200
201 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \
202 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
203 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \
204 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \
205 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB))
206
207 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \
208 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
209 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \
210 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \
211 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB))
212
213 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \
214 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
215 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \
216 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \
217 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB))
218
219 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \
220 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
221 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \
222 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \
223 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB))
224
225 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \
226 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
227 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), \
228 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, \
229 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB))
230
231 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \
232 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
233 RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \
234 RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \
235 RX_MSDU_END_16_SA_SW_PEER_ID_LSB))
236
237 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
238 (uint8_t *)(link_desc_va) + \
239 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
240
241 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \
242 (uint8_t *)(msdu0) + \
243 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
244
245 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \
246 (uint8_t *)(ent_ring_desc) + \
247 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
248
249 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \
250 (uint8_t *)(dst_ring_desc) + \
251 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
252
253 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \
254 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MPDU_FRAME_CONTROL_VALID)
255
256 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \
257 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, TO_DS)
258
259 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \
260 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD1_VALID)
261
262 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \
263 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD2_VALID)
264
265 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \
266 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, RXPCU_MPDU_FILTER_IN_CATEGORY)
267
268 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \
269 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, PHY_PPDU_ID)
270
271 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \
272 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, SW_FRAME_GROUP_ID)
273
274 #define HAL_RX_GET_SW_PEER_ID(rx_mpdu_start) \
275 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_1, SW_PEER_ID)
276
277 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \
278 do { \
279 (reg_val) &= \
280 ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |\
281 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\
282 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK);\
283 (reg_val) |= \
284 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
285 FRAGMENT_DEST_RING, \
286 (reo_params)->frag_dst_ring) | \
287 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
288 AGING_LIST_ENABLE, 1) |\
289 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
290 AGING_FLUSH_ENABLE, 1);\
291 HAL_REG_WRITE((soc), \
292 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \
293 SEQ_WCSS_UMAC_REO_REG_OFFSET), \
294 (reg_val)); \
295 } while (0)
296
297 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \
298 ((struct rx_msdu_desc_info *) \
299 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \
300 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET))
301
302 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \
303 ((struct rx_msdu_details *) \
304 _OFFSET_TO_BYTE_PTR((link_desc),\
305 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET))
306
307 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \
308 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
309 RX_MSDU_END_14_FLOW_IDX_OFFSET)), \
310 RX_MSDU_END_14_FLOW_IDX_MASK, \
311 RX_MSDU_END_14_FLOW_IDX_LSB))
312
313 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \
314 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
315 RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET)), \
316 RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \
317 RX_MSDU_END_5_FLOW_IDX_INVALID_LSB))
318
319 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \
320 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
321 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \
322 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \
323 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB))
324
325 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \
326 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
327 RX_MSDU_END_15_FSE_METADATA_OFFSET)), \
328 RX_MSDU_END_15_FSE_METADATA_MASK, \
329 RX_MSDU_END_15_FSE_METADATA_LSB))
330
331 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \
332 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
333 RX_MSDU_END_16_CCE_METADATA_OFFSET)), \
334 RX_MSDU_END_16_CCE_METADATA_MASK, \
335 RX_MSDU_END_16_CCE_METADATA_LSB))
336
337 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \
338 (_HAL_MS( \
339 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
340 msdu_end_tlv.rx_msdu_end), \
341 RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \
342 RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \
343 RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB))
344
345 #if defined(QCA_WIFI_QCA6290_11AX)
346 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
347 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
348 RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \
349 RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \
350 RX_MSDU_START_5_MIMO_SS_BITMAP_LSB))
351
352 /**
353 * hal_rx_msdu_start_nss_get_6290() - API to get the NSS Interval from
354 * rx_msdu_start
355 * @buf: pointer to the start of RX PKT TLV header
356 *
357 * Return: uint32_t(nss)
358 */
359 static uint32_t
hal_rx_msdu_start_nss_get_6290(uint8_t * buf)360 hal_rx_msdu_start_nss_get_6290(uint8_t *buf)
361 {
362 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
363 struct rx_msdu_start *msdu_start =
364 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
365 uint8_t mimo_ss_bitmap;
366
367 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start);
368
369 return qdf_get_hweight8(mimo_ss_bitmap);
370 }
371 #else
372 static uint32_t
hal_rx_msdu_start_nss_get_6290(uint8_t * buf)373 hal_rx_msdu_start_nss_get_6290(uint8_t *buf)
374 {
375 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
376 struct rx_msdu_start *msdu_start =
377 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
378 uint32_t nss;
379
380 nss = HAL_RX_MSDU_START_NSS_GET(msdu_start);
381 return nss;
382 }
383 #endif
384
385 /**
386 * hal_rx_mon_hw_desc_get_mpdu_status_6290() - Retrieve MPDU status
387 * @hw_desc_addr: Start address of Rx HW TLVs
388 * @rs: Status for monitor mode
389 *
390 * Return: void
391 */
hal_rx_mon_hw_desc_get_mpdu_status_6290(void * hw_desc_addr,struct mon_rx_status * rs)392 static void hal_rx_mon_hw_desc_get_mpdu_status_6290(void *hw_desc_addr,
393 struct mon_rx_status *rs)
394 {
395 struct rx_msdu_start *rx_msdu_start;
396 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
397 uint32_t reg_value;
398 const uint32_t sgi_hw_to_cdp[] = {
399 CDP_SGI_0_8_US,
400 CDP_SGI_0_4_US,
401 CDP_SGI_1_6_US,
402 CDP_SGI_3_2_US,
403 };
404
405 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
406
407 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs);
408
409 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start,
410 RX_MSDU_START_5, USER_RSSI);
411 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC);
412
413 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI);
414 rs->sgi = sgi_hw_to_cdp[reg_value];
415 #if !defined(QCA_WIFI_QCA6290_11AX)
416 rs->nr_ant = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, NSS);
417 #endif
418 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE);
419 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0;
420 /* TODO: rs->beamformed should be set for SU beamforming also */
421 }
422
423 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
424
hal_get_link_desc_size_6290(void)425 static uint32_t hal_get_link_desc_size_6290(void)
426 {
427 return LINK_DESC_SIZE;
428 }
429
430
431 #ifdef QCA_WIFI_QCA6290_11AX
432 /**
433 * hal_rx_get_tlv_6290() - API to get the tlv
434 * @rx_tlv: TLV data extracted from the rx packet
435 *
436 * Return: uint8_t
437 */
hal_rx_get_tlv_6290(void * rx_tlv)438 static uint8_t hal_rx_get_tlv_6290(void *rx_tlv)
439 {
440 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH);
441 }
442 #else
hal_rx_get_tlv_6290(void * rx_tlv)443 static uint8_t hal_rx_get_tlv_6290(void *rx_tlv)
444 {
445 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_35, RECEIVE_BANDWIDTH);
446 }
447 #endif
448
449 #ifdef QCA_WIFI_QCA6290_11AX
450 /**
451 * hal_rx_proc_phyrx_other_receive_info_tlv_6290()
452 * - process other receive info TLV
453 * @rx_tlv_hdr: pointer to TLV header
454 * @ppdu_info_handle: pointer to ppdu_info
455 *
456 * Return: None
457 */
458 static
hal_rx_proc_phyrx_other_receive_info_tlv_6290(void * rx_tlv_hdr,void * ppdu_info_handle)459 void hal_rx_proc_phyrx_other_receive_info_tlv_6290(void *rx_tlv_hdr,
460 void *ppdu_info_handle)
461 {
462 uint32_t tlv_tag, tlv_len;
463 uint32_t temp_len, other_tlv_len, other_tlv_tag;
464 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
465 void *other_tlv_hdr = NULL;
466 void *other_tlv = NULL;
467 uint32_t ru_details_channel_0;
468 struct hal_rx_ppdu_info *ppdu_info =
469 (struct hal_rx_ppdu_info *)ppdu_info_handle;
470
471 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
472 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
473 temp_len = 0;
474
475 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE;
476
477 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr);
478 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr);
479 temp_len += other_tlv_len;
480 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
481
482 switch (other_tlv_tag) {
483 case WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E:
484 ru_details_channel_0 =
485 HAL_RX_GET(other_tlv,
486 PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0,
487 RU_DETAILS_CHANNEL_0);
488
489 qdf_mem_copy(ppdu_info->rx_status.he_RU,
490 &ru_details_channel_0,
491 sizeof(ppdu_info->rx_status.he_RU));
492
493 if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_20) {
494 ppdu_info->rx_status.he_sig_b_common_known |=
495 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0;
496 }
497 if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_40) {
498 ppdu_info->rx_status.he_sig_b_common_known |=
499 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU1;
500 }
501 if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_80) {
502 ppdu_info->rx_status.he_sig_b_common_known |=
503 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU2;
504 }
505 if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_160) {
506 ppdu_info->rx_status.he_sig_b_common_known |=
507 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU3;
508 }
509 break;
510 default:
511 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
512 "%s unhandled TLV type: %d, TLV len:%d",
513 __func__, other_tlv_tag, other_tlv_len);
514 break;
515 }
516 }
517 #else
518 static
hal_rx_proc_phyrx_other_receive_info_tlv_6290(void * rx_tlv_hdr,void * ppdu_info_handle)519 void hal_rx_proc_phyrx_other_receive_info_tlv_6290(void *rx_tlv_hdr,
520 void *ppdu_info_handle)
521 {
522 }
523 #endif /* QCA_WIFI_QCA6290_11AX */
524
525 /**
526 * hal_rx_dump_msdu_start_tlv_6290() - dump RX msdu_start TLV in structured
527 * human readable format.
528 * @pkttlvs: pointer to the pkttlvs.
529 * @dbg_level: log level.
530 *
531 * Return: void
532 */
hal_rx_dump_msdu_start_tlv_6290(void * pkttlvs,uint8_t dbg_level)533 static void hal_rx_dump_msdu_start_tlv_6290(void *pkttlvs,
534 uint8_t dbg_level)
535 {
536 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
537 struct rx_msdu_start *msdu_start =
538 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
539
540 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
541 "rx_msdu_start tlv - "
542 "rxpcu_mpdu_filter_in_category: %d "
543 "sw_frame_group_id: %d "
544 "phy_ppdu_id: %d "
545 "msdu_length: %d "
546 "ipsec_esp: %d "
547 "l3_offset: %d "
548 "ipsec_ah: %d "
549 "l4_offset: %d "
550 "msdu_number: %d "
551 "decap_format: %d "
552 "ipv4_proto: %d "
553 "ipv6_proto: %d "
554 "tcp_proto: %d "
555 "udp_proto: %d "
556 "ip_frag: %d "
557 "tcp_only_ack: %d "
558 "da_is_bcast_mcast: %d "
559 "ip4_protocol_ip6_next_header: %d "
560 "toeplitz_hash_2_or_4: %d "
561 "flow_id_toeplitz: %d "
562 "user_rssi: %d "
563 "pkt_type: %d "
564 "stbc: %d "
565 "sgi: %d "
566 "rate_mcs: %d "
567 "receive_bandwidth: %d "
568 "reception_type: %d "
569 #if !defined(QCA_WIFI_QCA6290_11AX)
570 "toeplitz_hash: %d "
571 "nss: %d "
572 #endif
573 "ppdu_start_timestamp: %d "
574 "sw_phy_meta_data: %d ",
575 msdu_start->rxpcu_mpdu_filter_in_category,
576 msdu_start->sw_frame_group_id,
577 msdu_start->phy_ppdu_id,
578 msdu_start->msdu_length,
579 msdu_start->ipsec_esp,
580 msdu_start->l3_offset,
581 msdu_start->ipsec_ah,
582 msdu_start->l4_offset,
583 msdu_start->msdu_number,
584 msdu_start->decap_format,
585 msdu_start->ipv4_proto,
586 msdu_start->ipv6_proto,
587 msdu_start->tcp_proto,
588 msdu_start->udp_proto,
589 msdu_start->ip_frag,
590 msdu_start->tcp_only_ack,
591 msdu_start->da_is_bcast_mcast,
592 msdu_start->ip4_protocol_ip6_next_header,
593 msdu_start->toeplitz_hash_2_or_4,
594 msdu_start->flow_id_toeplitz,
595 msdu_start->user_rssi,
596 msdu_start->pkt_type,
597 msdu_start->stbc,
598 msdu_start->sgi,
599 msdu_start->rate_mcs,
600 msdu_start->receive_bandwidth,
601 msdu_start->reception_type,
602 #if !defined(QCA_WIFI_QCA6290_11AX)
603 msdu_start->toeplitz_hash,
604 msdu_start->nss,
605 #endif
606 msdu_start->ppdu_start_timestamp,
607 msdu_start->sw_phy_meta_data);
608 }
609
610 /**
611 * hal_rx_dump_msdu_end_tlv_6290() - dump RX msdu_end TLV in structured
612 * human readable format.
613 * @pkttlvs: pointer to the pkttlvs.
614 * @dbg_level: log level.
615 *
616 * Return: void
617 */
hal_rx_dump_msdu_end_tlv_6290(void * pkttlvs,uint8_t dbg_level)618 static void hal_rx_dump_msdu_end_tlv_6290(void *pkttlvs,
619 uint8_t dbg_level)
620 {
621 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
622 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
623
624 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
625 "rx_msdu_end tlv - "
626 "rxpcu_mpdu_filter_in_category: %d "
627 "sw_frame_group_id: %d "
628 "phy_ppdu_id: %d "
629 "ip_hdr_chksum: %d "
630 "tcp_udp_chksum: %d "
631 "key_id_octet: %d "
632 "cce_super_rule: %d "
633 "cce_classify_not_done_truncat: %d "
634 "cce_classify_not_done_cce_dis: %d "
635 "ext_wapi_pn_63_48: %d "
636 "ext_wapi_pn_95_64: %d "
637 "ext_wapi_pn_127_96: %d "
638 "reported_mpdu_length: %d "
639 "first_msdu: %d "
640 "last_msdu: %d "
641 "sa_idx_timeout: %d "
642 "da_idx_timeout: %d "
643 "msdu_limit_error: %d "
644 "flow_idx_timeout: %d "
645 "flow_idx_invalid: %d "
646 "wifi_parser_error: %d "
647 "amsdu_parser_error: %d "
648 "sa_is_valid: %d "
649 "da_is_valid: %d "
650 "da_is_mcbc: %d "
651 "l3_header_padding: %d "
652 "ipv6_options_crc: %d "
653 "tcp_seq_number: %d "
654 "tcp_ack_number: %d "
655 "tcp_flag: %d "
656 "lro_eligible: %d "
657 "window_size: %d "
658 "da_offset: %d "
659 "sa_offset: %d "
660 "da_offset_valid: %d "
661 "sa_offset_valid: %d "
662 "rule_indication_31_0: %d "
663 "rule_indication_63_32: %d "
664 "sa_idx: %d "
665 "da_idx: %d "
666 "msdu_drop: %d "
667 "reo_destination_indication: %d "
668 "flow_idx: %d "
669 "fse_metadata: %d "
670 "cce_metadata: %d "
671 "sa_sw_peer_id: %d ",
672 msdu_end->rxpcu_mpdu_filter_in_category,
673 msdu_end->sw_frame_group_id,
674 msdu_end->phy_ppdu_id,
675 msdu_end->ip_hdr_chksum,
676 msdu_end->tcp_udp_chksum,
677 msdu_end->key_id_octet,
678 msdu_end->cce_super_rule,
679 msdu_end->cce_classify_not_done_truncate,
680 msdu_end->cce_classify_not_done_cce_dis,
681 msdu_end->ext_wapi_pn_63_48,
682 msdu_end->ext_wapi_pn_95_64,
683 msdu_end->ext_wapi_pn_127_96,
684 msdu_end->reported_mpdu_length,
685 msdu_end->first_msdu,
686 msdu_end->last_msdu,
687 msdu_end->sa_idx_timeout,
688 msdu_end->da_idx_timeout,
689 msdu_end->msdu_limit_error,
690 msdu_end->flow_idx_timeout,
691 msdu_end->flow_idx_invalid,
692 msdu_end->wifi_parser_error,
693 msdu_end->amsdu_parser_error,
694 msdu_end->sa_is_valid,
695 msdu_end->da_is_valid,
696 msdu_end->da_is_mcbc,
697 msdu_end->l3_header_padding,
698 msdu_end->ipv6_options_crc,
699 msdu_end->tcp_seq_number,
700 msdu_end->tcp_ack_number,
701 msdu_end->tcp_flag,
702 msdu_end->lro_eligible,
703 msdu_end->window_size,
704 msdu_end->da_offset,
705 msdu_end->sa_offset,
706 msdu_end->da_offset_valid,
707 msdu_end->sa_offset_valid,
708 msdu_end->rule_indication_31_0,
709 msdu_end->rule_indication_63_32,
710 msdu_end->sa_idx,
711 msdu_end->da_idx,
712 msdu_end->msdu_drop,
713 msdu_end->reo_destination_indication,
714 msdu_end->flow_idx,
715 msdu_end->fse_metadata,
716 msdu_end->cce_metadata,
717 msdu_end->sa_sw_peer_id);
718 }
719
720
721 /*
722 * Get tid from RX_MPDU_START
723 */
724 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \
725 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
726 RX_MPDU_INFO_3_TID_OFFSET)), \
727 RX_MPDU_INFO_3_TID_MASK, \
728 RX_MPDU_INFO_3_TID_LSB))
729
hal_rx_mpdu_start_tid_get_6290(uint8_t * buf)730 static uint32_t hal_rx_mpdu_start_tid_get_6290(uint8_t *buf)
731 {
732 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
733 struct rx_mpdu_start *mpdu_start =
734 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
735 uint32_t tid;
736
737 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details);
738
739 return tid;
740 }
741
742 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \
743 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \
744 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \
745 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \
746 RX_MSDU_START_5_RECEPTION_TYPE_LSB))
747
748 /**
749 * hal_rx_msdu_start_reception_type_get_6290() - API to get the reception type
750 * Interval from rx_msdu_start
751 * @buf: pointer to the start of RX PKT TLV header
752 *
753 * Return: uint32_t(reception_type)
754 */
hal_rx_msdu_start_reception_type_get_6290(uint8_t * buf)755 static uint32_t hal_rx_msdu_start_reception_type_get_6290(uint8_t *buf)
756 {
757 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
758 struct rx_msdu_start *msdu_start =
759 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
760 uint32_t reception_type;
761
762 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start);
763
764 return reception_type;
765 }
766
767 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \
768 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
769 RX_MSDU_END_13_DA_IDX_OFFSET)), \
770 RX_MSDU_END_13_DA_IDX_MASK, \
771 RX_MSDU_END_13_DA_IDX_LSB))
772
773 /**
774 * hal_rx_msdu_end_da_idx_get_6290() - API to get da_idx from rx_msdu_end TLV
775 * @buf: pointer to the start of RX PKT TLV headers
776 *
777 * Return: da index
778 */
hal_rx_msdu_end_da_idx_get_6290(uint8_t * buf)779 static uint16_t hal_rx_msdu_end_da_idx_get_6290(uint8_t *buf)
780 {
781 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
782 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
783 uint16_t da_idx;
784
785 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
786
787 return da_idx;
788 }
789