1 /*
2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for
6 * any purpose with or without fee is hereby granted, provided that the
7 * above copyright notice and this permission notice appear in all
8 * copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17 * PERFORMANCE OF THIS SOFTWARE.
18 */
19 #include "qdf_types.h"
20 #include "qdf_util.h"
21 #include "qdf_types.h"
22 #include "qdf_lock.h"
23 #include "qdf_mem.h"
24 #include "qdf_nbuf.h"
25 #include "hal_li_hw_headers.h"
26 #include "hal_internal.h"
27 #include "hal_api.h"
28 #include "target_type.h"
29 #include "wcss_version.h"
30 #include "qdf_module.h"
31
32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
33 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET
34 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
35 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK
36 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \
37 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB
38 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \
39 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET
40 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \
41 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET
42 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \
43 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET
44 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \
45 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET
46 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \
47 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET
48 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \
49 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET
50 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \
51 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET
52 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \
53 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET
54 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \
55 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET
56 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \
57 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET
58 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \
59 PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET
60 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
61 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET
62 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
63 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
64 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
65 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
66 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
67 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
68 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
69 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
70 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
71 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER
72 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
73 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
74 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
75 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
76 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
77 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET
78 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
79 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET
80 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
81 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET
82 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
83 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB
84 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
85 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK
86 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
87 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB
88 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
89 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK
90 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
91 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB
92 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
93 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK
94 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
95 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB
96 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
97 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK
98 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
99 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB
100 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
101 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK
102 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
103 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK
104 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
105 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET
106 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
107 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB
108
109 #include "hal_6290_tx.h"
110 #include "hal_6290_rx.h"
111 #include <hal_generic_api.h>
112 #include "hal_li_rx.h"
113 #include "hal_li_api.h"
114 #include "hal_li_generic_api.h"
115
116 /**
117 * hal_rx_get_rx_fragment_number_6290() - API to retrieve rx fragment number
118 * @buf: Network buffer
119 *
120 * Return: rx fragment number
121 */
122 static
hal_rx_get_rx_fragment_number_6290(uint8_t * buf)123 uint8_t hal_rx_get_rx_fragment_number_6290(uint8_t *buf)
124 {
125 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
126 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
127
128 /* Return first 4 bits as fragment number */
129 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) &
130 DOT11_SEQ_FRAG_MASK);
131 }
132
133 /**
134 * hal_rx_msdu_end_da_is_mcbc_get_6290() - API to check if pkt is MCBC
135 * from rx_msdu_end TLV
136 * @buf: pointer to the start of RX PKT TLV headers
137 *
138 * Return: da_is_mcbc
139 */
140 static inline uint8_t
hal_rx_msdu_end_da_is_mcbc_get_6290(uint8_t * buf)141 hal_rx_msdu_end_da_is_mcbc_get_6290(uint8_t *buf)
142 {
143 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
144 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
145
146 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
147 }
148
149 /**
150 * hal_rx_msdu_end_sa_is_valid_get_6290() - API to get_6290 the sa_is_valid bit
151 * from rx_msdu_end TLV
152 * @buf: pointer to the start of RX PKT TLV headers
153 *
154 * Return: sa_is_valid bit
155 */
156 static uint8_t
hal_rx_msdu_end_sa_is_valid_get_6290(uint8_t * buf)157 hal_rx_msdu_end_sa_is_valid_get_6290(uint8_t *buf)
158 {
159 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
160 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
161 uint8_t sa_is_valid;
162
163 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end);
164
165 return sa_is_valid;
166 }
167
168 /**
169 * hal_rx_msdu_end_sa_idx_get_6290() - API to get_6290 the sa_idx from
170 * rx_msdu_end TLV
171 * @buf: pointer to the start of RX PKT TLV headers
172 *
173 * Return: sa_idx (SA AST index)
174 */
175 static
hal_rx_msdu_end_sa_idx_get_6290(uint8_t * buf)176 uint16_t hal_rx_msdu_end_sa_idx_get_6290(uint8_t *buf)
177 {
178 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
179 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
180 uint16_t sa_idx;
181
182 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
183
184 return sa_idx;
185 }
186
187 /**
188 * hal_rx_desc_is_first_msdu_6290() - Check if first msdu
189 * @hw_desc_addr: hardware descriptor address
190 *
191 * Return: 0 - success/ non-zero failure
192 */
hal_rx_desc_is_first_msdu_6290(void * hw_desc_addr)193 static uint32_t hal_rx_desc_is_first_msdu_6290(void *hw_desc_addr)
194 {
195 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
196 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
197
198 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
199 }
200
201 /**
202 * hal_rx_msdu_end_l3_hdr_padding_get_6290() - API to get_6290 the l3_header
203 * padding from rx_msdu_end TLV
204 * @buf: pointer to the start of RX PKT TLV headers
205 *
206 * Return: number of l3 header padding bytes
207 */
hal_rx_msdu_end_l3_hdr_padding_get_6290(uint8_t * buf)208 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6290(uint8_t *buf)
209 {
210 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
211 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
212 uint32_t l3_header_padding;
213
214 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
215
216 return l3_header_padding;
217 }
218
219 /**
220 * hal_rx_encryption_info_valid_6290() - Returns encryption type.
221 * @buf: rx_tlv_hdr of the received packet
222 *
223 * Return: encryption type
224 */
hal_rx_encryption_info_valid_6290(uint8_t * buf)225 static uint32_t hal_rx_encryption_info_valid_6290(uint8_t *buf)
226 {
227 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
228 struct rx_mpdu_start *mpdu_start =
229 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
230 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
231 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info);
232
233 return encryption_info;
234 }
235
236 /**
237 * hal_rx_print_pn_6290() - Prints the PN of rx packet.
238 * @buf: rx_tlv_hdr of the received packet
239 *
240 * Return: void
241 */
hal_rx_print_pn_6290(uint8_t * buf)242 static void hal_rx_print_pn_6290(uint8_t *buf)
243 {
244 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
245 struct rx_mpdu_start *mpdu_start =
246 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
247 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
248
249 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info);
250 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info);
251 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info);
252 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info);
253
254 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x",
255 pn_127_96, pn_95_64, pn_63_32, pn_31_0);
256 }
257
258 /**
259 * hal_rx_msdu_end_first_msdu_get_6290() - API to get first msdu status from
260 * rx_msdu_end TLV
261 * @buf: pointer to the start of RX PKT TLV headers
262 *
263 * Return: first_msdu
264 */
265 static uint8_t
hal_rx_msdu_end_first_msdu_get_6290(uint8_t * buf)266 hal_rx_msdu_end_first_msdu_get_6290(uint8_t *buf)
267 {
268 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
269 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
270 uint8_t first_msdu;
271
272 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end);
273
274 return first_msdu;
275 }
276
277 /**
278 * hal_rx_msdu_end_da_is_valid_get_6290() - API to check if da is valid from
279 * rx_msdu_end TLV
280 * @buf: pointer to the start of RX PKT TLV headers
281 *
282 * Return: da_is_valid
283 */
hal_rx_msdu_end_da_is_valid_get_6290(uint8_t * buf)284 static uint8_t hal_rx_msdu_end_da_is_valid_get_6290(uint8_t *buf)
285 {
286 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
287 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
288 uint8_t da_is_valid;
289
290 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end);
291
292 return da_is_valid;
293 }
294
295 /**
296 * hal_rx_msdu_end_last_msdu_get_6290() - API to get last msdu status
297 * from rx_msdu_end TLV
298 * @buf: pointer to the start of RX PKT TLV headers
299 *
300 * Return: last_msdu
301 */
hal_rx_msdu_end_last_msdu_get_6290(uint8_t * buf)302 static uint8_t hal_rx_msdu_end_last_msdu_get_6290(uint8_t *buf)
303 {
304 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
305 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
306 uint8_t last_msdu;
307
308 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end);
309
310 return last_msdu;
311 }
312
313 /**
314 * hal_rx_get_mpdu_mac_ad4_valid_6290() - Retrieves if mpdu 4th addr is valid
315 * @buf: Network buffer
316 *
317 * Return: value of mpdu 4th address valid field
318 */
hal_rx_get_mpdu_mac_ad4_valid_6290(uint8_t * buf)319 static bool hal_rx_get_mpdu_mac_ad4_valid_6290(uint8_t *buf)
320 {
321 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
322 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
323 bool ad4_valid = 0;
324
325 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info);
326
327 return ad4_valid;
328 }
329
330 /**
331 * hal_rx_mpdu_start_sw_peer_id_get_6290() - Retrieve sw peer_id
332 * @buf: network buffer
333 *
334 * Return: sw peer_id:
335 */
hal_rx_mpdu_start_sw_peer_id_get_6290(uint8_t * buf)336 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6290(uint8_t *buf)
337 {
338 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
339 struct rx_mpdu_start *mpdu_start =
340 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
341
342 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET(
343 &mpdu_start->rx_mpdu_info_details);
344 }
345
346 /**
347 * hal_rx_mpdu_get_to_ds_6290() - API to get the tods info from rx_mpdu_start
348 * @buf: pointer to the start of RX PKT TLV header
349 *
350 * Return: uint32_t(to_ds)
351 */
352
hal_rx_mpdu_get_to_ds_6290(uint8_t * buf)353 static uint32_t hal_rx_mpdu_get_to_ds_6290(uint8_t *buf)
354 {
355 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
356 struct rx_mpdu_start *mpdu_start =
357 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
358
359 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
360
361 return HAL_RX_MPDU_GET_TODS(mpdu_info);
362 }
363
364 /**
365 * hal_rx_mpdu_get_fr_ds_6290() - API to get the from ds info from rx_mpdu_start
366 * @buf: pointer to the start of RX PKT TLV header
367 *
368 * Return: uint32_t(fr_ds)
369 */
hal_rx_mpdu_get_fr_ds_6290(uint8_t * buf)370 static uint32_t hal_rx_mpdu_get_fr_ds_6290(uint8_t *buf)
371 {
372 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
373 struct rx_mpdu_start *mpdu_start =
374 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
375
376 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
377
378 return HAL_RX_MPDU_GET_FROMDS(mpdu_info);
379 }
380
381 /**
382 * hal_rx_get_mpdu_frame_control_valid_6290() - Retrieves mpdu frame control
383 * valid
384 * @buf: Network buffer
385 *
386 * Return: value of frame control valid field
387 */
hal_rx_get_mpdu_frame_control_valid_6290(uint8_t * buf)388 static uint8_t hal_rx_get_mpdu_frame_control_valid_6290(uint8_t *buf)
389 {
390 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
391 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
392
393 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info);
394 }
395
396 /**
397 * hal_rx_mpdu_get_addr1_6290() - API to check get address1 of the mpdu
398 * @buf: pointer to the start of RX PKT TLV headera
399 * @mac_addr: pointer to mac address
400 *
401 * Return: success/failure
402 */
hal_rx_mpdu_get_addr1_6290(uint8_t * buf,uint8_t * mac_addr)403 static QDF_STATUS hal_rx_mpdu_get_addr1_6290(uint8_t *buf, uint8_t *mac_addr)
404 {
405 struct __attribute__((__packed__)) hal_addr1 {
406 uint32_t ad1_31_0;
407 uint16_t ad1_47_32;
408 };
409
410 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
411 struct rx_mpdu_start *mpdu_start =
412 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
413
414 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
415 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr;
416 uint32_t mac_addr_ad1_valid;
417
418 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info);
419
420 if (mac_addr_ad1_valid) {
421 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info);
422 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info);
423 return QDF_STATUS_SUCCESS;
424 }
425
426 return QDF_STATUS_E_FAILURE;
427 }
428
429 /**
430 * hal_rx_mpdu_get_addr2_6290() - API to get address2 of the mpdu in the packet
431 * @buf: pointer to the start of RX PKT TLV header
432 * @mac_addr: pointer to mac address
433 *
434 * Return: success/failure
435 */
hal_rx_mpdu_get_addr2_6290(uint8_t * buf,uint8_t * mac_addr)436 static QDF_STATUS hal_rx_mpdu_get_addr2_6290(uint8_t *buf,
437 uint8_t *mac_addr)
438 {
439 struct __attribute__((__packed__)) hal_addr2 {
440 uint16_t ad2_15_0;
441 uint32_t ad2_47_16;
442 };
443
444 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
445 struct rx_mpdu_start *mpdu_start =
446 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
447
448 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
449 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr;
450 uint32_t mac_addr_ad2_valid;
451
452 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info);
453
454 if (mac_addr_ad2_valid) {
455 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info);
456 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info);
457 return QDF_STATUS_SUCCESS;
458 }
459
460 return QDF_STATUS_E_FAILURE;
461 }
462
463 /**
464 * hal_rx_mpdu_get_addr3_6290() - API to get address3 of the mpdu in the packet
465 * @buf: pointer to the start of RX PKT TLV header
466 * @mac_addr: pointer to mac address
467 *
468 * Return: success/failure
469 */
hal_rx_mpdu_get_addr3_6290(uint8_t * buf,uint8_t * mac_addr)470 static QDF_STATUS hal_rx_mpdu_get_addr3_6290(uint8_t *buf, uint8_t *mac_addr)
471 {
472 struct __attribute__((__packed__)) hal_addr3 {
473 uint32_t ad3_31_0;
474 uint16_t ad3_47_32;
475 };
476
477 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
478 struct rx_mpdu_start *mpdu_start =
479 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
480
481 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
482 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr;
483 uint32_t mac_addr_ad3_valid;
484
485 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info);
486
487 if (mac_addr_ad3_valid) {
488 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info);
489 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info);
490 return QDF_STATUS_SUCCESS;
491 }
492
493 return QDF_STATUS_E_FAILURE;
494 }
495
496 /**
497 * hal_rx_mpdu_get_addr4_6290() - API to get address4 of the mpdu in the packet
498 * @buf: pointer to the start of RX PKT TLV header
499 * @mac_addr: pointer to mac address
500 *
501 * Return: success/failure
502 */
hal_rx_mpdu_get_addr4_6290(uint8_t * buf,uint8_t * mac_addr)503 static QDF_STATUS hal_rx_mpdu_get_addr4_6290(uint8_t *buf, uint8_t *mac_addr)
504 {
505 struct __attribute__((__packed__)) hal_addr4 {
506 uint32_t ad4_31_0;
507 uint16_t ad4_47_32;
508 };
509
510 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
511 struct rx_mpdu_start *mpdu_start =
512 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
513
514 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
515 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr;
516 uint32_t mac_addr_ad4_valid;
517
518 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info);
519
520 if (mac_addr_ad4_valid) {
521 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info);
522 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info);
523 return QDF_STATUS_SUCCESS;
524 }
525
526 return QDF_STATUS_E_FAILURE;
527 }
528
529 /**
530 * hal_rx_get_mpdu_sequence_control_valid_6290() - Get mpdu sequence control
531 * valid
532 * @buf: Network buffer
533 *
534 * Return: value of sequence control valid field
535 */
hal_rx_get_mpdu_sequence_control_valid_6290(uint8_t * buf)536 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6290(uint8_t *buf)
537 {
538 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
539 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
540
541 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
542 }
543
544 /**
545 * hal_rx_is_unicast_6290() - check packet is unicast frame or not.
546 * @buf: pointer to rx pkt TLV.
547 *
548 * Return: true on unicast.
549 */
hal_rx_is_unicast_6290(uint8_t * buf)550 static bool hal_rx_is_unicast_6290(uint8_t *buf)
551 {
552 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
553 struct rx_mpdu_start *mpdu_start =
554 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
555 uint32_t grp_id;
556 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
557
558 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
559 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)),
560 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK,
561 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB));
562
563 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
564 }
565
566 /**
567 * hal_rx_tid_get_6290() - get tid based on qos control valid.
568 * @hal_soc_hdl: hal soc handle
569 * @buf: pointer to rx pkt TLV.
570 *
571 * Return: tid
572 */
hal_rx_tid_get_6290(hal_soc_handle_t hal_soc_hdl,uint8_t * buf)573 static uint32_t hal_rx_tid_get_6290(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
574 {
575 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
576 struct rx_mpdu_start *mpdu_start =
577 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
578 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
579 uint8_t qos_control_valid =
580 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
581 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)),
582 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK,
583 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB));
584
585 if (qos_control_valid)
586 return hal_rx_mpdu_start_tid_get_6290(buf);
587
588 return HAL_RX_NON_QOS_TID;
589 }
590
591 /**
592 * hal_rx_hw_desc_get_ppduid_get_6290() - retrieve ppdu id
593 * @rx_tlv_hdr: start address of rx_pkt_tlvs
594 * @rxdma_dst_ring_desc: Rx HW descriptor
595 *
596 * Return: ppdu id
597 */
hal_rx_hw_desc_get_ppduid_get_6290(void * rx_tlv_hdr,void * rxdma_dst_ring_desc)598 static uint32_t hal_rx_hw_desc_get_ppduid_get_6290(void *rx_tlv_hdr,
599 void *rxdma_dst_ring_desc)
600 {
601 struct rx_mpdu_info *rx_mpdu_info;
602 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr;
603
604 rx_mpdu_info =
605 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
606
607 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID);
608 }
609
610 /**
611 * hal_reo_status_get_header_6290() - Process reo desc info
612 * @ring_desc: REO status ring descriptor
613 * @b: tlv type info
614 * @h1: Pointer to hal_reo_status_header where info to be stored
615 *
616 * Return: none.
617 *
618 */
hal_reo_status_get_header_6290(hal_ring_desc_t ring_desc,int b,void * h1)619 static void hal_reo_status_get_header_6290(hal_ring_desc_t ring_desc, int b,
620 void *h1)
621 {
622 uint32_t *d = (uint32_t *)ring_desc;
623 uint32_t val1 = 0;
624 struct hal_reo_status_header *h =
625 (struct hal_reo_status_header *)h1;
626
627 /* Offsets of descriptor fields defined in HW headers start
628 * from the field after TLV header
629 */
630 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr));
631
632 switch (b) {
633 case HAL_REO_QUEUE_STATS_STATUS_TLV:
634 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
635 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
636 break;
637 case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
638 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0,
639 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
640 break;
641 case HAL_REO_FLUSH_CACHE_STATUS_TLV:
642 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0,
643 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
644 break;
645 case HAL_REO_UNBLK_CACHE_STATUS_TLV:
646 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0,
647 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
648 break;
649 case HAL_REO_TIMOUT_LIST_STATUS_TLV:
650 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0,
651 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
652 break;
653 case HAL_REO_DESC_THRES_STATUS_TLV:
654 val1 =
655 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0,
656 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
657 break;
658 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
659 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0,
660 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
661 break;
662 default:
663 qdf_nofl_err("ERROR: Unknown tlv\n");
664 break;
665 }
666 h->cmd_num =
667 HAL_GET_FIELD(
668 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER,
669 val1);
670 h->exec_time =
671 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
672 CMD_EXECUTION_TIME, val1);
673 h->status =
674 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
675 REO_CMD_EXECUTION_STATUS, val1);
676 switch (b) {
677 case HAL_REO_QUEUE_STATS_STATUS_TLV:
678 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1,
679 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
680 break;
681 case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
682 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1,
683 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
684 break;
685 case HAL_REO_FLUSH_CACHE_STATUS_TLV:
686 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1,
687 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
688 break;
689 case HAL_REO_UNBLK_CACHE_STATUS_TLV:
690 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1,
691 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
692 break;
693 case HAL_REO_TIMOUT_LIST_STATUS_TLV:
694 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1,
695 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
696 break;
697 case HAL_REO_DESC_THRES_STATUS_TLV:
698 val1 =
699 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1,
700 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
701 break;
702 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
703 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1,
704 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
705 break;
706 default:
707 qdf_nofl_err("ERROR: Unknown tlv\n");
708 break;
709 }
710 h->tstamp =
711 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1);
712 }
713
714 /**
715 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290() -
716 * Retrieve qos control valid bit from the tlv.
717 * @buf: pointer to rx pkt TLV.
718 *
719 * Return: qos control value.
720 */
721 static inline uint32_t
hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290(uint8_t * buf)722 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290(uint8_t *buf)
723 {
724 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
725 struct rx_mpdu_start *mpdu_start =
726 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
727
728 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(
729 &mpdu_start->rx_mpdu_info_details);
730 }
731
732 /**
733 * hal_rx_msdu_end_sa_sw_peer_id_get_6290() - API to get the
734 * sa_sw_peer_id from rx_msdu_end TLV
735 * @buf: pointer to the start of RX PKT TLV headers
736 *
737 * Return: sa_sw_peer_id index
738 */
739 static inline uint32_t
hal_rx_msdu_end_sa_sw_peer_id_get_6290(uint8_t * buf)740 hal_rx_msdu_end_sa_sw_peer_id_get_6290(uint8_t *buf)
741 {
742 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
743 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
744
745 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
746 }
747
748 /**
749 * hal_tx_desc_set_mesh_en_6290() - Set mesh_enable flag in Tx descriptor
750 * @desc: Handle to Tx Descriptor
751 * @en: For raw WiFi frames, this indicates transmission to a mesh STA,
752 * enabling the interpretation of the 'Mesh Control Present' bit
753 * (bit 8) of QoS Control (otherwise this bit is ignored),
754 * For native WiFi frames, this indicates that a 'Mesh Control' field
755 * is present between the header and the LLC.
756 *
757 * Return: void
758 */
759 static inline
hal_tx_desc_set_mesh_en_6290(void * desc,uint8_t en)760 void hal_tx_desc_set_mesh_en_6290(void *desc, uint8_t en)
761 {
762 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |=
763 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
764 }
765
766 static
hal_rx_msdu0_buffer_addr_lsb_6290(void * link_desc_va)767 void *hal_rx_msdu0_buffer_addr_lsb_6290(void *link_desc_va)
768 {
769 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
770 }
771
772 static
hal_rx_msdu_desc_info_ptr_get_6290(void * msdu0)773 void *hal_rx_msdu_desc_info_ptr_get_6290(void *msdu0)
774 {
775 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
776 }
777
778 static
hal_ent_mpdu_desc_info_6290(void * ent_ring_desc)779 void *hal_ent_mpdu_desc_info_6290(void *ent_ring_desc)
780 {
781 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
782 }
783
784 static
hal_dst_mpdu_desc_info_6290(void * dst_ring_desc)785 void *hal_dst_mpdu_desc_info_6290(void *dst_ring_desc)
786 {
787 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
788 }
789
790 static
hal_rx_get_fc_valid_6290(uint8_t * buf)791 uint8_t hal_rx_get_fc_valid_6290(uint8_t *buf)
792 {
793 return HAL_RX_GET_FC_VALID(buf);
794 }
795
hal_rx_get_to_ds_flag_6290(uint8_t * buf)796 static uint8_t hal_rx_get_to_ds_flag_6290(uint8_t *buf)
797 {
798 return HAL_RX_GET_TO_DS_FLAG(buf);
799 }
800
hal_rx_get_mac_addr2_valid_6290(uint8_t * buf)801 static uint8_t hal_rx_get_mac_addr2_valid_6290(uint8_t *buf)
802 {
803 return HAL_RX_GET_MAC_ADDR2_VALID(buf);
804 }
805
hal_rx_get_filter_category_6290(uint8_t * buf)806 static uint8_t hal_rx_get_filter_category_6290(uint8_t *buf)
807 {
808 return HAL_RX_GET_FILTER_CATEGORY(buf);
809 }
810
811 static uint32_t
hal_rx_get_ppdu_id_6290(uint8_t * buf)812 hal_rx_get_ppdu_id_6290(uint8_t *buf)
813 {
814 return HAL_RX_GET_PPDU_ID(buf);
815 }
816
817 /**
818 * hal_reo_config_6290() - Set reo config parameters
819 * @soc: hal soc handle
820 * @reg_val: value to be set
821 * @reo_params: reo parameters
822 *
823 * Return: void
824 */
825 static
hal_reo_config_6290(struct hal_soc * soc,uint32_t reg_val,struct hal_reo_params * reo_params)826 void hal_reo_config_6290(struct hal_soc *soc,
827 uint32_t reg_val,
828 struct hal_reo_params *reo_params)
829 {
830 HAL_REO_R0_CONFIG(soc, reg_val, reo_params);
831 }
832
833 /**
834 * hal_rx_msdu_desc_info_get_ptr_6290() - Get msdu desc info ptr
835 * @msdu_details_ptr: Pointer to msdu_details_ptr
836 *
837 * Return: Pointer to rx_msdu_desc_info structure.
838 *
839 */
hal_rx_msdu_desc_info_get_ptr_6290(void * msdu_details_ptr)840 static void *hal_rx_msdu_desc_info_get_ptr_6290(void *msdu_details_ptr)
841 {
842 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
843 }
844
845 /**
846 * hal_rx_link_desc_msdu0_ptr_6290() - Get pointer to rx_msdu details
847 * @link_desc: Pointer to link desc
848 *
849 * Return: Pointer to rx_msdu_details structure
850 *
851 */
hal_rx_link_desc_msdu0_ptr_6290(void * link_desc)852 static void *hal_rx_link_desc_msdu0_ptr_6290(void *link_desc)
853 {
854 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
855 }
856
857 /**
858 * hal_rx_msdu_flow_idx_get_6290() - API to get flow index
859 * from rx_msdu_end TLV
860 * @buf: pointer to the start of RX PKT TLV headers
861 *
862 * Return: flow index value from MSDU END TLV
863 */
hal_rx_msdu_flow_idx_get_6290(uint8_t * buf)864 static inline uint32_t hal_rx_msdu_flow_idx_get_6290(uint8_t *buf)
865 {
866 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
867 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
868
869 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
870 }
871
872 /**
873 * hal_rx_msdu_flow_idx_invalid_6290() - API to get flow index invalid
874 * from rx_msdu_end TLV
875 * @buf: pointer to the start of RX PKT TLV headers
876 *
877 * Return: flow index invalid value from MSDU END TLV
878 */
hal_rx_msdu_flow_idx_invalid_6290(uint8_t * buf)879 static bool hal_rx_msdu_flow_idx_invalid_6290(uint8_t *buf)
880 {
881 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
882 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
883
884 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
885 }
886
887 /**
888 * hal_rx_msdu_flow_idx_timeout_6290() - API to get flow index timeout
889 * from rx_msdu_end TLV
890 * @buf: pointer to the start of RX PKT TLV headers
891 *
892 * Return: flow index timeout value from MSDU END TLV
893 */
hal_rx_msdu_flow_idx_timeout_6290(uint8_t * buf)894 static bool hal_rx_msdu_flow_idx_timeout_6290(uint8_t *buf)
895 {
896 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
897 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
898
899 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
900 }
901
902 /**
903 * hal_rx_msdu_fse_metadata_get_6290() - API to get FSE metadata
904 * from rx_msdu_end TLV
905 * @buf: pointer to the start of RX PKT TLV headers
906 *
907 * Return: fse metadata value from MSDU END TLV
908 */
hal_rx_msdu_fse_metadata_get_6290(uint8_t * buf)909 static uint32_t hal_rx_msdu_fse_metadata_get_6290(uint8_t *buf)
910 {
911 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
912 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
913
914 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end);
915 }
916
917 /**
918 * hal_rx_msdu_cce_metadata_get_6290() - API to get CCE metadata
919 * from rx_msdu_end TLV
920 * @buf: pointer to the start of RX PKT TLV headers
921 *
922 * Return: cce_metadata
923 */
924 static uint16_t
hal_rx_msdu_cce_metadata_get_6290(uint8_t * buf)925 hal_rx_msdu_cce_metadata_get_6290(uint8_t *buf)
926 {
927 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
928 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
929
930 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end);
931 }
932
933 /**
934 * hal_rx_msdu_get_flow_params_6290() - API to get flow index, flow index
935 * invalid and flow index timeout from
936 * rx_msdu_end TLV
937 * @buf: pointer to the start of RX PKT TLV headers
938 * @flow_invalid: pointer to return value of flow_idx_valid
939 * @flow_timeout: pointer to return value of flow_idx_timeout
940 * @flow_index: pointer to return value of flow_idx
941 *
942 * Return: none
943 */
944 static inline void
hal_rx_msdu_get_flow_params_6290(uint8_t * buf,bool * flow_invalid,bool * flow_timeout,uint32_t * flow_index)945 hal_rx_msdu_get_flow_params_6290(uint8_t *buf,
946 bool *flow_invalid,
947 bool *flow_timeout,
948 uint32_t *flow_index)
949 {
950 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
951 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
952
953 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
954 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
955 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
956 }
957
958 /**
959 * hal_rx_tlv_get_tcp_chksum_6290() - API to get tcp checksum
960 * @buf: rx_tlv_hdr
961 *
962 * Return: tcp checksum
963 */
964 static uint16_t
hal_rx_tlv_get_tcp_chksum_6290(uint8_t * buf)965 hal_rx_tlv_get_tcp_chksum_6290(uint8_t *buf)
966 {
967 return HAL_RX_TLV_GET_TCP_CHKSUM(buf);
968 }
969
970 /**
971 * hal_rx_get_rx_sequence_6290() - Function to retrieve rx sequence number
972 * @buf: Network buffer
973 *
974 * Return: rx sequence number
975 */
976 static
hal_rx_get_rx_sequence_6290(uint8_t * buf)977 uint16_t hal_rx_get_rx_sequence_6290(uint8_t *buf)
978 {
979 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
980 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
981
982 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info);
983 }
984
985 /**
986 * hal_get_window_address_6290() - Function to get hp/tp address
987 * @hal_soc: Pointer to hal_soc
988 * @addr: address offset of register
989 *
990 * Return: modified address offset of register
991 */
hal_get_window_address_6290(struct hal_soc * hal_soc,qdf_iomem_t addr)992 static inline qdf_iomem_t hal_get_window_address_6290(struct hal_soc *hal_soc,
993 qdf_iomem_t addr)
994 {
995 return addr;
996 }
997
998 static
hal_compute_reo_remap_ix2_ix3_6290(uint32_t * ring,uint32_t num_rings,uint32_t * remap1,uint32_t * remap2)999 void hal_compute_reo_remap_ix2_ix3_6290(uint32_t *ring, uint32_t num_rings,
1000 uint32_t *remap1, uint32_t *remap2)
1001 {
1002 switch (num_rings) {
1003 case 3:
1004 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1005 HAL_REO_REMAP_IX2(ring[1], 17) |
1006 HAL_REO_REMAP_IX2(ring[2], 18) |
1007 HAL_REO_REMAP_IX2(ring[0], 19) |
1008 HAL_REO_REMAP_IX2(ring[1], 20) |
1009 HAL_REO_REMAP_IX2(ring[2], 21) |
1010 HAL_REO_REMAP_IX2(ring[0], 22) |
1011 HAL_REO_REMAP_IX2(ring[1], 23);
1012
1013 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) |
1014 HAL_REO_REMAP_IX3(ring[0], 25) |
1015 HAL_REO_REMAP_IX3(ring[1], 26) |
1016 HAL_REO_REMAP_IX3(ring[2], 27) |
1017 HAL_REO_REMAP_IX3(ring[0], 28) |
1018 HAL_REO_REMAP_IX3(ring[1], 29) |
1019 HAL_REO_REMAP_IX3(ring[2], 30) |
1020 HAL_REO_REMAP_IX3(ring[0], 31);
1021 break;
1022 case 4:
1023 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1024 HAL_REO_REMAP_IX2(ring[1], 17) |
1025 HAL_REO_REMAP_IX2(ring[2], 18) |
1026 HAL_REO_REMAP_IX2(ring[3], 19) |
1027 HAL_REO_REMAP_IX2(ring[0], 20) |
1028 HAL_REO_REMAP_IX2(ring[1], 21) |
1029 HAL_REO_REMAP_IX2(ring[2], 22) |
1030 HAL_REO_REMAP_IX2(ring[3], 23);
1031
1032 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
1033 HAL_REO_REMAP_IX3(ring[1], 25) |
1034 HAL_REO_REMAP_IX3(ring[2], 26) |
1035 HAL_REO_REMAP_IX3(ring[3], 27) |
1036 HAL_REO_REMAP_IX3(ring[0], 28) |
1037 HAL_REO_REMAP_IX3(ring[1], 29) |
1038 HAL_REO_REMAP_IX3(ring[2], 30) |
1039 HAL_REO_REMAP_IX3(ring[3], 31);
1040 break;
1041 }
1042 }
1043
1044 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
1045 /**
1046 * hal_get_first_wow_wakeup_packet_6290() - Function to get if the buffer
1047 * is the first one that wakes up host from WoW.
1048 *
1049 * @buf: network buffer
1050 *
1051 * Dummy function for QCA6290
1052 *
1053 * Return: 1 to indicate it is first packet received that wakes up host from
1054 * WoW. Otherwise 0
1055 */
hal_get_first_wow_wakeup_packet_6290(uint8_t * buf)1056 static inline uint8_t hal_get_first_wow_wakeup_packet_6290(uint8_t *buf)
1057 {
1058 return 0;
1059 }
1060 #endif
1061
hal_hw_txrx_ops_attach_6290(struct hal_soc * hal_soc)1062 static void hal_hw_txrx_ops_attach_6290(struct hal_soc *hal_soc)
1063 {
1064 /* init and setup */
1065 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
1066 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
1067 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
1068 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li;
1069 hal_soc->ops->hal_get_window_address = hal_get_window_address_6290;
1070
1071 /* tx */
1072 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
1073 hal_tx_desc_set_dscp_tid_table_id_6290;
1074 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6290;
1075 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6290;
1076 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6290;
1077 hal_soc->ops->hal_tx_desc_set_buf_addr =
1078 hal_tx_desc_set_buf_addr_generic_li;
1079 hal_soc->ops->hal_tx_desc_set_search_type =
1080 hal_tx_desc_set_search_type_generic_li;
1081 hal_soc->ops->hal_tx_desc_set_search_index =
1082 hal_tx_desc_set_search_index_generic_li;
1083 hal_soc->ops->hal_tx_desc_set_cache_set_num =
1084 hal_tx_desc_set_cache_set_num_generic_li;
1085 hal_soc->ops->hal_tx_comp_get_status =
1086 hal_tx_comp_get_status_generic_li;
1087 hal_soc->ops->hal_tx_comp_get_release_reason =
1088 hal_tx_comp_get_release_reason_generic_li;
1089 hal_soc->ops->hal_get_wbm_internal_error =
1090 hal_get_wbm_internal_error_generic_li;
1091 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6290;
1092 hal_soc->ops->hal_tx_init_cmd_credit_ring =
1093 hal_tx_init_cmd_credit_ring_6290;
1094
1095 /* rx */
1096 hal_soc->ops->hal_rx_msdu_start_nss_get =
1097 hal_rx_msdu_start_nss_get_6290;
1098 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
1099 hal_rx_mon_hw_desc_get_mpdu_status_6290;
1100 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6290;
1101 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
1102 hal_rx_proc_phyrx_other_receive_info_tlv_6290;
1103
1104 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6290;
1105 hal_soc->ops->hal_rx_dump_rx_attention_tlv =
1106 hal_rx_dump_rx_attention_tlv_generic_li;
1107 hal_soc->ops->hal_rx_dump_msdu_start_tlv =
1108 hal_rx_dump_msdu_start_tlv_6290;
1109 hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
1110 hal_rx_dump_mpdu_start_tlv_generic_li;
1111 hal_soc->ops->hal_rx_dump_mpdu_end_tlv =
1112 hal_rx_dump_mpdu_end_tlv_generic_li;
1113 hal_soc->ops->hal_rx_dump_pkt_hdr_tlv =
1114 hal_rx_dump_pkt_hdr_tlv_generic_li;
1115
1116 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6290;
1117 hal_soc->ops->hal_rx_mpdu_start_tid_get =
1118 hal_rx_mpdu_start_tid_get_6290;
1119 hal_soc->ops->hal_rx_msdu_start_reception_type_get =
1120 hal_rx_msdu_start_reception_type_get_6290;
1121 hal_soc->ops->hal_rx_msdu_end_da_idx_get =
1122 hal_rx_msdu_end_da_idx_get_6290;
1123 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
1124 hal_rx_msdu_desc_info_get_ptr_6290;
1125 hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
1126 hal_rx_link_desc_msdu0_ptr_6290;
1127 hal_soc->ops->hal_reo_status_get_header =
1128 hal_reo_status_get_header_6290;
1129 hal_soc->ops->hal_rx_status_get_tlv_info =
1130 hal_rx_status_get_tlv_info_generic_li;
1131 hal_soc->ops->hal_rx_wbm_err_info_get =
1132 hal_rx_wbm_err_info_get_generic_li;
1133
1134 hal_soc->ops->hal_tx_set_pcp_tid_map =
1135 hal_tx_set_pcp_tid_map_generic_li;
1136 hal_soc->ops->hal_tx_update_pcp_tid_map =
1137 hal_tx_update_pcp_tid_generic_li;
1138 hal_soc->ops->hal_tx_set_tidmap_prty =
1139 hal_tx_update_tidmap_prty_generic_li;
1140 hal_soc->ops->hal_rx_get_rx_fragment_number =
1141 hal_rx_get_rx_fragment_number_6290;
1142 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
1143 hal_rx_msdu_end_da_is_mcbc_get_6290;
1144 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
1145 hal_rx_msdu_end_sa_is_valid_get_6290;
1146 hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
1147 hal_rx_msdu_end_sa_idx_get_6290;
1148 hal_soc->ops->hal_rx_desc_is_first_msdu =
1149 hal_rx_desc_is_first_msdu_6290;
1150 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
1151 hal_rx_msdu_end_l3_hdr_padding_get_6290;
1152 hal_soc->ops->hal_rx_encryption_info_valid =
1153 hal_rx_encryption_info_valid_6290;
1154 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6290;
1155 hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
1156 hal_rx_msdu_end_first_msdu_get_6290;
1157 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
1158 hal_rx_msdu_end_da_is_valid_get_6290;
1159 hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
1160 hal_rx_msdu_end_last_msdu_get_6290;
1161 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
1162 hal_rx_get_mpdu_mac_ad4_valid_6290;
1163 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
1164 hal_rx_mpdu_start_sw_peer_id_get_6290;
1165 hal_soc->ops->hal_rx_tlv_peer_meta_data_get =
1166 hal_rx_mpdu_peer_meta_data_get_li;
1167 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6290;
1168 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6290;
1169 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
1170 hal_rx_get_mpdu_frame_control_valid_6290;
1171 hal_soc->ops->hal_rx_get_frame_ctrl_field =
1172 hal_rx_get_frame_ctrl_field_li;
1173 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6290;
1174 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6290;
1175 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6290;
1176 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6290;
1177 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
1178 hal_rx_get_mpdu_sequence_control_valid_6290;
1179 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6290;
1180 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6290;
1181 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
1182 hal_rx_hw_desc_get_ppduid_get_6290;
1183 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
1184 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290;
1185 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
1186 hal_rx_msdu_end_sa_sw_peer_id_get_6290;
1187 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
1188 hal_rx_msdu0_buffer_addr_lsb_6290;
1189 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
1190 hal_rx_msdu_desc_info_ptr_get_6290;
1191 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6290;
1192 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6290;
1193 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6290;
1194 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6290;
1195 hal_soc->ops->hal_rx_get_mac_addr2_valid =
1196 hal_rx_get_mac_addr2_valid_6290;
1197 hal_soc->ops->hal_rx_get_filter_category =
1198 hal_rx_get_filter_category_6290;
1199 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6290;
1200 hal_soc->ops->hal_reo_config = hal_reo_config_6290;
1201 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6290;
1202 hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
1203 hal_rx_msdu_flow_idx_invalid_6290;
1204 hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
1205 hal_rx_msdu_flow_idx_timeout_6290;
1206 hal_soc->ops->hal_rx_msdu_fse_metadata_get =
1207 hal_rx_msdu_fse_metadata_get_6290;
1208 hal_soc->ops->hal_rx_msdu_cce_match_get =
1209 hal_rx_msdu_cce_match_get_li;
1210 hal_soc->ops->hal_rx_msdu_cce_metadata_get =
1211 hal_rx_msdu_cce_metadata_get_6290;
1212 hal_soc->ops->hal_rx_msdu_get_flow_params =
1213 hal_rx_msdu_get_flow_params_6290;
1214 hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
1215 hal_rx_tlv_get_tcp_chksum_6290;
1216 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6290;
1217 /* rx - msdu end fast path info fields */
1218 hal_soc->ops->hal_rx_msdu_packet_metadata_get =
1219 hal_rx_msdu_packet_metadata_get_generic_li;
1220 /* rx - TLV struct offsets */
1221 hal_soc->ops->hal_rx_msdu_end_offset_get =
1222 hal_rx_msdu_end_offset_get_generic;
1223 hal_soc->ops->hal_rx_attn_offset_get =
1224 hal_rx_attn_offset_get_generic;
1225 hal_soc->ops->hal_rx_msdu_start_offset_get =
1226 hal_rx_msdu_start_offset_get_generic;
1227 hal_soc->ops->hal_rx_mpdu_start_offset_get =
1228 hal_rx_mpdu_start_offset_get_generic;
1229 hal_soc->ops->hal_rx_mpdu_end_offset_get =
1230 hal_rx_mpdu_end_offset_get_generic;
1231 #ifndef NO_RX_PKT_HDR_TLV
1232 hal_soc->ops->hal_rx_pkt_tlv_offset_get =
1233 hal_rx_pkt_tlv_offset_get_generic;
1234 #endif
1235 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
1236 hal_compute_reo_remap_ix2_ix3_6290;
1237 hal_soc->ops->hal_setup_link_idle_list =
1238 hal_setup_link_idle_list_generic_li;
1239 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
1240 hal_soc->ops->hal_get_first_wow_wakeup_packet =
1241 hal_get_first_wow_wakeup_packet_6290;
1242 #endif
1243 hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_li;
1244 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_li;
1245 hal_soc->ops->hal_rx_tlv_decrypt_err_get =
1246 hal_rx_tlv_decrypt_err_get_li;
1247 hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags =
1248 hal_rx_tlv_get_pkt_capture_flags_li;
1249 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get =
1250 hal_rx_mpdu_info_ampdu_flag_get_li;
1251 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL;
1252 };
1253
1254 struct hal_hw_srng_config hw_srng_table_6290[] = {
1255 /* TODO: max_rings can populated by querying HW capabilities */
1256 { /* REO_DST */
1257 .start_ring_id = HAL_SRNG_REO2SW1,
1258 .max_rings = 4,
1259 .entry_size = sizeof(struct reo_destination_ring) >> 2,
1260 .lmac_ring = FALSE,
1261 .ring_dir = HAL_SRNG_DST_RING,
1262 .reg_start = {
1263 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
1264 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1265 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
1266 SEQ_WCSS_UMAC_REO_REG_OFFSET)
1267 },
1268 .reg_size = {
1269 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
1270 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
1271 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
1272 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
1273 },
1274 .max_size = HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
1275 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
1276 },
1277 { /* REO_EXCEPTION */
1278 /* Designating REO2TCL ring as exception ring. This ring is
1279 * similar to other REO2SW rings though it is named as REO2TCL.
1280 * Any of theREO2SW rings can be used as exception ring.
1281 */
1282 .start_ring_id = HAL_SRNG_REO2TCL,
1283 .max_rings = 1,
1284 .entry_size = sizeof(struct reo_destination_ring) >> 2,
1285 .lmac_ring = FALSE,
1286 .ring_dir = HAL_SRNG_DST_RING,
1287 .reg_start = {
1288 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(
1289 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1290 HWIO_REO_R2_REO2TCL_RING_HP_ADDR(
1291 SEQ_WCSS_UMAC_REO_REG_OFFSET)
1292 },
1293 /* Single ring - provide ring size if multiple rings of this
1294 * type are supported
1295 */
1296 .reg_size = {},
1297 .max_size = HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >>
1298 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT,
1299 },
1300 { /* REO_REINJECT */
1301 .start_ring_id = HAL_SRNG_SW2REO,
1302 .max_rings = 1,
1303 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
1304 .lmac_ring = FALSE,
1305 .ring_dir = HAL_SRNG_SRC_RING,
1306 .reg_start = {
1307 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
1308 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1309 HWIO_REO_R2_SW2REO_RING_HP_ADDR(
1310 SEQ_WCSS_UMAC_REO_REG_OFFSET)
1311 },
1312 /* Single ring - provide ring size if multiple rings of this
1313 * type are supported
1314 */
1315 .reg_size = {},
1316 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
1317 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
1318 },
1319 { /* REO_CMD */
1320 .start_ring_id = HAL_SRNG_REO_CMD,
1321 .max_rings = 1,
1322 .entry_size = (sizeof(struct tlv_32_hdr) +
1323 sizeof(struct reo_get_queue_stats)) >> 2,
1324 .lmac_ring = FALSE,
1325 .ring_dir = HAL_SRNG_SRC_RING,
1326 .reg_start = {
1327 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
1328 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1329 HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
1330 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1331 },
1332 /* Single ring - provide ring size if multiple rings of this
1333 * type are supported
1334 */
1335 .reg_size = {},
1336 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
1337 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
1338 },
1339 { /* REO_STATUS */
1340 .start_ring_id = HAL_SRNG_REO_STATUS,
1341 .max_rings = 1,
1342 .entry_size = (sizeof(struct tlv_32_hdr) +
1343 sizeof(struct reo_get_queue_stats_status)) >> 2,
1344 .lmac_ring = FALSE,
1345 .ring_dir = HAL_SRNG_DST_RING,
1346 .reg_start = {
1347 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
1348 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1349 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
1350 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1351 },
1352 /* Single ring - provide ring size if multiple rings of this
1353 * type are supported
1354 */
1355 .reg_size = {},
1356 .max_size =
1357 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
1358 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
1359 },
1360 { /* TCL_DATA */
1361 .start_ring_id = HAL_SRNG_SW2TCL1,
1362 .max_rings = 3,
1363 .entry_size = (sizeof(struct tlv_32_hdr) +
1364 sizeof(struct tcl_data_cmd)) >> 2,
1365 .lmac_ring = FALSE,
1366 .ring_dir = HAL_SRNG_SRC_RING,
1367 .reg_start = {
1368 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
1369 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
1370 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
1371 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
1372 },
1373 .reg_size = {
1374 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
1375 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
1376 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
1377 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
1378 },
1379 .max_size = HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
1380 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
1381 },
1382 { /* TCL_CMD */
1383 .start_ring_id = HAL_SRNG_SW2TCL_CMD,
1384 .max_rings = 1,
1385 .entry_size = (sizeof(struct tlv_32_hdr) +
1386 sizeof(struct tcl_gse_cmd)) >> 2,
1387 .lmac_ring = FALSE,
1388 .ring_dir = HAL_SRNG_SRC_RING,
1389 .reg_start = {
1390 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(
1391 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
1392 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(
1393 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
1394 },
1395 /* Single ring - provide ring size if multiple rings of this
1396 * type are supported
1397 */
1398 .reg_size = {},
1399 .max_size =
1400 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
1401 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
1402 },
1403 { /* TCL_STATUS */
1404 .start_ring_id = HAL_SRNG_TCL_STATUS,
1405 .max_rings = 1,
1406 .entry_size = (sizeof(struct tlv_32_hdr) +
1407 sizeof(struct tcl_status_ring)) >> 2,
1408 .lmac_ring = FALSE,
1409 .ring_dir = HAL_SRNG_DST_RING,
1410 .reg_start = {
1411 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
1412 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
1413 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
1414 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
1415 },
1416 /* Single ring - provide ring size if multiple rings of this
1417 * type are supported
1418 */
1419 .reg_size = {},
1420 .max_size =
1421 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
1422 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
1423 },
1424 { /* CE_SRC */
1425 .start_ring_id = HAL_SRNG_CE_0_SRC,
1426 .max_rings = 12,
1427 .entry_size = sizeof(struct ce_src_desc) >> 2,
1428 .lmac_ring = FALSE,
1429 .ring_dir = HAL_SRNG_SRC_RING,
1430 .reg_start = {
1431 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
1432 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
1433 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
1434 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
1435 },
1436 .reg_size = {
1437 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
1438 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
1439 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
1440 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
1441 },
1442 .max_size =
1443 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
1444 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
1445 },
1446 { /* CE_DST */
1447 .start_ring_id = HAL_SRNG_CE_0_DST,
1448 .max_rings = 12,
1449 .entry_size = 8 >> 2,
1450 /*TODO: entry_size above should actually be
1451 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
1452 * of struct ce_dst_desc in HW header files
1453 */
1454 .lmac_ring = FALSE,
1455 .ring_dir = HAL_SRNG_SRC_RING,
1456 .reg_start = {
1457 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
1458 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
1459 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
1460 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
1461 },
1462 .reg_size = {
1463 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
1464 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
1465 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
1466 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
1467 },
1468 .max_size =
1469 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
1470 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
1471 },
1472 { /* CE_DST_STATUS */
1473 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
1474 .max_rings = 12,
1475 .entry_size = sizeof(struct ce_stat_desc) >> 2,
1476 .lmac_ring = FALSE,
1477 .ring_dir = HAL_SRNG_DST_RING,
1478 .reg_start = {
1479 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
1480 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
1481 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
1482 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
1483 },
1484 /* TODO: check destination status ring registers */
1485 .reg_size = {
1486 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
1487 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
1488 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
1489 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
1490 },
1491 .max_size =
1492 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
1493 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
1494 },
1495 { /* WBM_IDLE_LINK */
1496 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
1497 .max_rings = 1,
1498 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
1499 .lmac_ring = FALSE,
1500 .ring_dir = HAL_SRNG_SRC_RING,
1501 .reg_start = {
1502 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1503 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1504 },
1505 /* Single ring - provide ring size if multiple rings of this
1506 * type are supported
1507 */
1508 .reg_size = {},
1509 .max_size =
1510 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
1511 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
1512 },
1513 { /* SW2WBM_RELEASE */
1514 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
1515 .max_rings = 1,
1516 .entry_size = sizeof(struct wbm_release_ring) >> 2,
1517 .lmac_ring = FALSE,
1518 .ring_dir = HAL_SRNG_SRC_RING,
1519 .reg_start = {
1520 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1521 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1522 },
1523 /* Single ring - provide ring size if multiple rings of this
1524 * type are supported
1525 */
1526 .reg_size = {},
1527 .max_size =
1528 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
1529 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
1530 },
1531 { /* WBM2SW_RELEASE */
1532 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
1533 .max_rings = 4,
1534 .entry_size = sizeof(struct wbm_release_ring) >> 2,
1535 .lmac_ring = FALSE,
1536 .ring_dir = HAL_SRNG_DST_RING,
1537 .reg_start = {
1538 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1539 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1540 },
1541 .reg_size = {
1542 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
1543 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1544 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
1545 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1546 },
1547 .max_size =
1548 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
1549 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
1550 },
1551 { /* RXDMA_BUF */
1552 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
1553 #ifdef IPA_OFFLOAD
1554 .max_rings = 3,
1555 #else
1556 .max_rings = 2,
1557 #endif
1558 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
1559 .lmac_ring = TRUE,
1560 .ring_dir = HAL_SRNG_SRC_RING,
1561 /* reg_start is not set because LMAC rings are not accessed
1562 * from host
1563 */
1564 .reg_start = {},
1565 .reg_size = {},
1566 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1567 },
1568 { /* RXDMA_DST */
1569 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
1570 .max_rings = 1,
1571 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
1572 .lmac_ring = TRUE,
1573 .ring_dir = HAL_SRNG_DST_RING,
1574 /* reg_start is not set because LMAC rings are not accessed
1575 * from host
1576 */
1577 .reg_start = {},
1578 .reg_size = {},
1579 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1580 },
1581 { /* RXDMA_MONITOR_BUF */
1582 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
1583 .max_rings = 1,
1584 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
1585 .lmac_ring = TRUE,
1586 .ring_dir = HAL_SRNG_SRC_RING,
1587 /* reg_start is not set because LMAC rings are not accessed
1588 * from host
1589 */
1590 .reg_start = {},
1591 .reg_size = {},
1592 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1593 },
1594 { /* RXDMA_MONITOR_STATUS */
1595 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
1596 .max_rings = 1,
1597 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
1598 .lmac_ring = TRUE,
1599 .ring_dir = HAL_SRNG_SRC_RING,
1600 /* reg_start is not set because LMAC rings are not accessed
1601 * from host
1602 */
1603 .reg_start = {},
1604 .reg_size = {},
1605 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1606 },
1607 { /* RXDMA_MONITOR_DST */
1608 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1,
1609 .max_rings = 1,
1610 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
1611 .lmac_ring = TRUE,
1612 .ring_dir = HAL_SRNG_DST_RING,
1613 /* reg_start is not set because LMAC rings are not accessed
1614 * from host
1615 */
1616 .reg_start = {},
1617 .reg_size = {},
1618 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1619 },
1620 { /* RXDMA_MONITOR_DESC */
1621 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
1622 .max_rings = 1,
1623 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
1624 .lmac_ring = TRUE,
1625 .ring_dir = HAL_SRNG_SRC_RING,
1626 /* reg_start is not set because LMAC rings are not accessed
1627 * from host
1628 */
1629 .reg_start = {},
1630 .reg_size = {},
1631 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1632 },
1633 { /* DIR_BUF_RX_DMA_SRC */
1634 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
1635 .max_rings = 1,
1636 .entry_size = 2,
1637 .lmac_ring = TRUE,
1638 .ring_dir = HAL_SRNG_SRC_RING,
1639 /* reg_start is not set because LMAC rings are not accessed
1640 * from host
1641 */
1642 .reg_start = {},
1643 .reg_size = {},
1644 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1645 },
1646 #ifdef WLAN_FEATURE_CIF_CFR
1647 { /* WIFI_POS_SRC */
1648 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
1649 .max_rings = 1,
1650 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
1651 .lmac_ring = TRUE,
1652 .ring_dir = HAL_SRNG_SRC_RING,
1653 /* reg_start is not set because LMAC rings are not accessed
1654 * from host
1655 */
1656 .reg_start = {},
1657 .reg_size = {},
1658 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1659 },
1660 #endif
1661 { /* REO2PPE */ 0},
1662 { /* PPE2TCL */ 0},
1663 { /* PPE_RELEASE */ 0},
1664 { /* TX_MONITOR_BUF */ 0},
1665 { /* TX_MONITOR_DST */ 0},
1666 { /* SW2RXDMA_NEW */ 0},
1667 { /* SW2RXDMA_LINK_RELEASE */ 0},
1668 };
1669
1670 /**
1671 * hal_qca6290_attach() - Attach 6290 target specific hal_soc ops,
1672 * offset and srng table
1673 * @hal_soc: Pointer to hal_soc
1674 */
hal_qca6290_attach(struct hal_soc * hal_soc)1675 void hal_qca6290_attach(struct hal_soc *hal_soc)
1676 {
1677 hal_soc->hw_srng_table = hw_srng_table_6290;
1678 hal_srng_hw_reg_offset_init_generic(hal_soc);
1679
1680 hal_hw_txrx_default_ops_attach_li(hal_soc);
1681 hal_hw_txrx_ops_attach_6290(hal_soc);
1682 }
1683