1 /*
2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
3 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for
6 * any purpose with or without fee is hereby granted, provided that the
7 * above copyright notice and this permission notice appear in all
8 * copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17 * PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #ifndef _HAL_INTERNAL_H_
21 #define _HAL_INTERNAL_H_
22
23 #include "qdf_types.h"
24 #include "qdf_atomic.h"
25 #include "qdf_lock.h"
26 #include "qdf_mem.h"
27 #include "qdf_nbuf.h"
28 #include "pld_common.h"
29 #if defined(FEATURE_HAL_DELAYED_REG_WRITE)
30 #include "qdf_defer.h"
31 #include "qdf_timer.h"
32 #endif
33
34 #define hal_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_HAL, params)
35 #define hal_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_HAL, params)
36 #define hal_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_HAL, params)
37 #define hal_info(params...) \
38 __QDF_TRACE_FL(QDF_TRACE_LEVEL_INFO_HIGH, QDF_MODULE_ID_HAL, ## params)
39 #define hal_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params)
40
41 #define hal_alert_rl(params...) QDF_TRACE_FATAL_RL(QDF_MODULE_ID_HAL, params)
42 #define hal_err_rl(params...) QDF_TRACE_ERROR_RL(QDF_MODULE_ID_HAL, params)
43 #define hal_warn_rl(params...) QDF_TRACE_WARN_RL(QDF_MODULE_ID_HAL, params)
44 #define hal_info_rl(params...) QDF_TRACE_INFO_RL(QDF_MODULE_ID_HAL, params)
45 #define hal_debug_rl(params...) QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_HAL, params)
46
47 #ifdef ENABLE_VERBOSE_DEBUG
48 extern bool is_hal_verbose_debug_enabled;
49 #define hal_verbose_debug(params...) \
50 if (unlikely(is_hal_verbose_debug_enabled)) \
51 do {\
52 QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params); \
53 } while (0)
54 #define hal_verbose_hex_dump(params...) \
55 if (unlikely(is_hal_verbose_debug_enabled)) \
56 do {\
57 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, \
58 QDF_TRACE_LEVEL_DEBUG, \
59 params); \
60 } while (0)
61 #else
62 #define hal_verbose_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params)
63 #define hal_verbose_hex_dump(params...) \
64 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_DEBUG, \
65 params)
66 #endif
67
68 /*
69 * Given the offset of a field in bytes, returns uint8_t *
70 */
71 #define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \
72 (((uint8_t *)(_ptr)) + (_off_in_bytes))
73
74 /*
75 * Given the offset of a field in bytes, returns uint32_t *
76 */
77 #define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \
78 (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2))
79
80 /*
81 * Given the offset of a field in bytes, returns uint64_t *
82 */
83 #define _OFFSET_TO_QWORD_PTR(_ptr, _off_in_bytes) \
84 (((uint64_t *)(_ptr)) + ((_off_in_bytes) >> 3))
85
86 #define _HAL_MS(_word, _mask, _shift) \
87 (((_word) & (_mask)) >> (_shift))
88
89 /*
90 * Get number of QWORDS possible for num.
91 * Its the caller's duty to make sure num is a multiple of QWORD (8)
92 */
93 #define HAL_GET_NUM_QWORDS(num) ((num) >> 3)
94
95 /*
96 * Get number of DWORDS possible for num.
97 * Its the caller's duty to make sure num is a multiple of DWORD (8)
98 */
99 #define HAL_GET_NUM_DWORDS(num) ((num) >> 2)
100
101 struct hal_hw_cc_config {
102 uint32_t lut_base_addr_31_0;
103 uint32_t cc_global_en:1,
104 page_4k_align:1,
105 cookie_offset_msb:5,
106 cookie_page_msb:5,
107 lut_base_addr_39_32:8,
108 wbm2sw6_cc_en:1,
109 wbm2sw5_cc_en:1,
110 wbm2sw4_cc_en:1,
111 wbm2sw3_cc_en:1,
112 wbm2sw2_cc_en:1,
113 wbm2sw1_cc_en:1,
114 wbm2sw0_cc_en:1,
115 wbm2fw_cc_en:1,
116 error_path_cookie_conv_en:1,
117 release_path_cookie_conv_en:1,
118 reserved:2;
119 };
120
121 struct hal_soc_handle;
122 /*
123 * typedef hal_soc_handle_t - opaque handle for DP HAL soc
124 */
125 typedef struct hal_soc_handle *hal_soc_handle_t;
126
127 struct hal_ring_desc;
128 /*
129 * typedef hal_ring_desc_t - opaque handle for DP ring descriptor
130 */
131 typedef struct hal_ring_desc *hal_ring_desc_t;
132
133 struct hal_link_desc;
134 /*
135 * typedef hal_link_desc_t - opaque handle for DP link descriptor
136 */
137 typedef struct hal_link_desc *hal_link_desc_t;
138
139 struct hal_rxdma_desc;
140 /*
141 * typedef hal_rxdma_desc_t - opaque handle for DP rxdma dst ring descriptor
142 */
143 typedef struct hal_rxdma_desc *hal_rxdma_desc_t;
144
145 struct hal_buff_addrinfo;
146 /*
147 * typedef hal_buff_addrinfo_t - opaque handle for DP buffer address info
148 */
149 typedef struct hal_buff_addrinfo *hal_buff_addrinfo_t;
150
151 struct hal_rx_mon_desc_info;
152 /*
153 * typedef hal_rx_mon_desc_info_t - opaque handle for sw monitor ring desc info
154 */
155 typedef struct hal_rx_mon_desc_info *hal_rx_mon_desc_info_t;
156
157 struct hal_buf_info;
158 /*
159 * typedef hal_buf_info_t - opaque handle for HAL buffer info
160 */
161 typedef struct hal_buf_info *hal_buf_info_t;
162
163 struct rx_msdu_desc_info;
164 /*
165 * typedef rx_msdu_desc_info_t - opaque handle for rx MSDU descriptor info
166 */
167 typedef struct rx_msdu_desc_info *rx_msdu_desc_info_t;
168
169 /*
170 * Opaque handler for PPE VP config.
171 */
172 union hal_tx_ppe_vp_config;
173 union hal_tx_cmn_config_ppe;
174 union hal_tx_bank_config;
175 union hal_tx_ppe_idx_map_config;
176
177 #ifndef WLAN_SOFTUMAC_SUPPORT
178 /* TBD: This should be movded to shared HW header file */
179 enum hal_srng_ring_id {
180 /* UMAC rings */
181 HAL_SRNG_REO2SW0 = 0,
182 HAL_SRNG_REO2SW1 = 1,
183 HAL_SRNG_REO2SW2 = 2,
184 HAL_SRNG_REO2SW3 = 3,
185 HAL_SRNG_REO2SW4 = 4,
186 HAL_SRNG_REO2SW5 = 5,
187 HAL_SRNG_REO2SW6 = 6,
188 HAL_SRNG_REO2SW7 = 7,
189 HAL_SRNG_REO2SW8 = 8,
190 HAL_SRNG_REO2TCL = 9,
191 HAL_SRNG_REO2PPE = 10,
192 /* 11-15 unused */
193 HAL_SRNG_SW2REO = 16,
194 HAL_SRNG_SW2REO1 = 17,
195 HAL_SRNG_SW2REO2 = 18,
196 HAL_SRNG_SW2REO3 = 19,
197 HAL_SRNG_REO_CMD = 20,
198 HAL_SRNG_REO_STATUS = 21,
199 /* 22-23 unused */
200 HAL_SRNG_SW2TCL1 = 24,
201 HAL_SRNG_SW2TCL2 = 25,
202 HAL_SRNG_SW2TCL3 = 26,
203 HAL_SRNG_SW2TCL4 = 27,
204 HAL_SRNG_SW2TCL5 = 28,
205 HAL_SRNG_SW2TCL6 = 29,
206 HAL_SRNG_PPE2TCL1 = 30,
207 /* 31-39 unused */
208 HAL_SRNG_SW2TCL_CMD = 40,
209 HAL_SRNG_TCL_STATUS = 41,
210 HAL_SRNG_SW2TCL_CREDIT = 42,
211 /* 43-63 unused */
212 HAL_SRNG_CE_0_SRC = 64,
213 HAL_SRNG_CE_1_SRC = 65,
214 HAL_SRNG_CE_2_SRC = 66,
215 HAL_SRNG_CE_3_SRC = 67,
216 HAL_SRNG_CE_4_SRC = 68,
217 HAL_SRNG_CE_5_SRC = 69,
218 HAL_SRNG_CE_6_SRC = 70,
219 HAL_SRNG_CE_7_SRC = 71,
220 HAL_SRNG_CE_8_SRC = 72,
221 HAL_SRNG_CE_9_SRC = 73,
222 HAL_SRNG_CE_10_SRC = 74,
223 HAL_SRNG_CE_11_SRC = 75,
224 HAL_SRNG_CE_12_SRC = 76,
225 HAL_SRNG_CE_13_SRC = 77,
226 HAL_SRNG_CE_14_SRC = 78,
227 HAL_SRNG_CE_15_SRC = 79,
228 /* 80 */
229 HAL_SRNG_CE_0_DST = 81,
230 HAL_SRNG_CE_1_DST = 82,
231 HAL_SRNG_CE_2_DST = 83,
232 HAL_SRNG_CE_3_DST = 84,
233 HAL_SRNG_CE_4_DST = 85,
234 HAL_SRNG_CE_5_DST = 86,
235 HAL_SRNG_CE_6_DST = 87,
236 HAL_SRNG_CE_7_DST = 89,
237 HAL_SRNG_CE_8_DST = 90,
238 HAL_SRNG_CE_9_DST = 91,
239 HAL_SRNG_CE_10_DST = 92,
240 HAL_SRNG_CE_11_DST = 93,
241 HAL_SRNG_CE_12_DST = 94,
242 HAL_SRNG_CE_13_DST = 95,
243 HAL_SRNG_CE_14_DST = 96,
244 HAL_SRNG_CE_15_DST = 97,
245 /* 98-99 unused */
246 HAL_SRNG_CE_0_DST_STATUS = 100,
247 HAL_SRNG_CE_1_DST_STATUS = 101,
248 HAL_SRNG_CE_2_DST_STATUS = 102,
249 HAL_SRNG_CE_3_DST_STATUS = 103,
250 HAL_SRNG_CE_4_DST_STATUS = 104,
251 HAL_SRNG_CE_5_DST_STATUS = 105,
252 HAL_SRNG_CE_6_DST_STATUS = 106,
253 HAL_SRNG_CE_7_DST_STATUS = 107,
254 HAL_SRNG_CE_8_DST_STATUS = 108,
255 HAL_SRNG_CE_9_DST_STATUS = 109,
256 HAL_SRNG_CE_10_DST_STATUS = 110,
257 HAL_SRNG_CE_11_DST_STATUS = 111,
258 HAL_SRNG_CE_12_DST_STATUS = 112,
259 HAL_SRNG_CE_13_DST_STATUS = 113,
260 HAL_SRNG_CE_14_DST_STATUS = 114,
261 HAL_SRNG_CE_15_DST_STATUS = 115,
262 /* 116-119 unused */
263 HAL_SRNG_WBM_IDLE_LINK = 120,
264 HAL_SRNG_WBM_SW_RELEASE = 121,
265 HAL_SRNG_WBM_SW1_RELEASE = 122,
266 HAL_SRNG_WBM_PPE_RELEASE = 123,
267 /* 124-127 unused */
268 HAL_SRNG_WBM2SW0_RELEASE = 128,
269 HAL_SRNG_WBM2SW1_RELEASE = 129,
270 HAL_SRNG_WBM2SW2_RELEASE = 130,
271 HAL_SRNG_WBM2SW3_RELEASE = 131,
272 HAL_SRNG_WBM2SW4_RELEASE = 132,
273 HAL_SRNG_WBM2SW5_RELEASE = 133,
274 HAL_SRNG_WBM2SW6_RELEASE = 134,
275 HAL_SRNG_WBM_ERROR_RELEASE = 135,
276 /* 136-158 unused */
277 HAL_SRNG_UMAC_ID_END = 159,
278 /* Common DMAC rings shared by all LMACs */
279 HAL_SRNG_SW2RXDMA_BUF0 = 160,
280 HAL_SRNG_SW2RXDMA_BUF1 = 161,
281 HAL_SRNG_SW2RXDMA_BUF2 = 162,
282 /* 163-167 unused */
283 HAL_SRNG_SW2RXMON_BUF0 = 168,
284 /* 169-175 unused */
285 /* 177-183 unused */
286 HAL_SRNG_DMAC_CMN_ID_END = 183,
287 /* LMAC rings - The following set will be replicated for each LMAC */
288 HAL_SRNG_LMAC1_ID_START = 184,
289 HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START,
290 HAL_SRNG_WMAC1_SW2RXDMA1_BUF,
291 #ifdef IPA_OFFLOAD
292 HAL_SRNG_WMAC1_SW2RXDMA0_BUF1,
293 #ifdef IPA_WDI3_VLAN_SUPPORT
294 HAL_SRNG_WMAC1_SW2RXDMA0_BUF2,
295 #endif
296 #endif
297 #ifdef FEATURE_DIRECT_LINK
298 HAL_SRNG_WMAC1_RX_DIRECT_LINK_SW_REFILL_RING,
299 #endif
300 HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
301 HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF,
302 HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
303 HAL_SRNG_WMAC1_RXDMA2SW0,
304 HAL_SRNG_WMAC1_RXDMA2SW1,
305 HAL_SRNG_WMAC1_RXMON2SW0 = HAL_SRNG_WMAC1_RXDMA2SW1,
306 HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
307 #ifdef WLAN_FEATURE_CIF_CFR
308 HAL_SRNG_WIFI_POS_SRC_DMA_RING,
309 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
310 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING1,
311 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING2,
312 #else
313 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
314 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING1,
315 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING2,
316 #endif
317 HAL_SRNG_WMAC1_TXMON2SW0,
318 HAL_SRNG_SW2TXMON_BUF0,
319 HAL_SRNG_LMAC1_ID_END = (HAL_SRNG_SW2TXMON_BUF0 + 2),
320 };
321 #else
322 /* lmac rings are remains same for evros */
323 enum hal_srng_ring_id {
324 HAL_SRNG_LMAC1_ID_START,
325 HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START,
326 HAL_SRNG_WMAC1_SW2RXDMA1_BUF,
327 #ifdef IPA_OFFLOAD
328 HAL_SRNG_WMAC1_SW2RXDMA0_BUF1,
329 #ifdef IPA_WDI3_VLAN_SUPPORT
330 HAL_SRNG_WMAC1_SW2RXDMA0_BUF2,
331 #endif
332 #endif
333 #ifdef FEATURE_DIRECT_LINK
334 HAL_SRNG_WMAC1_RX_DIRECT_LINK_SW_REFILL_RING,
335 #endif
336 HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
337 HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF,
338 HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
339 HAL_SRNG_WMAC1_RXDMA2SW0,
340 HAL_SRNG_WMAC1_RXDMA2SW1,
341 HAL_SRNG_WMAC1_RXMON2SW0 = HAL_SRNG_WMAC1_RXDMA2SW1,
342 HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
343 #ifdef WLAN_FEATURE_CIF_CFR
344 HAL_SRNG_WIFI_POS_SRC_DMA_RING,
345 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
346 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING1,
347 #else
348 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
349 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING1,
350 #endif
351 HAL_SRNG_WMAC1_TXMON2SW0,
352 HAL_SRNG_SW2TXMON_BUF0,
353 HAL_SRNG_WMAC1_SW2RXDMA_LINK_RING = HAL_SRNG_SW2TXMON_BUF0 + 2,
354 HAL_SRNG_LMAC1_ID_END = HAL_SRNG_WMAC1_SW2RXDMA_LINK_RING,
355 };
356
357 #define HAL_SRNG_DMAC_CMN_ID_END 0
358 #define HAL_SRNG_WBM_IDLE_LINK 120
359 #endif
360
361 #define HAL_RXDMA_MAX_RING_SIZE 0xFFFF
362 #define HAL_MAX_LMACS 3
363 #define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START)
364 #define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC)
365
366 #define HAL_SRNG_ID_MAX (HAL_SRNG_DMAC_CMN_ID_END + HAL_MAX_LMAC_RINGS)
367
368 /* SRNG type to be passed in APIs hal_srng_get_entrysize and hal_srng_setup */
369 enum hal_ring_type {
370 REO_DST = 0,
371 REO_EXCEPTION = 1,
372 REO_REINJECT = 2,
373 REO_CMD = 3,
374 REO_STATUS = 4,
375 TCL_DATA = 5,
376 TCL_CMD_CREDIT = 6,
377 TCL_STATUS = 7,
378 CE_SRC = 8,
379 CE_DST = 9,
380 CE_DST_STATUS = 10,
381 WBM_IDLE_LINK = 11,
382 SW2WBM_RELEASE = 12,
383 WBM2SW_RELEASE = 13,
384 RXDMA_BUF = 14,
385 RXDMA_DST = 15,
386 RXDMA_MONITOR_BUF = 16,
387 RXDMA_MONITOR_STATUS = 17,
388 RXDMA_MONITOR_DST = 18,
389 RXDMA_MONITOR_DESC = 19,
390 DIR_BUF_RX_DMA_SRC = 20,
391 #ifdef WLAN_FEATURE_CIF_CFR
392 WIFI_POS_SRC,
393 #endif
394 REO2PPE,
395 PPE2TCL,
396 PPE_RELEASE,
397 TX_MONITOR_BUF,
398 TX_MONITOR_DST,
399 SW2RXDMA_NEW,
400 SW2RXDMA_LINK_RELEASE,
401 MAX_RING_TYPES
402 };
403
404 enum SRNG_REGISTERS {
405 DST_HP = 0,
406 DST_TP,
407 DST_ID,
408 DST_MISC,
409 DST_HP_ADDR_LSB,
410 DST_HP_ADDR_MSB,
411 DST_MSI1_BASE_LSB,
412 DST_MSI1_BASE_MSB,
413 DST_MSI1_DATA,
414 DST_MISC_1,
415 #ifdef CONFIG_BERYLLIUM
416 DST_MSI2_BASE_LSB,
417 DST_MSI2_BASE_MSB,
418 DST_MSI2_DATA,
419 #endif
420 DST_BASE_LSB,
421 DST_BASE_MSB,
422 DST_PRODUCER_INT_SETUP,
423 #ifdef CONFIG_BERYLLIUM
424 DST_PRODUCER_INT2_SETUP,
425 #endif
426
427 SRC_HP,
428 SRC_TP,
429 SRC_ID,
430 SRC_MISC,
431 SRC_TP_ADDR_LSB,
432 SRC_TP_ADDR_MSB,
433 SRC_MSI1_BASE_LSB,
434 SRC_MSI1_BASE_MSB,
435 SRC_MSI1_DATA,
436 SRC_BASE_LSB,
437 SRC_BASE_MSB,
438 SRC_CONSUMER_INT_SETUP_IX0,
439 SRC_CONSUMER_INT_SETUP_IX1,
440 #ifdef DP_UMAC_HW_RESET_SUPPORT
441 SRC_CONSUMER_PREFETCH_TIMER,
442 #endif
443 SRNG_REGISTER_MAX,
444 };
445
446 enum hal_srng_dir {
447 HAL_SRNG_SRC_RING,
448 HAL_SRNG_DST_RING
449 };
450
451 /**
452 * enum hal_reo_remap_reg - REO remap registers
453 * @HAL_REO_REMAP_REG_IX0: reo remap reg IX0
454 * @HAL_REO_REMAP_REG_IX1: reo remap reg IX1
455 * @HAL_REO_REMAP_REG_IX2: reo remap reg IX2
456 * @HAL_REO_REMAP_REG_IX3: reo remap reg IX3
457 */
458 enum hal_reo_remap_reg {
459 HAL_REO_REMAP_REG_IX0,
460 HAL_REO_REMAP_REG_IX1,
461 HAL_REO_REMAP_REG_IX2,
462 HAL_REO_REMAP_REG_IX3
463 };
464
465 /* Lock wrappers for SRNG */
466 #define hal_srng_lock_t qdf_spinlock_t
467 #define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock)
468 #define SRNG_LOCK(_lock) qdf_spin_lock_bh(_lock)
469 #define SRNG_TRY_LOCK(_lock) qdf_spin_trylock_bh(_lock)
470 #define SRNG_UNLOCK(_lock) qdf_spin_unlock_bh(_lock)
471 #define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock)
472
473 struct hal_soc;
474 struct hal_ring_handle;
475
476 /*
477 * typedef hal_ring_handle_t - opaque handle for DP HAL SRNG
478 */
479 typedef struct hal_ring_handle *hal_ring_handle_t;
480
481 #define MAX_SRNG_REG_GROUPS 2
482
483 /* Hal Srng bit mask
484 * HAL_SRNG_FLUSH_EVENT: SRNG HP TP flush in case of link down
485 */
486 #define HAL_SRNG_FLUSH_EVENT BIT(0)
487
488 #if defined(FEATURE_HAL_DELAYED_REG_WRITE)
489
490 /**
491 * struct hal_reg_write_q_elem - delayed register write queue element
492 * @srng: hal_srng queued for a delayed write
493 * @addr: iomem address of the register
494 * @enqueue_val: register value at the time of delayed write enqueue
495 * @dequeue_val: register value at the time of delayed write dequeue
496 * @valid: whether this entry is valid or not
497 * @enqueue_time: enqueue time (qdf_log_timestamp)
498 * @work_scheduled_time: work scheduled time (qdf_log_timestamp)
499 * @dequeue_time: dequeue time (qdf_log_timestamp)
500 * @cpu_id: record cpuid when schedule work
501 * @ring_id: saved srng id
502 */
503 struct hal_reg_write_q_elem {
504 struct hal_srng *srng;
505 void __iomem *addr;
506 uint32_t enqueue_val;
507 uint32_t dequeue_val;
508 uint8_t valid;
509 qdf_time_t enqueue_time;
510 qdf_time_t work_scheduled_time;
511 qdf_time_t dequeue_time;
512 int cpu_id;
513 qdf_atomic_t ring_id;
514 };
515
516 /**
517 * struct hal_reg_write_srng_stats - srng stats to keep track of register writes
518 * @enqueues: writes enqueued to delayed work
519 * @dequeues: writes dequeued from delayed work (not written yet)
520 * @coalesces: writes not enqueued since srng is already queued up
521 * @direct: writes not enqueued and written to register directly
522 * @dequeue_delay: dequeue operation be delayed
523 */
524 struct hal_reg_write_srng_stats {
525 uint32_t enqueues;
526 uint32_t dequeues;
527 uint32_t coalesces;
528 uint32_t direct;
529 uint32_t dequeue_delay;
530 };
531
532 /**
533 * enum hal_reg_sched_delay - ENUM for write sched delay histogram
534 * @REG_WRITE_SCHED_DELAY_SUB_100us: index for delay < 100us
535 * @REG_WRITE_SCHED_DELAY_SUB_1000us: index for delay < 1000us
536 * @REG_WRITE_SCHED_DELAY_SUB_5000us: index for delay < 5000us
537 * @REG_WRITE_SCHED_DELAY_GT_5000us: index for delay >= 5000us
538 * @REG_WRITE_SCHED_DELAY_HIST_MAX: Max value (nnsize of histogram array)
539 */
540 enum hal_reg_sched_delay {
541 REG_WRITE_SCHED_DELAY_SUB_100us,
542 REG_WRITE_SCHED_DELAY_SUB_1000us,
543 REG_WRITE_SCHED_DELAY_SUB_5000us,
544 REG_WRITE_SCHED_DELAY_GT_5000us,
545 REG_WRITE_SCHED_DELAY_HIST_MAX,
546 };
547
548 /**
549 * struct hal_reg_write_soc_stats - soc stats to keep track of register writes
550 * @enqueues: writes enqueued to delayed work
551 * @dequeues: writes dequeued from delayed work (not written yet)
552 * @coalesces: writes not enqueued since srng is already queued up
553 * @direct: writes not enqueud and writted to register directly
554 * @prevent_l1_fails: prevent l1 API failed
555 * @q_depth: current queue depth in delayed register write queue
556 * @max_q_depth: maximum queue for delayed register write queue
557 * @sched_delay: = kernel work sched delay + bus wakeup delay, histogram
558 * @dequeue_delay: dequeue operation be delayed
559 */
560 struct hal_reg_write_soc_stats {
561 qdf_atomic_t enqueues;
562 uint32_t dequeues;
563 qdf_atomic_t coalesces;
564 qdf_atomic_t direct;
565 uint32_t prevent_l1_fails;
566 qdf_atomic_t q_depth;
567 uint32_t max_q_depth;
568 uint32_t sched_delay[REG_WRITE_SCHED_DELAY_HIST_MAX];
569 uint32_t dequeue_delay;
570 };
571 #endif
572
573 struct hal_offload_info {
574 uint8_t lro_eligible;
575 uint8_t tcp_proto;
576 uint8_t tcp_pure_ack;
577 uint8_t ipv6_proto;
578 uint8_t tcp_offset;
579 uint16_t tcp_csum;
580 uint16_t tcp_win;
581 uint32_t tcp_seq_num;
582 uint32_t tcp_ack_num;
583 uint32_t flow_id;
584 };
585
586 #ifdef WLAN_DP_SRNG_USAGE_WM_TRACKING
587 /**
588 * enum hal_srng_high_wm_bin - BIN for SRNG high watermark
589 * @HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT: <50% SRNG entries used
590 * @HAL_SRNG_HIGH_WM_BIN_50_to_60: 50-60% SRNG entries used
591 * @HAL_SRNG_HIGH_WM_BIN_60_to_70: 60-70% SRNG entries used
592 * @HAL_SRNG_HIGH_WM_BIN_70_to_80: 70-80% SRNG entries used
593 * @HAL_SRNG_HIGH_WM_BIN_80_to_90: 80-90% SRNG entries used
594 * @HAL_SRNG_HIGH_WM_BIN_90_to_100: 90-100% SRNG entries used
595 * @HAL_SRNG_HIGH_WM_BIN_MAX: maximum enumeration
596 */
597 enum hal_srng_high_wm_bin {
598 HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT,
599 HAL_SRNG_HIGH_WM_BIN_50_to_60,
600 HAL_SRNG_HIGH_WM_BIN_60_to_70,
601 HAL_SRNG_HIGH_WM_BIN_70_to_80,
602 HAL_SRNG_HIGH_WM_BIN_80_to_90,
603 HAL_SRNG_HIGH_WM_BIN_90_to_100,
604 HAL_SRNG_HIGH_WM_BIN_MAX,
605 };
606
607 /**
608 * struct hal_srng_high_wm_info - SRNG usage high watermark info
609 * @val: highest number of entries used in SRNG
610 * @timestamp: Timestamp when the max num entries were in used for a SRNG
611 * @bin_thresh: threshold for each bins
612 * @bins: Bins for srng usage
613 */
614 struct hal_srng_high_wm_info {
615 uint32_t val;
616 uint64_t timestamp;
617 uint32_t bin_thresh[HAL_SRNG_HIGH_WM_BIN_MAX];
618 uint32_t bins[HAL_SRNG_HIGH_WM_BIN_MAX];
619 };
620 #endif
621
622 #define DEFAULT_TSF_ID 1
623
624 /**
625 * enum hal_scratch_reg_enum - Enum to indicate scratch register values
626 * @PMM_QTIMER_GLOBAL_OFFSET_LO_US: QTIMER GLOBAL OFFSET LOW
627 * @PMM_QTIMER_GLOBAL_OFFSET_HI_US: QTIMER GLOBAL OFFSET HIGH
628 * @PMM_MAC0_TSF1_OFFSET_LO_US: MAC0 TSF1 OFFSET LOW
629 * @PMM_MAC0_TSF1_OFFSET_HI_US: MAC0 TSF1 OFFSET HIGH
630 * @PMM_MAC0_TSF2_OFFSET_LO_US: MAC0 TSF2 OFFSET LOW
631 * @PMM_MAC0_TSF2_OFFSET_HI_US: MAC0 TSF2 OFFSET HIGH
632 * @PMM_MAC1_TSF1_OFFSET_LO_US: MAC1 TSF1 OFFSET LOW
633 * @PMM_MAC1_TSF1_OFFSET_HI_US: MAC1 TSF1 OFFSET HIGH
634 * @PMM_MAC1_TSF2_OFFSET_LO_US: MAC1 TSF2 OFFSET LOW
635 * @PMM_MAC1_TSF2_OFFSET_HI_US: MAC1 TSF2 OFFSET HIGH
636 * @PMM_MLO_OFFSET_LO_US: MLO OFFSET LOW
637 * @PMM_MLO_OFFSET_HI_US: MLO OFFSET HIGH
638 * @PMM_TQM_CLOCK_OFFSET_LO_US: TQM CLOCK OFFSET LOW
639 * @PMM_TQM_CLOCK_OFFSET_HI_US: TQM CLOCK OFFSET HIGH
640 * @PMM_Q6_CRASH_REASON: Q6 CRASH REASON
641 * @PMM_SCRATCH_TWT_OFFSET: TWT OFFSET
642 * @PMM_PMM_REG_MAX: Max PMM REG value
643 */
644 enum hal_scratch_reg_enum {
645 PMM_QTIMER_GLOBAL_OFFSET_LO_US,
646 PMM_QTIMER_GLOBAL_OFFSET_HI_US,
647 PMM_MAC0_TSF1_OFFSET_LO_US,
648 PMM_MAC0_TSF1_OFFSET_HI_US,
649 PMM_MAC0_TSF2_OFFSET_LO_US,
650 PMM_MAC0_TSF2_OFFSET_HI_US,
651 PMM_MAC1_TSF1_OFFSET_LO_US,
652 PMM_MAC1_TSF1_OFFSET_HI_US,
653 PMM_MAC1_TSF2_OFFSET_LO_US,
654 PMM_MAC1_TSF2_OFFSET_HI_US,
655 PMM_MLO_OFFSET_LO_US,
656 PMM_MLO_OFFSET_HI_US,
657 PMM_TQM_CLOCK_OFFSET_LO_US,
658 PMM_TQM_CLOCK_OFFSET_HI_US,
659 PMM_Q6_CRASH_REASON,
660 PMM_SCRATCH_TWT_OFFSET,
661 PMM_PMM_REG_MAX
662 };
663
664 /**
665 * hal_get_tsf_enum(): API to get the enum corresponding to the mac and tsf id
666 *
667 * @tsf_id: tsf id
668 * @mac_id: mac id
669 * @tsf_enum_low: Pointer to update low scratch register
670 * @tsf_enum_hi: Pointer to update hi scratch register
671 *
672 * Return: void
673 */
674 static inline void
hal_get_tsf_enum(uint32_t tsf_id,uint32_t mac_id,enum hal_scratch_reg_enum * tsf_enum_low,enum hal_scratch_reg_enum * tsf_enum_hi)675 hal_get_tsf_enum(uint32_t tsf_id, uint32_t mac_id,
676 enum hal_scratch_reg_enum *tsf_enum_low,
677 enum hal_scratch_reg_enum *tsf_enum_hi)
678 {
679 if (mac_id == 0) {
680 if (tsf_id == 0) {
681 *tsf_enum_low = PMM_MAC0_TSF1_OFFSET_LO_US;
682 *tsf_enum_hi = PMM_MAC0_TSF1_OFFSET_HI_US;
683 } else if (tsf_id == 1) {
684 *tsf_enum_low = PMM_MAC0_TSF2_OFFSET_LO_US;
685 *tsf_enum_hi = PMM_MAC0_TSF2_OFFSET_HI_US;
686 }
687 } else if (mac_id == 1) {
688 if (tsf_id == 0) {
689 *tsf_enum_low = PMM_MAC1_TSF1_OFFSET_LO_US;
690 *tsf_enum_hi = PMM_MAC1_TSF1_OFFSET_HI_US;
691 } else if (tsf_id == 1) {
692 *tsf_enum_low = PMM_MAC1_TSF2_OFFSET_LO_US;
693 *tsf_enum_hi = PMM_MAC1_TSF2_OFFSET_HI_US;
694 }
695 }
696 }
697
698 #ifdef HAL_SRNG_REG_HIS_DEBUG
699
700 #define HAL_SRNG_REG_MAX_ENTRIES 64
701
702 /**
703 * struct hal_srng_reg_his_entry - history entry for single srng pointer
704 * register update
705 * @write_time: register write timestamp
706 * @write_value: register write value
707 */
708 struct hal_srng_reg_his_entry {
709 qdf_time_t write_time;
710 uint32_t write_value;
711 };
712
713 /**
714 * struct hal_srng_reg_his_ctx - context for srng pointer writing history
715 * @current_idx: the index which has recorded srng pointer writing
716 * @reg_his_arr: array to record the history
717 */
718 struct hal_srng_reg_his_ctx {
719 qdf_atomic_t current_idx;
720 struct hal_srng_reg_his_entry reg_his_arr[HAL_SRNG_REG_MAX_ENTRIES];
721 };
722 #endif
723
724 /* Common SRNG ring structure for source and destination rings */
725 struct hal_srng {
726 /* Unique SRNG ring ID */
727 uint8_t ring_id;
728
729 /* Ring initialization done */
730 uint8_t initialized;
731
732 /* Interrupt/MSI value assigned to this ring */
733 int irq;
734
735 /* Physical base address of the ring */
736 qdf_dma_addr_t ring_base_paddr;
737
738 /* Virtual base address of the ring */
739 uint32_t *ring_base_vaddr;
740
741 /* virtual address end */
742 uint32_t *ring_vaddr_end;
743
744 /* Number of entries in ring */
745 uint32_t num_entries;
746
747 /* Ring size */
748 uint32_t ring_size;
749
750 /* Ring size mask */
751 uint32_t ring_size_mask;
752
753 /* Size of ring entry */
754 uint32_t entry_size;
755
756 /* Interrupt timer threshold – in micro seconds */
757 uint32_t intr_timer_thres_us;
758
759 /* Interrupt batch counter threshold – in number of ring entries */
760 uint32_t intr_batch_cntr_thres_entries;
761
762 /* Applicable only for CE dest ring */
763 uint32_t prefetch_timer;
764
765 /* MSI Address */
766 qdf_dma_addr_t msi_addr;
767
768 /* MSI data */
769 uint32_t msi_data;
770
771 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
772 /* MSI2 Address */
773 qdf_dma_addr_t msi2_addr;
774
775 /* MSI2 data */
776 uint32_t msi2_data;
777 #endif
778
779 /* Misc flags */
780 uint32_t flags;
781
782 /* Lock for serializing ring index updates */
783 hal_srng_lock_t lock;
784
785 /* Start offset of SRNG register groups for this ring
786 * TBD: See if this is required - register address can be derived
787 * from ring ID
788 */
789 void *hwreg_base[MAX_SRNG_REG_GROUPS];
790
791 /* Ring type/name */
792 enum hal_ring_type ring_type;
793
794 /* Source or Destination ring */
795 enum hal_srng_dir ring_dir;
796
797 union {
798 struct {
799 /* SW tail pointer */
800 uint32_t tp;
801
802 /* Shadow head pointer location to be updated by HW */
803 uint32_t *hp_addr;
804
805 /* Cached head pointer */
806 uint32_t cached_hp;
807
808 /* Tail pointer location to be updated by SW – This
809 * will be a register address and need not be
810 * accessed through SW structure */
811 uint32_t *tp_addr;
812
813 /* Current SW loop cnt */
814 uint32_t loop_cnt;
815
816 /* max transfer size */
817 uint16_t max_buffer_length;
818
819 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
820 /* near full IRQ supported */
821 uint16_t nf_irq_support;
822
823 /* High threshold for Near full IRQ */
824 uint16_t high_thresh;
825 #endif
826 } dst_ring;
827
828 struct {
829 /* SW head pointer */
830 uint32_t hp;
831
832 /* SW reap head pointer */
833 uint32_t reap_hp;
834
835 /* Shadow tail pointer location to be updated by HW */
836 uint32_t *tp_addr;
837
838 /* Cached tail pointer */
839 uint32_t cached_tp;
840
841 /* Head pointer location to be updated by SW – This
842 * will be a register address and need not be accessed
843 * through SW structure */
844 uint32_t *hp_addr;
845
846 /* Low threshold – in number of ring entries */
847 uint32_t low_threshold;
848 } src_ring;
849 } u;
850
851 struct hal_soc *hal_soc;
852
853 /* Number of times hp/tp updated in runtime resume */
854 uint32_t flush_count;
855 /* hal srng event flag*/
856 unsigned long srng_event;
857 /* last flushed time stamp */
858 uint64_t last_flush_ts;
859 #if defined(CLEAR_SW2TCL_CONSUMED_DESC)
860 /* last ring desc entry cleared */
861 uint32_t last_desc_cleared;
862 #endif
863 #if defined(FEATURE_HAL_DELAYED_REG_WRITE)
864 /* flag to indicate whether srng is already queued for delayed write */
865 uint8_t reg_write_in_progress;
866 /* last dequeue elem time stamp */
867 qdf_time_t last_dequeue_time;
868
869 /* srng specific delayed write stats */
870 struct hal_reg_write_srng_stats wstats;
871
872 union {
873 uint32_t updated_hp;
874 uint32_t updated_tp;
875 };
876 uint32_t force_cnt;
877 #endif
878 #ifdef WLAN_DP_SRNG_USAGE_WM_TRACKING
879 struct hal_srng_high_wm_info high_wm;
880 #endif
881 /* Timer threshold to issue ring pointer update - in micro seconds */
882 uint16_t pointer_timer_threshold;
883 /* Number threshold of ring entries to issue pointer update */
884 uint8_t pointer_num_threshold;
885 #ifdef HAL_SRNG_REG_HIS_DEBUG
886 /* pointer register writing history for this srng */
887 struct hal_srng_reg_his_ctx *reg_his_ctx;
888 #endif
889 };
890
891 #ifdef HAL_SRNG_REG_HIS_DEBUG
892 /**
893 * hal_srng_reg_his_init() - SRNG register history context initialize
894 *
895 * @srng: SRNG handle pointer
896 *
897 * Return: None
898 */
899 static inline
hal_srng_reg_his_init(struct hal_srng * srng)900 void hal_srng_reg_his_init(struct hal_srng *srng)
901 {
902 qdf_atomic_set(&srng->reg_his_ctx->current_idx, -1);
903 }
904
905 /**
906 * hal_srng_reg_his_add() - add pointer writing history to SRNG
907 *
908 * @srng: SRNG handle pointer
909 * @reg_val: pointer value to write
910 *
911 * Return: None
912 */
913 static inline
hal_srng_reg_his_add(struct hal_srng * srng,uint32_t reg_val)914 void hal_srng_reg_his_add(struct hal_srng *srng, uint32_t reg_val)
915 {
916 uint32_t write_idx;
917 struct hal_srng_reg_his_entry *reg_his_entry;
918
919 write_idx = qdf_atomic_inc_return(&srng->reg_his_ctx->current_idx);
920 write_idx = write_idx & (HAL_SRNG_REG_MAX_ENTRIES - 1);
921
922 reg_his_entry = &srng->reg_his_ctx->reg_his_arr[write_idx];
923
924 reg_his_entry->write_time = qdf_get_log_timestamp();
925 reg_his_entry->write_value = reg_val;
926 }
927 #else
928 static inline
hal_srng_reg_his_init(struct hal_srng * srng)929 void hal_srng_reg_his_init(struct hal_srng *srng)
930 {
931 }
932
933 static inline
hal_srng_reg_his_add(struct hal_srng * srng,uint32_t reg_val)934 void hal_srng_reg_his_add(struct hal_srng *srng, uint32_t reg_val)
935 {
936 }
937 #endif
938
939 /* HW SRNG configuration table */
940 struct hal_hw_srng_config {
941 int start_ring_id;
942 uint16_t max_rings;
943 uint16_t entry_size;
944 uint32_t reg_start[MAX_SRNG_REG_GROUPS];
945 uint16_t reg_size[MAX_SRNG_REG_GROUPS];
946 uint8_t lmac_ring;
947 enum hal_srng_dir ring_dir;
948 uint32_t max_size;
949 bool nf_irq_support;
950 bool dmac_cmn_ring;
951 };
952
953 #define MAX_SHADOW_REGISTERS 40
954 #define MAX_GENERIC_SHADOW_REG 5
955
956 /**
957 * struct shadow_reg_config - Hal soc structure that contains
958 * the list of generic shadow registers
959 * @target_register: target reg offset
960 * @shadow_config_index: shadow config index in shadow config
961 * list sent to FW
962 * @va: virtual addr of shadow reg
963 *
964 * This structure holds the generic registers that are mapped to
965 * the shadow region and holds the mapping of the target
966 * register offset to shadow config index provided to FW during
967 * init
968 */
969 struct shadow_reg_config {
970 uint32_t target_register;
971 int shadow_config_index;
972 uint64_t va;
973 };
974
975 /* REO parameters to be passed to hal_reo_setup */
976 struct hal_reo_params {
977 /** rx hash steering enabled or disabled */
978 bool rx_hash_enabled;
979 /** reo remap 0 register */
980 uint32_t remap0;
981 /** reo remap 1 register */
982 uint32_t remap1;
983 /** reo remap 2 register */
984 uint32_t remap2;
985 /** fragment destination ring */
986 uint8_t frag_dst_ring;
987 /* Destination for alternate */
988 uint8_t alt_dst_ind_0;
989 /* reo_qref struct for mlo and non mlo table */
990 struct reo_queue_ref_table *reo_qref;
991 };
992
993 /**
994 * enum hal_reo_cmd_type: Enum for REO command type
995 * @CMD_GET_QUEUE_STATS: Get REO queue status/stats
996 * @CMD_FLUSH_QUEUE: Flush all frames in REO queue
997 * @CMD_FLUSH_CACHE: Flush descriptor entries in the cache
998 * @CMD_UNBLOCK_CACHE: Unblock a descriptor’s address that was blocked
999 * earlier with a ‘REO_FLUSH_CACHE’ command
1000 * @CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list
1001 * @CMD_UPDATE_RX_REO_QUEUE: Update REO queue settings
1002 */
1003 enum hal_reo_cmd_type {
1004 CMD_GET_QUEUE_STATS = 0,
1005 CMD_FLUSH_QUEUE = 1,
1006 CMD_FLUSH_CACHE = 2,
1007 CMD_UNBLOCK_CACHE = 3,
1008 CMD_FLUSH_TIMEOUT_LIST = 4,
1009 CMD_UPDATE_RX_REO_QUEUE = 5
1010 };
1011
1012 /**
1013 * enum hal_tx_mcast_mlo_reinject_notify
1014 * @HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY: MLO Mcast reinject routed to FW
1015 * @HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY: MLO Mcast reinject routed to TQM
1016 */
1017 enum hal_tx_mcast_mlo_reinject_notify {
1018 HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY = 0,
1019 HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY,
1020 };
1021
1022 /**
1023 * enum hal_tx_vdev_mismatch_notify
1024 * @HAL_TX_VDEV_MISMATCH_TQM_NOTIFY: vdev mismatch exception routed to TQM
1025 * @HAL_TX_VDEV_MISMATCH_FW_NOTIFY: vdev mismatch exception routed to FW
1026 */
1027 enum hal_tx_vdev_mismatch_notify {
1028 HAL_TX_VDEV_MISMATCH_TQM_NOTIFY = 0,
1029 HAL_TX_VDEV_MISMATCH_FW_NOTIFY,
1030 };
1031
1032 struct hal_rx_pkt_capture_flags {
1033 uint8_t encrypt_type;
1034 uint8_t fragment_flag;
1035 uint8_t fcs_err;
1036 uint32_t chan_freq;
1037 uint32_t rssi_comb;
1038 uint64_t tsft;
1039 };
1040
1041 /**
1042 * struct reo_queue_ref_table - Reo qref LUT addr
1043 * @mlo_reo_qref_table_vaddr: MLO table vaddr
1044 * @non_mlo_reo_qref_table_vaddr: Non MLO table vaddr
1045 * @mlo_reo_qref_table_paddr: MLO table paddr
1046 * @non_mlo_reo_qref_table_paddr: Non MLO table paddr
1047 * @reo_qref_table_en: Enable flag
1048 */
1049 struct reo_queue_ref_table {
1050 uint64_t *mlo_reo_qref_table_vaddr;
1051 uint64_t *non_mlo_reo_qref_table_vaddr;
1052 qdf_dma_addr_t mlo_reo_qref_table_paddr;
1053 qdf_dma_addr_t non_mlo_reo_qref_table_paddr;
1054 uint8_t reo_qref_table_en;
1055 };
1056
1057 struct hal_hw_txrx_ops {
1058 /* init and setup */
1059 void (*hal_srng_dst_hw_init)(struct hal_soc *hal,
1060 struct hal_srng *srng, bool idle_check,
1061 uint32_t idx);
1062 void (*hal_srng_src_hw_init)(struct hal_soc *hal,
1063 struct hal_srng *srng, bool idle_check,
1064 uint32_t idx);
1065
1066 void (*hal_srng_hw_disable)(struct hal_soc *hal,
1067 struct hal_srng *srng);
1068 void (*hal_get_hw_hptp)(struct hal_soc *hal,
1069 hal_ring_handle_t hal_ring_hdl,
1070 uint32_t *headp, uint32_t *tailp,
1071 uint8_t ring_type);
1072 void (*hal_reo_setup)(struct hal_soc *hal_soc, void *reoparams,
1073 int qref_reset);
1074 void (*hal_setup_link_idle_list)(
1075 struct hal_soc *hal_soc,
1076 qdf_dma_addr_t scatter_bufs_base_paddr[],
1077 void *scatter_bufs_base_vaddr[],
1078 uint32_t num_scatter_bufs,
1079 uint32_t scatter_buf_size,
1080 uint32_t last_buf_end_offset,
1081 uint32_t num_entries);
1082 qdf_iomem_t (*hal_get_window_address)(struct hal_soc *hal_soc,
1083 qdf_iomem_t addr);
1084 void (*hal_reo_set_err_dst_remap)(void *hal_soc);
1085 uint8_t (*hal_reo_enable_pn_in_dest)(void *hal_soc);
1086 void (*hal_reo_qdesc_setup)(hal_soc_handle_t hal_soc_hdl, int tid,
1087 uint32_t ba_window_size,
1088 uint32_t start_seq, void *hw_qdesc_vaddr,
1089 qdf_dma_addr_t hw_qdesc_paddr,
1090 int pn_type, uint8_t vdev_stats_id);
1091 uint32_t (*hal_gen_reo_remap_val)(enum hal_reo_remap_reg,
1092 uint8_t *ix0_map);
1093
1094 /* tx */
1095 void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id);
1096 void (*hal_tx_set_dscp_tid_map)(struct hal_soc *hal_soc, uint8_t *map,
1097 uint8_t id);
1098 void (*hal_tx_update_dscp_tid)(struct hal_soc *hal_soc, uint8_t tid,
1099 uint8_t id,
1100 uint8_t dscp);
1101 void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id);
1102 void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr,
1103 uint8_t pool_id, uint32_t desc_id,
1104 uint8_t type);
1105 void (*hal_tx_desc_set_search_type)(void *desc, uint8_t search_type);
1106 void (*hal_tx_desc_set_search_index)(void *desc, uint32_t search_index);
1107 void (*hal_tx_desc_set_cache_set_num)(void *desc, uint8_t search_index);
1108 void (*hal_tx_comp_get_status)(void *desc, void *ts,
1109 struct hal_soc *hal);
1110 uint8_t (*hal_tx_comp_get_release_reason)(void *hal_desc);
1111 uint8_t (*hal_get_wbm_internal_error)(void *hal_desc);
1112 void (*hal_tx_desc_set_mesh_en)(void *desc, uint8_t en);
1113 void (*hal_tx_init_cmd_credit_ring)(hal_soc_handle_t hal_soc_hdl,
1114 hal_ring_handle_t hal_ring_hdl);
1115 uint32_t (*hal_tx_comp_get_buffer_source)(void *hal_desc);
1116 uint32_t (*hal_tx_get_num_ppe_vp_tbl_entries)(
1117 hal_soc_handle_t hal_soc_hdl);
1118
1119 void (*hal_reo_config_reo2ppe_dest_info)(hal_soc_handle_t hal_soc_hdl);
1120
1121 void (*hal_tx_set_ppe_cmn_cfg)(hal_soc_handle_t hal_soc_hdl,
1122 union hal_tx_cmn_config_ppe *cmn_cfg);
1123 void (*hal_tx_set_ppe_vp_entry)(hal_soc_handle_t hal_soc_hdl,
1124 union hal_tx_ppe_vp_config *vp_cfg,
1125 int ppe_vp_idx);
1126 void (*hal_ppeds_cfg_ast_override_map_reg)(hal_soc_handle_t hal_soc_hdl,
1127 uint8_t idx, union hal_tx_ppe_idx_map_config *ppeds_idx_map);
1128 void (*hal_tx_set_ppe_pri2tid)(hal_soc_handle_t hal_soc_hdl,
1129 uint32_t val,
1130 uint8_t map_no);
1131 void (*hal_tx_update_ppe_pri2tid)(hal_soc_handle_t hal_soc_hdl,
1132 uint8_t pri,
1133 uint8_t tid);
1134 void (*hal_tx_dump_ppe_vp_entry)(hal_soc_handle_t hal_soc_hdl);
1135 void (*hal_tx_enable_pri2tid_map)(hal_soc_handle_t hal_soc_hdl,
1136 bool value, uint8_t ppe_vp_idx);
1137 void (*hal_tx_config_rbm_mapping_be)(hal_soc_handle_t hal_soc_hdl,
1138 hal_ring_handle_t hal_ring_hdl,
1139 uint8_t rbm_id);
1140
1141 /* rx */
1142 uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *);
1143 void (*hal_rx_mon_hw_desc_get_mpdu_status)(void *hw_desc_addr,
1144 struct mon_rx_status *rs);
1145 uint8_t (*hal_rx_get_tlv)(void *rx_tlv);
1146 int8_t (*hal_rx_phy_legacy_get_rssi)(uint8_t *rx_tlv);
1147
1148 void (*hal_rx_proc_phyrx_other_receive_info_tlv)(void *rx_tlv_hdr,
1149 void *ppdu_info_handle);
1150 void (*hal_rx_dump_msdu_end_tlv)(void *pkt_tlvs, uint8_t dbg_level);
1151 void (*hal_rx_dump_rx_attention_tlv)(void *pkt_tlvs, uint8_t dbg_level);
1152 void (*hal_rx_dump_msdu_start_tlv)(void *pkt_tlvs, uint8_t dbg_level);
1153 void (*hal_rx_dump_mpdu_start_tlv)(void *pkt_tlvs, uint8_t dbg_level);
1154 void (*hal_rx_dump_mpdu_end_tlv)(void *pkt_tlvs, uint8_t dbg_level);
1155 void (*hal_rx_dump_pkt_hdr_tlv)(void *pkt_tlvs, uint8_t dbg_level);
1156 uint32_t (*hal_get_link_desc_size)(void);
1157 uint32_t (*hal_rx_mpdu_start_tid_get)(uint8_t *buf);
1158 uint32_t (*hal_rx_msdu_start_reception_type_get)(uint8_t *buf);
1159 uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf);
1160 void* (*hal_rx_msdu_desc_info_get_ptr)(void *msdu_details_ptr);
1161 void* (*hal_rx_link_desc_msdu0_ptr)(void *msdu_link_ptr);
1162 void (*hal_reo_status_get_header)(hal_ring_desc_t ring_desc, int b,
1163 void *h);
1164 uint32_t (*hal_rx_status_get_tlv_info)(void *rx_tlv_hdr,
1165 void *ppdu_info,
1166 hal_soc_handle_t hal_soc_hdl,
1167 qdf_nbuf_t nbuf);
1168
1169 void (*hal_rx_wbm_rel_buf_paddr_get)(hal_ring_desc_t rx_desc,
1170 struct hal_buf_info *buf_info);
1171
1172 void (*hal_rx_wbm_err_info_get)(void *wbm_desc,
1173 void *wbm_er_info);
1174
1175 void (*hal_tx_set_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t *map);
1176 void (*hal_tx_update_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t pcp,
1177 uint8_t id);
1178 void (*hal_tx_set_tidmap_prty)(struct hal_soc *hal_soc, uint8_t prio);
1179
1180 /* rx */
1181 uint8_t (*hal_rx_get_rx_fragment_number)(uint8_t *buf);
1182 uint8_t (*hal_rx_msdu_end_da_is_mcbc_get)(uint8_t *buf);
1183 uint8_t (*hal_rx_msdu_end_is_tkip_mic_err)(uint8_t *buf);
1184 uint8_t (*hal_rx_msdu_end_sa_is_valid_get)(uint8_t *buf);
1185 uint16_t (*hal_rx_msdu_end_sa_idx_get)(uint8_t *buf);
1186 uint32_t (*hal_rx_desc_is_first_msdu)(void *hw_desc_addr);
1187 uint32_t (*hal_rx_msdu_end_l3_hdr_padding_get)(uint8_t *buf);
1188 uint32_t (*hal_rx_encryption_info_valid)(uint8_t *buf);
1189 void (*hal_rx_print_pn)(uint8_t *buf);
1190 uint8_t (*hal_rx_msdu_end_first_msdu_get)(uint8_t *buf);
1191 uint8_t (*hal_rx_msdu_end_da_is_valid_get)(uint8_t *buf);
1192 uint8_t (*hal_rx_msdu_end_last_msdu_get)(uint8_t *buf);
1193 bool (*hal_rx_get_mpdu_mac_ad4_valid)(uint8_t *buf);
1194 uint32_t (*hal_rx_mpdu_start_sw_peer_id_get)(uint8_t *buf);
1195 uint32_t (*hal_rx_tlv_peer_meta_data_get)(uint8_t *buf);
1196 uint32_t (*hal_rx_mpdu_get_to_ds)(uint8_t *buf);
1197 uint32_t (*hal_rx_mpdu_get_fr_ds)(uint8_t *buf);
1198 uint8_t (*hal_rx_get_mpdu_frame_control_valid)(uint8_t *buf);
1199 QDF_STATUS
1200 (*hal_rx_mpdu_get_addr1)(uint8_t *buf, uint8_t *mac_addr);
1201 QDF_STATUS
1202 (*hal_rx_mpdu_get_addr2)(uint8_t *buf, uint8_t *mac_addr);
1203 QDF_STATUS
1204 (*hal_rx_mpdu_get_addr3)(uint8_t *buf, uint8_t *mac_addr);
1205 QDF_STATUS
1206 (*hal_rx_mpdu_get_addr4)(uint8_t *buf, uint8_t *mac_addr);
1207 uint8_t (*hal_rx_get_mpdu_sequence_control_valid)(uint8_t *buf);
1208 bool (*hal_rx_is_unicast)(uint8_t *buf);
1209 uint32_t (*hal_rx_tid_get)(hal_soc_handle_t hal_soc_hdl, uint8_t *buf);
1210 uint32_t (*hal_rx_hw_desc_get_ppduid_get)(void *rx_tlv_hdr,
1211 void *rxdma_dst_ring_desc);
1212 uint32_t (*hal_rx_mpdu_start_mpdu_qos_control_valid_get)(uint8_t *buf);
1213 uint32_t (*hal_rx_msdu_end_sa_sw_peer_id_get)(uint8_t *buf);
1214 void * (*hal_rx_msdu0_buffer_addr_lsb)(void *link_desc_addr);
1215 void * (*hal_rx_msdu_desc_info_ptr_get)(void *msdu0);
1216 void * (*hal_ent_mpdu_desc_info)(void *hw_addr);
1217 void * (*hal_dst_mpdu_desc_info)(void *hw_addr);
1218 uint8_t (*hal_rx_get_fc_valid)(uint8_t *buf);
1219 uint8_t (*hal_rx_get_to_ds_flag)(uint8_t *buf);
1220 uint8_t (*hal_rx_get_mac_addr2_valid)(uint8_t *buf);
1221 uint8_t (*hal_rx_get_filter_category)(uint8_t *buf);
1222 uint32_t (*hal_rx_get_ppdu_id)(uint8_t *buf);
1223 void (*hal_reo_config)(struct hal_soc *soc,
1224 uint32_t reg_val,
1225 struct hal_reo_params *reo_params);
1226 uint32_t (*hal_rx_msdu_flow_idx_get)(uint8_t *buf);
1227 bool (*hal_rx_msdu_flow_idx_invalid)(uint8_t *buf);
1228 bool (*hal_rx_msdu_flow_idx_timeout)(uint8_t *buf);
1229 uint32_t (*hal_rx_msdu_fse_metadata_get)(uint8_t *buf);
1230 bool (*hal_rx_msdu_cce_match_get)(uint8_t *buf);
1231 uint16_t (*hal_rx_msdu_cce_metadata_get)(uint8_t *buf);
1232 void
1233 (*hal_rx_msdu_get_flow_params)(
1234 uint8_t *buf,
1235 bool *flow_invalid,
1236 bool *flow_timeout,
1237 uint32_t *flow_index);
1238 uint16_t (*hal_rx_tlv_get_tcp_chksum)(uint8_t *buf);
1239 uint16_t (*hal_rx_get_rx_sequence)(uint8_t *buf);
1240 void (*hal_rx_get_bb_info)(void *rx_tlv, void *ppdu_info_handle);
1241 void (*hal_rx_get_rtt_info)(void *rx_tlv, void *ppdu_info_handle);
1242 void (*hal_rx_msdu_packet_metadata_get)(uint8_t *buf,
1243 void *msdu_pkt_metadata);
1244 uint16_t (*hal_rx_get_fisa_cumulative_l4_checksum)(uint8_t *buf);
1245 uint16_t (*hal_rx_get_fisa_cumulative_ip_length)(uint8_t *buf);
1246 bool (*hal_rx_get_udp_proto)(uint8_t *buf);
1247 bool (*hal_rx_get_fisa_flow_agg_continuation)(uint8_t *buf);
1248 uint8_t (*hal_rx_get_fisa_flow_agg_count)(uint8_t *buf);
1249 bool (*hal_rx_get_fisa_timeout)(uint8_t *buf);
1250 uint8_t (*hal_rx_mpdu_start_tlv_tag_valid)(void *rx_tlv_hdr);
1251 void (*hal_rx_sw_mon_desc_info_get)(hal_ring_desc_t rxdma_dst_ring_desc,
1252 hal_rx_mon_desc_info_t mon_desc_info);
1253 uint8_t (*hal_rx_wbm_err_msdu_continuation_get)(void *ring_desc);
1254 uint32_t (*hal_rx_msdu_end_offset_get)(void);
1255 uint32_t (*hal_rx_attn_offset_get)(void);
1256 uint32_t (*hal_rx_msdu_start_offset_get)(void);
1257 uint32_t (*hal_rx_mpdu_start_offset_get)(void);
1258 uint32_t (*hal_rx_mpdu_end_offset_get)(void);
1259 uint32_t (*hal_rx_pkt_tlv_offset_get)(void);
1260 uint32_t (*hal_rx_msdu_end_wmask_get)(void);
1261 uint32_t (*hal_rx_mpdu_start_wmask_get)(void);
1262 void * (*hal_rx_flow_setup_fse)(uint8_t *rx_fst,
1263 uint32_t table_offset,
1264 uint8_t *rx_flow);
1265 void * (*hal_rx_flow_get_tuple_info)(uint8_t *rx_fst,
1266 uint32_t hal_hash,
1267 uint8_t *tuple_info);
1268 QDF_STATUS (*hal_rx_flow_delete_entry)(uint8_t *fst,
1269 void *fse);
1270 uint32_t (*hal_rx_fst_get_fse_size)(void);
1271 void (*hal_compute_reo_remap_ix2_ix3)(uint32_t *ring,
1272 uint32_t num_rings,
1273 uint32_t *remap1,
1274 uint32_t *remap2);
1275 void (*hal_compute_reo_remap_ix0)(uint32_t *remap0);
1276 uint32_t (*hal_rx_flow_setup_cmem_fse)(
1277 struct hal_soc *soc, uint32_t cmem_ba,
1278 uint32_t table_offset, uint8_t *rx_flow);
1279 uint32_t (*hal_rx_flow_get_cmem_fse_ts)(struct hal_soc *soc,
1280 uint32_t fse_offset);
1281 void (*hal_rx_flow_get_cmem_fse)(struct hal_soc *soc,
1282 uint32_t fse_offset,
1283 uint32_t *fse, qdf_size_t len);
1284
1285 void (*hal_cmem_write)(hal_soc_handle_t hal_soc_hdl, uint32_t offset,
1286 uint32_t value);
1287
1288 void (*hal_rx_msdu_get_reo_destination_indication)(uint8_t *buf,
1289 uint32_t *reo_destination_indication);
1290 uint8_t (*hal_tx_get_num_tcl_banks)(void);
1291 uint32_t (*hal_get_reo_qdesc_size)(uint32_t ba_window_size, int tid);
1292 uint16_t (*hal_get_rx_max_ba_window)(int tid);
1293
1294 void (*hal_set_link_desc_addr)(void *desc, uint32_t cookie,
1295 qdf_dma_addr_t link_desc_paddr,
1296 uint8_t bm_id);
1297 void (*hal_tx_init_data_ring)(hal_soc_handle_t hal_soc_hdl,
1298 hal_ring_handle_t hal_ring_hdl);
1299 void* (*hal_rx_msdu_ext_desc_info_get_ptr)(void *msdu_details_ptr);
1300 void (*hal_get_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl,
1301 uint8_t ac, uint32_t *value);
1302 void (*hal_set_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl,
1303 uint8_t ac, uint32_t value);
1304 uint32_t (*hal_get_reo_reg_base_offset)(void);
1305 void (*hal_rx_get_tlv_size)(uint16_t *rx_pkt_tlv_size,
1306 uint16_t *rx_mon_pkt_tlv_size);
1307 uint32_t (*hal_rx_msdu_is_wlan_mcast)(qdf_nbuf_t nbuf);
1308 uint32_t (*hal_rx_tlv_decap_format_get)(void *hw_desc_addr);
1309 void (*hal_rx_dump_pkt_tlvs)(hal_soc_handle_t hal_soc_hdl,
1310 uint8_t *buf, uint8_t dbg_level);
1311 int (*hal_rx_tlv_get_offload_info)(uint8_t *rx_tlv,
1312 struct hal_offload_info *offload_info);
1313 uint16_t (*hal_rx_tlv_phy_ppdu_id_get)(uint8_t *buf);
1314 uint32_t (*hal_rx_tlv_msdu_done_get)(uint8_t *buf);
1315 uint32_t (*hal_rx_tlv_msdu_len_get)(uint8_t *buf);
1316 uint16_t (*hal_rx_get_frame_ctrl_field)(uint8_t *buf);
1317 int (*hal_rx_get_proto_params)(uint8_t *buf, void *fisa_params);
1318 int (*hal_rx_get_l3_l4_offsets)(uint8_t *buf, uint32_t *l3_hdr_offset,
1319 uint32_t *l4_hdr_offset);
1320 uint32_t (*hal_rx_tlv_mic_err_get)(uint8_t *buf);
1321 uint32_t (*hal_rx_tlv_get_pkt_type)(uint8_t *buf);
1322 void (*hal_rx_tlv_get_pn_num)(uint8_t *buf, uint64_t *pn_num);
1323 void (*hal_rx_reo_prev_pn_get)(void *ring_desc, uint64_t *prev_pn);
1324 uint8_t * (*hal_rx_pkt_hdr_get)(uint8_t *buf);
1325 uint32_t (*hal_rx_msdu_reo_dst_ind_get)(hal_soc_handle_t hal_soc_hdl,
1326 void *msdu_link_desc);
1327 void (*hal_msdu_desc_info_set)(hal_soc_handle_t hal_soc_hdl,
1328 void *msdu_desc_info, uint32_t dst_ind,
1329 uint32_t nbuf_len);
1330 void (*hal_mpdu_desc_info_set)(hal_soc_handle_t hal_soc_hdl,
1331 void *ent_desc,
1332 void *mpdu_desc_info,
1333 uint32_t seq_no);
1334 #ifdef DP_UMAC_HW_RESET_SUPPORT
1335 void (*hal_unregister_reo_send_cmd)(struct hal_soc *hal_soc);
1336 void (*hal_register_reo_send_cmd)(struct hal_soc *hal_soc);
1337 void (*hal_reset_rx_reo_tid_q)(struct hal_soc *hal_soc,
1338 void *hw_qdesc_vaddr, uint32_t size);
1339 #endif
1340 uint32_t (*hal_rx_tlv_sgi_get)(uint8_t *buf);
1341 uint32_t (*hal_rx_tlv_get_freq)(uint8_t *buf);
1342 uint8_t (*hal_rx_msdu_get_keyid)(uint8_t *buf);
1343 uint32_t (*hal_rx_tlv_rate_mcs_get)(uint8_t *buf);
1344 uint32_t (*hal_rx_tlv_decrypt_err_get)(uint8_t *buf);
1345 uint32_t (*hal_rx_tlv_first_mpdu_get)(uint8_t *buf);
1346 uint32_t (*hal_rx_tlv_bw_get)(uint8_t *buf);
1347 uint32_t (*hal_rx_tlv_get_is_decrypted)(uint8_t *buf);
1348
1349 uint32_t (*hal_rx_wbm_err_src_get)(hal_ring_desc_t ring_desc);
1350 uint8_t (*hal_rx_ret_buf_manager_get)(hal_ring_desc_t ring_desc);
1351 void (*hal_rx_msdu_link_desc_set)(hal_soc_handle_t hal_soc_hdl,
1352 void *src_srng_desc,
1353 hal_buff_addrinfo_t buf_addr_info,
1354 uint8_t bm_action);
1355
1356 void (*hal_rx_buf_cookie_rbm_get)(uint32_t *buf_addr_info_hdl,
1357 hal_buf_info_t buf_info_hdl);
1358 void (*hal_rx_reo_buf_paddr_get)(hal_ring_desc_t rx_desc,
1359 struct hal_buf_info *buf_info);
1360 void (*hal_rxdma_buff_addr_info_set)(void *rxdma_entry,
1361 qdf_dma_addr_t paddr,
1362 uint32_t cookie, uint8_t manager);
1363 uint32_t (*hal_rx_msdu_flags_get)(rx_msdu_desc_info_t msdu_desc_info_hdl);
1364 uint32_t (*hal_rx_get_reo_error_code)(hal_ring_desc_t rx_desc);
1365 void (*hal_rx_tlv_csum_err_get)(uint8_t *rx_tlv_hdr,
1366 uint32_t *ip_csum_err,
1367 uint32_t *tcp_udp_csum_err);
1368 void (*hal_rx_mpdu_desc_info_get)(void *desc_addr,
1369 void *mpdu_desc_info_hdl);
1370 uint8_t (*hal_rx_err_status_get)(hal_ring_desc_t rx_desc);
1371 uint8_t (*hal_rx_reo_buf_type_get)(hal_ring_desc_t rx_desc);
1372 bool (*hal_rx_mpdu_info_ampdu_flag_get)(uint8_t *buf);
1373 uint32_t (*hal_rx_tlv_mpdu_len_err_get)(void *hw_desc_addr);
1374 uint32_t (*hal_rx_tlv_mpdu_fcs_err_get)(void *hw_desc_addr);
1375 void (*hal_rx_tlv_get_pkt_capture_flags)(uint8_t *rx_tlv_hdr,
1376 struct hal_rx_pkt_capture_flags *flags);
1377 uint8_t *(*hal_rx_desc_get_80211_hdr)(void *hw_desc_addr);
1378 uint32_t (*hal_rx_hw_desc_mpdu_user_id)(void *hw_desc_addr);
1379 void (*hal_rx_priv_info_set_in_tlv)(uint8_t *buf,
1380 uint8_t *priv_data,
1381 uint32_t len);
1382 void (*hal_rx_priv_info_get_from_tlv)(uint8_t *buf,
1383 uint8_t *priv_data,
1384 uint32_t len);
1385 void (*hal_rx_tlv_msdu_len_set)(uint8_t *buf, uint32_t len);
1386 void (*hal_rx_tlv_populate_mpdu_desc_info)(uint8_t *buf,
1387 void *mpdu_desc_info_hdl);
1388 uint8_t *(*hal_get_reo_ent_desc_qdesc_addr)(uint8_t *desc);
1389 uint64_t (*hal_rx_get_qdesc_addr)(uint8_t *dst_ring_desc,
1390 uint8_t *buf);
1391 uint8_t (*hal_rx_get_phy_ppdu_id_size)(void);
1392 void (*hal_set_reo_ent_desc_reo_dest_ind)(uint8_t *desc,
1393 uint32_t dst_ind);
1394 QDF_STATUS
1395 (*hal_rx_reo_ent_get_src_link_id)(hal_rxdma_desc_t rx_desc,
1396 uint8_t *src_link_id);
1397
1398 /* REO CMD and STATUS */
1399 int (*hal_reo_send_cmd)(hal_soc_handle_t hal_soc_hdl,
1400 hal_ring_handle_t hal_ring_hdl,
1401 enum hal_reo_cmd_type cmd,
1402 void *params);
1403 QDF_STATUS (*hal_reo_status_update)(hal_soc_handle_t hal_soc_hdl,
1404 hal_ring_desc_t reo_desc,
1405 void *st_handle,
1406 uint32_t tlv, int *num_ref);
1407 uint8_t (*hal_get_tlv_hdr_size)(void);
1408 uint8_t (*hal_get_idle_link_bm_id)(uint8_t chip_id);
1409
1410 bool (*hal_txmon_is_mon_buf_addr_tlv)(void *tx_tlv_hdr);
1411 void (*hal_txmon_populate_packet_info)(void *tx_tlv_hdr,
1412 void *pkt_info);
1413 /* TX MONITOR */
1414 #ifdef WLAN_PKT_CAPTURE_TX_2_0
1415 uint32_t (*hal_txmon_status_parse_tlv)(void *data_ppdu_info,
1416 void *prot_ppdu_info,
1417 void *data_status_info,
1418 void *prot_status_info,
1419 void *tx_tlv_hdr,
1420 qdf_frag_t status_frag);
1421 uint32_t (*hal_txmon_status_get_num_users)(void *tx_tlv_hdr,
1422 uint8_t *num_users);
1423 void (*hal_txmon_get_word_mask)(void *wmask);
1424 #endif /* WLAN_PKT_CAPTURE_TX_2_0 */
1425 QDF_STATUS (*hal_reo_shared_qaddr_setup)(hal_soc_handle_t hal_soc_hdl,
1426 struct reo_queue_ref_table
1427 *reo_qref);
1428 void (*hal_reo_shared_qaddr_init)(hal_soc_handle_t hal_soc_hdl,
1429 int qref_reset);
1430 void (*hal_reo_shared_qaddr_detach)(hal_soc_handle_t hal_soc_hdl);
1431 void (*hal_reo_shared_qaddr_write)(hal_soc_handle_t hal_soc_hdl,
1432 uint16_t peer_id,
1433 int tid,
1434 qdf_dma_addr_t hw_qdesc_paddr);
1435 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
1436 uint8_t (*hal_get_first_wow_wakeup_packet)(uint8_t *buf);
1437 #endif
1438 void (*hal_reo_shared_qaddr_cache_clear)(hal_soc_handle_t hal_soc_hdl);
1439 uint32_t (*hal_rx_tlv_l3_type_get)(uint8_t *buf);
1440 void (*hal_tx_vdev_mismatch_routing_set)(hal_soc_handle_t hal_soc_hdl,
1441 enum hal_tx_vdev_mismatch_notify config);
1442 void (*hal_tx_mcast_mlo_reinject_routing_set)(
1443 hal_soc_handle_t hal_soc_hdl,
1444 enum hal_tx_mcast_mlo_reinject_notify config);
1445 void (*hal_cookie_conversion_reg_cfg_be)(hal_soc_handle_t hal_soc_hdl,
1446 struct hal_hw_cc_config
1447 *cc_cfg);
1448 void (*hal_tx_populate_bank_register)(hal_soc_handle_t hal_soc_hdl,
1449 union hal_tx_bank_config *config,
1450 uint8_t bank_id);
1451 void (*hal_tx_vdev_mcast_ctrl_set)(hal_soc_handle_t hal_soc_hdl,
1452 uint8_t vdev_id,
1453 uint8_t mcast_ctrl_val);
1454 void (*hal_get_tsf_time)(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id,
1455 uint32_t mac_id, uint64_t *tsf,
1456 uint64_t *tsf_sync_soc_time);
1457 void (*hal_get_tsf2_scratch_reg)(hal_soc_handle_t hal_soc_hdl,
1458 uint8_t mac_id, uint64_t *value);
1459 void (*hal_get_tqm_scratch_reg)(hal_soc_handle_t hal_soc_hdl,
1460 uint64_t *value);
1461 #ifdef FEATURE_DIRECT_LINK
1462 QDF_STATUS (*hal_srng_set_msi_config)(hal_ring_handle_t ring_hdl,
1463 void *ring_params);
1464 #endif
1465 void (*hal_tx_ring_halt_set)(hal_soc_handle_t hal_soc_hdl);
1466 void (*hal_tx_ring_halt_reset)(hal_soc_handle_t hal_soc_hdl);
1467 bool (*hal_tx_ring_halt_poll)(hal_soc_handle_t hal_soc_hdl);
1468 uint32_t (*hal_tx_get_num_ppe_vp_search_idx_tbl_entries)(
1469 hal_soc_handle_t hal_soc_hdl);
1470 uint32_t (*hal_tx_ring_halt_get)(hal_soc_handle_t hal_soc_hdl);
1471 bool (*hal_rx_en_mcast_fp_data_filter)(void);
1472 void (*hal_rx_parse_eht_sig_hdr)(struct hal_soc *hal_soc,
1473 uint8_t *tlv,
1474 void *ppdu_info_handle);
1475 };
1476
1477 /**
1478 * struct hal_soc_stats - Hal layer stats
1479 * @reg_write_fail: number of failed register writes
1480 * @wstats: delayed register write stats
1481 * @shadow_reg_write_fail: shadow reg write failure stats
1482 * @shadow_reg_write_succ: shadow reg write success stats
1483 *
1484 * This structure holds all the statistics at HAL layer.
1485 */
1486 struct hal_soc_stats {
1487 uint32_t reg_write_fail;
1488 #if defined(FEATURE_HAL_DELAYED_REG_WRITE)
1489 struct hal_reg_write_soc_stats wstats;
1490 #endif
1491 #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE
1492 uint32_t shadow_reg_write_fail;
1493 uint32_t shadow_reg_write_succ;
1494 #endif
1495 };
1496
1497 #ifdef ENABLE_HAL_REG_WR_HISTORY
1498 /* The history size should always be a power of 2 */
1499 #define HAL_REG_WRITE_HIST_SIZE 8
1500
1501 /**
1502 * struct hal_reg_write_fail_entry - Record of
1503 * register write which failed.
1504 * @timestamp: timestamp of reg write failure
1505 * @reg_offset: offset of register where the write failed
1506 * @write_val: the value which was to be written
1507 * @read_val: the value read back from the register after write
1508 */
1509 struct hal_reg_write_fail_entry {
1510 uint64_t timestamp;
1511 uint32_t reg_offset;
1512 uint32_t write_val;
1513 uint32_t read_val;
1514 };
1515
1516 /**
1517 * struct hal_reg_write_fail_history - Hal layer history
1518 * of all the register write failures.
1519 * @index: index to add the new record
1520 * @record: array of all the records in history
1521 *
1522 * This structure holds the history of register write
1523 * failures at HAL layer.
1524 */
1525 struct hal_reg_write_fail_history {
1526 qdf_atomic_t index;
1527 struct hal_reg_write_fail_entry record[HAL_REG_WRITE_HIST_SIZE];
1528 };
1529 #endif
1530
1531 /**
1532 * union hal_shadow_reg_cfg - Shadow register config
1533 * @addr: Place holder where shadow address is saved
1534 * @v2: shadow config v2 format
1535 * @v3: shadow config v3 format
1536 */
1537 union hal_shadow_reg_cfg {
1538 uint32_t addr;
1539 struct pld_shadow_reg_v2_cfg v2;
1540 #ifdef CONFIG_SHADOW_V3
1541 struct pld_shadow_reg_v3_cfg v3;
1542 #endif
1543 };
1544
1545 #ifdef HAL_RECORD_SUSPEND_WRITE
1546 #define HAL_SUSPEND_WRITE_HISTORY_MAX 256
1547
1548 struct hal_suspend_write_record {
1549 uint64_t ts;
1550 uint8_t ring_id;
1551 uit32_t value;
1552 uint32_t direct_wcount;
1553 };
1554
1555 struct hal_suspend_write_history {
1556 qdf_atomic_t index;
1557 struct hal_suspend_write_record record[HAL_SUSPEND_WRITE_HISTORY_MAX];
1558
1559 };
1560 #endif
1561
1562 /**
1563 * struct hal_soc - HAL context to be used to access SRNG APIs
1564 * (currently used by data path and
1565 * transport (CE) modules)
1566 * @hif_handle: HIF handle to access HW registers
1567 * @qdf_dev: QDF device handle
1568 * @dev_base_addr: Device base address
1569 * @dev_base_addr_ce: Device base address for ce - qca5018 target
1570 * @dev_base_addr_cmem: Device base address for CMEM
1571 * @dev_base_addr_pmm: Device base address for PMM
1572 * @srng_list: HAL internal state for all SRNG rings
1573 * @shadow_rdptr_mem_vaddr: Remote pointer memory for HW/FW updates (virtual)
1574 * @shadow_rdptr_mem_paddr: Remote pointer memory for HW/FW updates (physical)
1575 * @shadow_wrptr_mem_vaddr: Shared memory for ring pointer updates from host
1576 * to FW (virtual)
1577 * @shadow_wrptr_mem_paddr: Shared memory for ring pointer updates from host
1578 * to FW (physical)
1579 * @reo_res_bitmap: REO blocking resource index
1580 * @index:
1581 * @target_type:
1582 * @version:
1583 * @shadow_config: shadow register configuration
1584 * @num_shadow_registers_configured:
1585 * @use_register_windowing:
1586 * @register_window:
1587 * @register_access_lock:
1588 * @static_window_map: Static window map configuration for multiple window write
1589 * @hw_srng_table: srng table
1590 * @hal_hw_reg_offset:
1591 * @ops: TXRX operations
1592 * @init_phase: Indicate srngs initialization
1593 * @stats: Hal level stats
1594 * @reg_wr_fail_hist: write failure history
1595 * @reg_write_queue: queue(array) to hold register writes
1596 * @reg_write_work: delayed work to be queued into workqueue
1597 * @reg_write_wq: workqueue for delayed register writes
1598 * @write_idx: write index used by caller to enqueue delayed work
1599 * @read_idx: read index used by worker thread to dequeue/write registers
1600 * @active_work_cnt:
1601 * @list_shadow_reg_config: array of generic regs mapped to
1602 * shadow regs
1603 * @num_generic_shadow_regs_configured: number of generic regs
1604 * mapped to shadow regs
1605 * @dmac_cmn_src_rxbuf_ring: flag to indicate cmn dmac rings in beryllium
1606 * @reo_qref: Reo queue ref table items
1607 */
1608 struct hal_soc {
1609 struct hif_opaque_softc *hif_handle;
1610 qdf_device_t qdf_dev;
1611 void *dev_base_addr;
1612 void *dev_base_addr_ce;
1613 void *dev_base_addr_cmem;
1614 void *dev_base_addr_pmm;
1615 struct hal_srng srng_list[HAL_SRNG_ID_MAX];
1616
1617 uint32_t *shadow_rdptr_mem_vaddr;
1618 qdf_dma_addr_t shadow_rdptr_mem_paddr;
1619
1620 uint32_t *shadow_wrptr_mem_vaddr;
1621 qdf_dma_addr_t shadow_wrptr_mem_paddr;
1622
1623 uint8_t reo_res_bitmap;
1624 uint8_t index;
1625 uint32_t target_type;
1626 uint32_t version;
1627
1628 union hal_shadow_reg_cfg shadow_config[MAX_SHADOW_REGISTERS];
1629 int num_shadow_registers_configured;
1630 bool use_register_windowing;
1631 uint32_t register_window;
1632 qdf_spinlock_t register_access_lock;
1633
1634 bool static_window_map;
1635
1636 struct hal_hw_srng_config *hw_srng_table;
1637 int32_t hal_hw_reg_offset[SRNG_REGISTER_MAX];
1638 struct hal_hw_txrx_ops *ops;
1639
1640 bool init_phase;
1641 struct hal_soc_stats stats;
1642 #ifdef ENABLE_HAL_REG_WR_HISTORY
1643 struct hal_reg_write_fail_history *reg_wr_fail_hist;
1644 #endif
1645 #ifdef FEATURE_HAL_DELAYED_REG_WRITE
1646 struct hal_reg_write_q_elem *reg_write_queue;
1647 qdf_work_t reg_write_work;
1648 qdf_workqueue_t *reg_write_wq;
1649 qdf_atomic_t write_idx;
1650 uint32_t read_idx;
1651 #endif /*FEATURE_HAL_DELAYED_REG_WRITE */
1652 qdf_atomic_t active_work_cnt;
1653 #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE
1654 struct shadow_reg_config
1655 list_shadow_reg_config[MAX_GENERIC_SHADOW_REG];
1656 int num_generic_shadow_regs_configured;
1657 #endif
1658 bool dmac_cmn_src_rxbuf_ring;
1659 struct reo_queue_ref_table reo_qref;
1660 };
1661
1662 #if defined(FEATURE_HAL_DELAYED_REG_WRITE)
1663 /**
1664 * hal_delayed_reg_write() - delayed register write
1665 * @hal_soc: HAL soc handle
1666 * @srng: hal srng
1667 * @addr: iomem address
1668 * @value: value to be written
1669 *
1670 * Return: none
1671 */
1672 void hal_delayed_reg_write(struct hal_soc *hal_soc,
1673 struct hal_srng *srng,
1674 void __iomem *addr,
1675 uint32_t value);
1676 #endif
1677
1678 void hal_qca6750_attach(struct hal_soc *hal_soc);
1679 void hal_qca6490_attach(struct hal_soc *hal_soc);
1680 void hal_qca6390_attach(struct hal_soc *hal_soc);
1681 void hal_qca6290_attach(struct hal_soc *hal_soc);
1682 void hal_qca8074_attach(struct hal_soc *hal_soc);
1683
1684 /**
1685 * hal_kiwi_attach() - Attach kiwi target specific hal_soc ops,
1686 * offset and srng table
1687 * @hal_soc: HAL soc
1688 */
1689 void hal_kiwi_attach(struct hal_soc *hal_soc);
1690
1691 void hal_qcn9224v2_attach(struct hal_soc *hal_soc);
1692 void hal_wcn6450_attach(struct hal_soc *hal_soc);
1693
1694 /**
1695 * hal_soc_to_hal_soc_handle() - API to convert hal_soc to opaque
1696 * hal_soc_handle_t type
1697 * @hal_soc: hal_soc type
1698 *
1699 * Return: hal_soc_handle_t type
1700 */
1701 static inline
hal_soc_to_hal_soc_handle(struct hal_soc * hal_soc)1702 hal_soc_handle_t hal_soc_to_hal_soc_handle(struct hal_soc *hal_soc)
1703 {
1704 return (hal_soc_handle_t)hal_soc;
1705 }
1706
1707 /**
1708 * hal_srng_to_hal_ring_handle() - API to convert hal_srng to opaque
1709 * hal_ring handle_t type
1710 * @hal_srng: hal_srng type
1711 *
1712 * Return: hal_ring_handle_t type
1713 */
1714 static inline
hal_srng_to_hal_ring_handle(struct hal_srng * hal_srng)1715 hal_ring_handle_t hal_srng_to_hal_ring_handle(struct hal_srng *hal_srng)
1716 {
1717 return (hal_ring_handle_t)hal_srng;
1718 }
1719
1720 /**
1721 * hal_ring_handle_to_hal_srng() - API to convert hal_ring_handle_t to hal_srng
1722 * @hal_ring: hal_ring_handle_t type
1723 *
1724 * Return: hal_srng pointer type
1725 */
1726 static inline
hal_ring_handle_to_hal_srng(hal_ring_handle_t hal_ring)1727 struct hal_srng *hal_ring_handle_to_hal_srng(hal_ring_handle_t hal_ring)
1728 {
1729 return (struct hal_srng *)hal_ring;
1730 }
1731
1732 /* Size of REO queue reference table in Host
1733 * 2k peers * 17 tids * 8bytes(rx_reo_queue_reference)
1734 * = 278528 bytes
1735 */
1736 #define REO_QUEUE_REF_NON_ML_TABLE_SIZE 278528
1737 /* Calculated based on 512 MLO peers */
1738 #define REO_QUEUE_REF_ML_TABLE_SIZE 69632
1739 #define HAL_ML_PEER_ID_START 0x2000
1740 #define HAL_PEER_ID_IS_MLO(peer_id) ((peer_id) & HAL_ML_PEER_ID_START)
1741
1742 /*
1743 * REO2PPE destination indication
1744 */
1745 #define REO2PPE_DST_IND 6
1746 #define REO2PPE_DST_RING 11
1747 #define REO2PPE_RULE_FAIL_FB 0x2000
1748
1749 /**
1750 * enum hal_pkt_type - Type of packet type reported by HW
1751 * @HAL_DOT11A: 802.11a PPDU type
1752 * @HAL_DOT11B: 802.11b PPDU type
1753 * @HAL_DOT11N_MM: 802.11n Mixed Mode PPDU type
1754 * @HAL_DOT11AC: 802.11ac PPDU type
1755 * @HAL_DOT11AX: 802.11ax PPDU type
1756 * @HAL_DOT11BA: 802.11ba (WUR) PPDU type
1757 * @HAL_DOT11BE: 802.11be PPDU type
1758 * @HAL_DOT11AZ: 802.11az (ranging) PPDU type
1759 * @HAL_DOT11N_GF: 802.11n Green Field PPDU type
1760 * @HAL_DOT11_MAX: Maximum enumeration
1761 *
1762 * Enum indicating the packet type reported by HW in rx_pkt_tlvs (RX data)
1763 * or WBM2SW ring entry's descriptor (TX data completion)
1764 */
1765 enum hal_pkt_type {
1766 HAL_DOT11A = 0,
1767 HAL_DOT11B = 1,
1768 HAL_DOT11N_MM = 2,
1769 HAL_DOT11AC = 3,
1770 HAL_DOT11AX = 4,
1771 HAL_DOT11BA = 5,
1772 HAL_DOT11BE = 6,
1773 HAL_DOT11AZ = 7,
1774 HAL_DOT11N_GF = 8,
1775 HAL_DOT11_MAX,
1776 };
1777
1778 #endif /* _HAL_INTERNAL_H_ */
1779