1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_BE_API_H_ 21 #define _HAL_BE_API_H_ 22 23 #include "hal_hw_headers.h" 24 #include "hal_rx.h" 25 26 #define HAL_RX_MSDU_EXT_DESC_INFO_GET(msdu_details_ptr) \ 27 ((struct rx_msdu_ext_desc_info *) \ 28 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 29 RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET)) 30 31 /** 32 * hal_reo_setup_generic_be - Initialize HW REO block 33 * 34 * @soc: Opaque HAL SOC handle 35 * @reoparams: parameters needed by HAL for REO config 36 * @qref_reset: reset qref 37 */ 38 void hal_reo_setup_generic_be(struct hal_soc *soc, 39 void *reoparams, int qref_reset); 40 41 /** 42 * hal_rx_msdu_ext_desc_info_get_ptr_be() - Get the msdu extension 43 * descriptor pointer. 44 * @msdu_details_ptr: msdu details 45 * 46 * Return: msdu exntension descriptor pointer. 47 */ 48 void *hal_rx_msdu_ext_desc_info_get_ptr_be(void *msdu_details_ptr); 49 50 /** 51 * hal_set_link_desc_addr_be - Setup link descriptor in a buffer_addr_info 52 * HW structure 53 * 54 * @desc: Descriptor entry (from WBM_IDLE_LINK ring) 55 * @cookie: SW cookie for the buffer/descriptor 56 * @link_desc_paddr: Physical address of link descriptor entry 57 * @bm_id: idle link BM id 58 * 59 */ 60 void hal_set_link_desc_addr_be(void *desc, uint32_t cookie, 61 qdf_dma_addr_t link_desc_paddr, 62 uint8_t bm_id); 63 64 /** 65 * hal_hw_txrx_default_ops_attach_be() - Add default ops for BE chips 66 * @soc: hal_soc handle 67 * 68 * Return: None 69 */ 70 void hal_hw_txrx_default_ops_attach_be(struct hal_soc *soc); 71 72 uint32_t hal_tx_comp_get_buffer_source_generic_be(void *hal_desc); 73 74 /** 75 * hal_rx_ret_buf_manager_get_be() - Get return buffer manager from ring desc 76 * @ring_desc: ring descriptor 77 * 78 * Return: rbm 79 */ 80 uint8_t hal_rx_ret_buf_manager_get_be(hal_ring_desc_t ring_desc); 81 82 /** 83 * hal_rx_wbm_err_info_get_generic_be() - Retrieves WBM error code and reason and 84 * save it to hal_wbm_err_desc_info structure passed by caller 85 * @wbm_desc: wbm ring descriptor 86 * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter. 87 * 88 * Return: void 89 */ 90 void hal_rx_wbm_err_info_get_generic_be(void *wbm_desc, void *wbm_er_info1); 91 92 /** 93 * hal_reo_qdesc_setup_be() - Setup HW REO queue descriptor 94 * @hal_soc_hdl: Opaque HAL SOC handle 95 * @tid: TID 96 * @ba_window_size: BlockAck window size 97 * @start_seq: Starting sequence number 98 * @hw_qdesc_vaddr: Virtual address of REO queue descriptor memory 99 * @hw_qdesc_paddr: Physical address of REO queue descriptor memory 100 * @pn_type: PN type (one of the types defined in 'enum hal_pn_type') 101 * @vdev_stats_id: vdev_stats_id to be programmed in REO Queue Descriptor 102 */ 103 void hal_reo_qdesc_setup_be(hal_soc_handle_t hal_soc_hdl, 104 int tid, uint32_t ba_window_size, 105 uint32_t start_seq, void *hw_qdesc_vaddr, 106 qdf_dma_addr_t hw_qdesc_paddr, 107 int pn_type, uint8_t vdev_stats_id); 108 109 /** 110 * hal_cookie_conversion_reg_cfg_be() - set cookie conversion relevant register 111 * for REO/WBM 112 * @hal_soc_hdl: Handle to HAL SoC structure 113 * @cc_cfg: structure pointer for HW cookie conversion configuration 114 * 115 * Return: None 116 */ 117 void hal_cookie_conversion_reg_cfg_be(hal_soc_handle_t hal_soc_hdl, 118 struct hal_hw_cc_config *cc_cfg); 119 120 /** 121 * hal_reo_ix_remap_value_get_be() - Calculate reo remap register value from 122 * ring_id_mask which is used for hash based 123 * reo distribution 124 * @hal_soc_hdl: Handle to HAL SoC structure 125 * @rx_ring_mask: mask value indicating the rx rings 0th bit set indicate 126 * REO2SW1 is included in hash distribution 127 * 128 * Return: REO remap value 129 */ 130 uint32_t 131 hal_reo_ix_remap_value_get_be(hal_soc_handle_t hal_soc_hdl, 132 uint8_t rx_ring_mask); 133 134 /** 135 * hal_reo_ring_remap_value_get_be() - return REO remap value 136 * @rx_ring_id: REO2SW ring mask 137 * 138 * Return: REO remap value 139 */ 140 uint8_t 141 hal_reo_ring_remap_value_get_be(uint8_t rx_ring_id); 142 143 /** 144 * hal_setup_reo_swap() - Set the swap flag for big endian machines 145 * @soc: HAL soc handle 146 * 147 * Return: None 148 */ 149 void hal_setup_reo_swap(struct hal_soc *soc); 150 151 /** 152 * hal_get_idle_link_bm_id_be() - Get idle link BM id from chid_id 153 * @chip_id: mlo chip_id 154 * 155 * Returns: RBM ID 156 */ 157 uint8_t hal_get_idle_link_bm_id_be(uint8_t chip_id); 158 #endif /* _HAL_BE_API_H_ */ 159