1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef _NET_CNSS2_H 8 #define _NET_CNSS2_H 9 10 #include <linux/pci.h> 11 12 #define CNSS_MAX_FILE_NAME 20 13 #define CNSS_MAX_TIMESTAMP_LEN 32 14 #define CNSS_WLFW_MAX_BUILD_ID_LEN 128 15 #define CNSS_MAX_DEV_MEM_NUM 4 16 #define CNSS_CHIP_VER_ANY 0 17 18 #define CNSS_SSR_DRIVER_DUMP_MAX_REGIONS 32 19 20 enum cnss_bus_width_type { 21 CNSS_BUS_WIDTH_NONE, 22 CNSS_BUS_WIDTH_IDLE, 23 CNSS_BUS_WIDTH_LOW, 24 CNSS_BUS_WIDTH_MEDIUM, 25 CNSS_BUS_WIDTH_HIGH, 26 CNSS_BUS_WIDTH_VERY_HIGH, 27 CNSS_BUS_WIDTH_LOW_LATENCY 28 }; 29 30 enum cnss_platform_cap_flag { 31 CNSS_HAS_EXTERNAL_SWREG = 0x01, 32 CNSS_HAS_UART_ACCESS = 0x02, 33 CNSS_HAS_DRV_SUPPORT = 0x04, 34 }; 35 36 struct cnss_platform_cap { 37 u32 cap_flag; 38 }; 39 40 struct cnss_fw_files { 41 char image_file[CNSS_MAX_FILE_NAME]; 42 char board_data[CNSS_MAX_FILE_NAME]; 43 char otp_data[CNSS_MAX_FILE_NAME]; 44 char utf_file[CNSS_MAX_FILE_NAME]; 45 char utf_board_data[CNSS_MAX_FILE_NAME]; 46 char epping_file[CNSS_MAX_FILE_NAME]; 47 char evicted_data[CNSS_MAX_FILE_NAME]; 48 }; 49 50 struct cnss_device_version { 51 u32 family_number; 52 u32 device_number; 53 u32 major_version; 54 u32 minor_version; 55 }; 56 57 struct cnss_dev_mem_info { 58 u64 start; 59 u64 size; 60 }; 61 62 struct cnss_soc_info { 63 void __iomem *va; 64 phys_addr_t pa; 65 uint32_t chip_id; 66 uint32_t chip_family; 67 uint32_t board_id; 68 uint32_t soc_id; 69 uint32_t fw_version; 70 char fw_build_timestamp[CNSS_MAX_TIMESTAMP_LEN + 1]; 71 struct cnss_device_version device_version; 72 struct cnss_dev_mem_info dev_mem_info[CNSS_MAX_DEV_MEM_NUM]; 73 char fw_build_id[CNSS_WLFW_MAX_BUILD_ID_LEN + 1]; 74 }; 75 76 struct cnss_wlan_runtime_ops { 77 int (*runtime_suspend)(struct pci_dev *pdev); 78 int (*runtime_resume)(struct pci_dev *pdev); 79 }; 80 81 enum cnss_driver_status { 82 CNSS_UNINITIALIZED, 83 CNSS_INITIALIZED, 84 CNSS_LOAD_UNLOAD, 85 CNSS_RECOVERY, 86 CNSS_FW_DOWN, 87 CNSS_HANG_EVENT, 88 CNSS_BUS_EVENT, 89 CNSS_SYS_REBOOT, 90 }; 91 92 enum cnss_host_dump_type { 93 CNSS_HOST_WLAN_LOGS = 0, 94 CNSS_HOST_HTC_CREDIT = 1, 95 CNSS_HOST_WMI_TX_CMP = 2, 96 CNSS_HOST_WMI_COMMAND_LOG = 3, 97 CNSS_HOST_WMI_EVENT_LOG = 4, 98 CNSS_HOST_WMI_RX_EVENT = 5, 99 CNSS_HOST_HAL_SOC = 6, 100 CNSS_HOST_GWLAN_LOGGING = 7, 101 CNSS_HOST_WMI_DEBUG_LOG_INFO = 8, 102 CNSS_HOST_HTC_CREDIT_IDX = 9, 103 CNSS_HOST_HTC_CREDIT_LEN = 10, 104 CNSS_HOST_WMI_TX_CMP_IDX = 11, 105 CNSS_HOST_WMI_COMMAND_LOG_IDX = 12, 106 CNSS_HOST_WMI_EVENT_LOG_IDX = 13, 107 CNSS_HOST_WMI_RX_EVENT_IDX = 14, 108 CNSS_HOST_HIF_CE_DESC_HISTORY_BUFF = 15, 109 CNSS_HOST_HANG_EVENT_DATA = 16, 110 CNSS_HOST_CE_DESC_HIST = 17, 111 CNSS_HOST_CE_COUNT_MAX = 18, 112 CNSS_HOST_CE_HISTORY_MAX = 19, 113 CNSS_HOST_ONLY_FOR_CRIT_CE = 20, 114 CNSS_HOST_HIF_EVENT_HISTORY = 21, 115 CNSS_HOST_HIF_EVENT_HIST_MAX = 22, 116 CNSS_HOST_DP_WBM_DESC_REL = 23, 117 CNSS_HOST_DP_WBM_DESC_REL_HANDLE = 24, 118 CNSS_HOST_DP_TCL_CMD = 25, 119 CNSS_HOST_DP_TCL_CMD_HANDLE = 26, 120 CNSS_HOST_DP_TCL_STATUS = 27, 121 CNSS_HOST_DP_TCL_STATUS_HANDLE = 28, 122 CNSS_HOST_DP_REO_REINJ = 29, 123 CNSS_HOST_DP_REO_REINJ_HANDLE = 30, 124 CNSS_HOST_DP_RX_REL = 31, 125 CNSS_HOST_DP_RX_REL_HANDLE = 32, 126 CNSS_HOST_DP_REO_EXP = 33, 127 CNSS_HOST_DP_REO_EXP_HANDLE = 34, 128 CNSS_HOST_DP_REO_CMD = 35, 129 CNSS_HOST_DP_REO_CMD_HANDLE = 36, 130 CNSS_HOST_DP_REO_STATUS = 37, 131 CNSS_HOST_DP_REO_STATUS_HANDLE = 38, 132 CNSS_HOST_DP_TCL_DATA_0 = 39, 133 CNSS_HOST_DP_TCL_DATA_0_HANDLE = 40, 134 CNSS_HOST_DP_TX_COMP_0 = 41, 135 CNSS_HOST_DP_TX_COMP_0_HANDLE = 42, 136 CNSS_HOST_DP_TCL_DATA_1 = 43, 137 CNSS_HOST_DP_TCL_DATA_1_HANDLE = 44, 138 CNSS_HOST_DP_TX_COMP_1 = 45, 139 CNSS_HOST_DP_TX_COMP_1_HANDLE = 46, 140 CNSS_HOST_DP_TCL_DATA_2 = 47, 141 CNSS_HOST_DP_TCL_DATA_2_HANDLE = 48, 142 CNSS_HOST_DP_TX_COMP_2 = 49, 143 CNSS_HOST_DP_TX_COMP_2_HANDLE = 50, 144 CNSS_HOST_DP_REO_DST_0 = 51, 145 CNSS_HOST_DP_REO_DST_0_HANDLE = 52, 146 CNSS_HOST_DP_REO_DST_1 = 53, 147 CNSS_HOST_DP_REO_DST_1_HANDLE = 54, 148 CNSS_HOST_DP_REO_DST_2 = 55, 149 CNSS_HOST_DP_REO_DST_2_HANDLE = 56, 150 CNSS_HOST_DP_REO_DST_3 = 57, 151 CNSS_HOST_DP_REO_DST_3_HANDLE = 58, 152 CNSS_HOST_DP_REO_DST_4 = 59, 153 CNSS_HOST_DP_REO_DST_4_HANDLE = 60, 154 CNSS_HOST_DP_REO_DST_5 = 61, 155 CNSS_HOST_DP_REO_DST_5_HANDLE = 62, 156 CNSS_HOST_DP_REO_DST_6 = 63, 157 CNSS_HOST_DP_REO_DST_6_HANDLE = 64, 158 CNSS_HOST_DP_REO_DST_7 = 65, 159 CNSS_HOST_DP_REO_DST_7_HANDLE = 66, 160 CNSS_HOST_DP_PDEV_0 = 67, 161 CNSS_HOST_DP_WLAN_CFG_CTX = 68, 162 CNSS_HOST_DP_SOC = 69, 163 CNSS_HOST_HAL_RX_FST = 70, 164 CNSS_HOST_DP_FISA = 71, 165 CNSS_HOST_DP_FISA_HW_FSE_TABLE = 72, 166 CNSS_HOST_DP_FISA_SW_FSE_TABLE = 73, 167 CNSS_HOST_HIF = 74, 168 CNSS_HOST_QDF_NBUF_HIST = 75, 169 CNSS_HOST_TCL_WBM_MAP = 76, 170 CNSS_HOST_RX_MAC_BUF_RING_0 = 77, 171 CNSS_HOST_RX_MAC_BUF_RING_0_HANDLE = 78, 172 CNSS_HOST_RX_MAC_BUF_RING_1 = 79, 173 CNSS_HOST_RX_MAC_BUF_RING_1_HANDLE = 80, 174 CNSS_HOST_RX_REFILL_0 = 81, 175 CNSS_HOST_RX_REFILL_0_HANDLE = 82, 176 CNSS_HOST_CE_0 = 83, 177 CNSS_HOST_CE_0_SRC_RING = 84, 178 CNSS_HOST_CE_0_SRC_RING_CTX = 85, 179 CNSS_HOST_CE_1 = 86, 180 CNSS_HOST_CE_1_STATUS_RING = 87, 181 CNSS_HOST_CE_1_STATUS_RING_CTX = 88, 182 CNSS_HOST_CE_1_DEST_RING = 89, 183 CNSS_HOST_CE_1_DEST_RING_CTX = 90, 184 CNSS_HOST_CE_2 = 91, 185 CNSS_HOST_CE_2_STATUS_RING = 92, 186 CNSS_HOST_CE_2_STATUS_RING_CTX = 93, 187 CNSS_HOST_CE_2_DEST_RING = 94, 188 CNSS_HOST_CE_2_DEST_RING_CTX = 95, 189 CNSS_HOST_CE_3 = 96, 190 CNSS_HOST_CE_3_SRC_RING = 97, 191 CNSS_HOST_CE_3_SRC_RING_CTX = 98, 192 CNSS_HOST_CE_4 = 99, 193 CNSS_HOST_CE_4_SRC_RING = 100, 194 CNSS_HOST_CE_4_SRC_RING_CTX = 101, 195 CNSS_HOST_CE_5 = 102, 196 CNSS_HOST_CE_6 = 103, 197 CNSS_HOST_CE_7 = 104, 198 CNSS_HOST_CE_7_STATUS_RING = 105, 199 CNSS_HOST_CE_7_STATUS_RING_CTX = 106, 200 CNSS_HOST_CE_7_DEST_RING = 107, 201 CNSS_HOST_CE_7_DEST_RING_CTX = 108, 202 CNSS_HOST_CE_8 = 109, 203 CNSS_HOST_DP_TCL_DATA_3 = 110, 204 CNSS_HOST_DP_TCL_DATA_3_HANDLE = 111, 205 CNSS_HOST_DP_TX_COMP_3 = 112, 206 CNSS_HOST_DP_TX_COMP_3_HANDLE = 113, 207 CNSS_HOST_DUMP_TYPE_MAX = 114, 208 }; 209 210 enum cnss_bus_event_type { 211 BUS_EVENT_PCI_LINK_DOWN = 0, 212 BUS_EVENT_PCI_LINK_RESUME_FAIL = 1, 213 214 BUS_EVENT_INVALID = 0xFFFF, 215 }; 216 217 enum cnss_wfc_mode { 218 CNSS_WFC_MODE_OFF, 219 CNSS_WFC_MODE_ON, 220 }; 221 222 struct cnss_wfc_cfg { 223 enum cnss_wfc_mode mode; 224 }; 225 226 struct cnss_hang_event { 227 void *hang_event_data; 228 u16 hang_event_data_len; 229 }; 230 231 struct cnss_bus_event { 232 enum cnss_bus_event_type etype; 233 void *event_data; 234 }; 235 236 struct cnss_uevent_data { 237 enum cnss_driver_status status; 238 void *data; 239 }; 240 241 struct cnss_ssr_driver_dump_entry { 242 char region_name[CNSS_SSR_DRIVER_DUMP_MAX_REGIONS]; 243 void *buffer_pointer; 244 size_t buffer_size; 245 }; 246 247 248 struct cnss_wlan_driver { 249 char *name; 250 int (*probe)(struct pci_dev *pdev, const struct pci_device_id *id); 251 void (*remove)(struct pci_dev *pdev); 252 int (*idle_restart)(struct pci_dev *pdev, 253 const struct pci_device_id *id); 254 int (*idle_shutdown)(struct pci_dev *pdev); 255 int (*reinit)(struct pci_dev *pdev, const struct pci_device_id *id); 256 void (*shutdown)(struct pci_dev *pdev); 257 void (*crash_shutdown)(struct pci_dev *pdev); 258 int (*suspend)(struct pci_dev *pdev, pm_message_t state); 259 int (*resume)(struct pci_dev *pdev); 260 int (*suspend_noirq)(struct pci_dev *pdev); 261 int (*resume_noirq)(struct pci_dev *pdev); 262 void (*modem_status)(struct pci_dev *pdev, int state); 263 void (*update_status)(struct pci_dev *pdev, uint32_t status); 264 int (*update_event)(struct pci_dev *pdev, 265 struct cnss_uevent_data *uevent); 266 struct cnss_wlan_runtime_ops *runtime_ops; 267 const struct pci_device_id *id_table; 268 u32 chip_version; 269 enum cnss_driver_mode (*get_driver_mode)(void); 270 int (*collect_driver_dump)(struct pci_dev *pdev, 271 struct cnss_ssr_driver_dump_entry *input_array, 272 size_t *num_entries_loaded); 273 int (*set_therm_cdev_state)(struct pci_dev *pci_dev, 274 unsigned long thermal_state, 275 int tcdev_id); 276 }; 277 278 struct cnss_ce_tgt_pipe_cfg { 279 u32 pipe_num; 280 u32 pipe_dir; 281 u32 nentries; 282 u32 nbytes_max; 283 u32 flags; 284 u32 reserved; 285 }; 286 287 struct cnss_ce_svc_pipe_cfg { 288 u32 service_id; 289 u32 pipe_dir; 290 u32 pipe_num; 291 }; 292 293 struct cnss_shadow_reg_cfg { 294 u16 ce_id; 295 u16 reg_offset; 296 }; 297 298 struct cnss_shadow_reg_v2_cfg { 299 u32 addr; 300 }; 301 302 struct cnss_rri_over_ddr_cfg { 303 u32 base_addr_low; 304 u32 base_addr_high; 305 }; 306 307 struct cnss_shadow_reg_v3_cfg { 308 u32 addr; 309 }; 310 311 struct cnss_wlan_enable_cfg { 312 u32 num_ce_tgt_cfg; 313 struct cnss_ce_tgt_pipe_cfg *ce_tgt_cfg; 314 u32 num_ce_svc_pipe_cfg; 315 struct cnss_ce_svc_pipe_cfg *ce_svc_cfg; 316 u32 num_shadow_reg_cfg; 317 struct cnss_shadow_reg_cfg *shadow_reg_cfg; 318 u32 num_shadow_reg_v2_cfg; 319 struct cnss_shadow_reg_v2_cfg *shadow_reg_v2_cfg; 320 bool rri_over_ddr_cfg_valid; 321 struct cnss_rri_over_ddr_cfg rri_over_ddr_cfg; 322 u32 num_shadow_reg_v3_cfg; 323 struct cnss_shadow_reg_v3_cfg *shadow_reg_v3_cfg; 324 bool send_msi_ce; 325 }; 326 327 enum cnss_driver_mode { 328 CNSS_MISSION, 329 CNSS_FTM, 330 CNSS_EPPING, 331 CNSS_WALTEST, 332 CNSS_OFF, 333 CNSS_CCPM, 334 CNSS_QVIT, 335 CNSS_CALIBRATION, 336 }; 337 338 enum cnss_recovery_reason { 339 CNSS_REASON_DEFAULT, 340 CNSS_REASON_LINK_DOWN, 341 CNSS_REASON_RDDM, 342 CNSS_REASON_TIMEOUT, 343 }; 344 345 enum cnss_fw_caps { 346 CNSS_FW_CAP_DIRECT_LINK_SUPPORT, 347 CNSS_FW_CAP_AUX_UC_SUPPORT, 348 CNSS_FW_CAP_CALDB_SEG_DDR_SUPPORT, 349 }; 350 351 enum cnss_remote_mem_type { 352 CNSS_REMOTE_MEM_TYPE_FW, 353 CNSS_REMOTE_MEM_TYPE_QDSS, 354 CNSS_REMOTE_MEM_TYPE_MAX, 355 }; 356 357 struct cnss_mem_segment { 358 size_t size; 359 void *va; 360 phys_addr_t pa; 361 }; 362 363 extern int cnss_wlan_register_driver(struct cnss_wlan_driver *driver); 364 extern void cnss_wlan_unregister_driver(struct cnss_wlan_driver *driver); 365 extern void cnss_device_crashed(struct device *dev); 366 extern int cnss_pci_prevent_l1(struct device *dev); 367 extern void cnss_pci_allow_l1(struct device *dev); 368 extern int cnss_pci_link_down(struct device *dev); 369 extern int cnss_pci_is_device_down(struct device *dev); 370 extern void cnss_schedule_recovery(struct device *dev, 371 enum cnss_recovery_reason reason); 372 extern int cnss_self_recovery(struct device *dev, 373 enum cnss_recovery_reason reason); 374 extern int cnss_force_fw_assert(struct device *dev); 375 extern int cnss_force_collect_rddm(struct device *dev); 376 extern int cnss_qmi_send_get(struct device *dev); 377 extern int cnss_qmi_send_put(struct device *dev); 378 extern int cnss_qmi_send(struct device *dev, int type, void *cmd, 379 int cmd_len, void *cb_ctx, 380 int (*cb)(void *ctx, void *event, int event_len)); 381 extern void *cnss_get_virt_ramdump_mem(struct device *dev, unsigned long *size); 382 extern int cnss_get_fw_files_for_target(struct device *dev, 383 struct cnss_fw_files *pfw_files, 384 u32 target_type, u32 target_version); 385 extern int cnss_get_platform_cap(struct device *dev, 386 struct cnss_platform_cap *cap); 387 extern struct iommu_domain *cnss_smmu_get_domain(struct device *dev); 388 extern int cnss_smmu_map(struct device *dev, 389 phys_addr_t paddr, uint32_t *iova_addr, size_t size); 390 extern int cnss_smmu_unmap(struct device *dev, uint32_t iova_addr, size_t size); 391 extern int cnss_get_soc_info(struct device *dev, struct cnss_soc_info *info); 392 extern int cnss_request_bus_bandwidth(struct device *dev, int bandwidth); 393 extern int cnss_power_up(struct device *dev); 394 extern int cnss_power_down(struct device *dev); 395 extern int cnss_idle_restart(struct device *dev); 396 extern int cnss_idle_shutdown(struct device *dev); 397 extern void cnss_request_pm_qos(struct device *dev, u32 qos_val); 398 extern void cnss_remove_pm_qos(struct device *dev); 399 extern void cnss_lock_pm_sem(struct device *dev); 400 extern void cnss_release_pm_sem(struct device *dev); 401 extern void cnss_pci_lock_reg_window(struct device *dev, unsigned long *flags); 402 extern void cnss_pci_unlock_reg_window(struct device *dev, 403 unsigned long *flags); 404 extern int cnss_wlan_pm_control(struct device *dev, bool vote); 405 extern int cnss_auto_suspend(struct device *dev); 406 extern int cnss_auto_resume(struct device *dev); 407 extern int cnss_pci_is_drv_connected(struct device *dev); 408 extern int cnss_pci_force_wake_request_sync(struct device *dev, int timeout); 409 extern int cnss_pci_force_wake_request(struct device *dev); 410 extern int cnss_pci_is_device_awake(struct device *dev); 411 extern int cnss_pci_force_wake_release(struct device *dev); 412 extern int cnss_get_user_msi_assignment(struct device *dev, char *user_name, 413 int *num_vectors, 414 uint32_t *user_base_data, 415 uint32_t *base_vector); 416 extern int cnss_get_msi_irq(struct device *dev, unsigned int vector); 417 extern bool cnss_is_one_msi(struct device *dev); 418 extern void cnss_get_msi_address(struct device *dev, uint32_t *msi_addr_low, 419 uint32_t *msi_addr_high); 420 extern int cnss_wlan_hw_enable(void); 421 extern int cnss_wlan_enable(struct device *dev, 422 struct cnss_wlan_enable_cfg *config, 423 enum cnss_driver_mode mode, 424 const char *host_version); 425 extern int cnss_wlan_disable(struct device *dev, enum cnss_driver_mode mode); 426 extern unsigned int cnss_get_boot_timeout(struct device *dev); 427 extern int cnss_athdiag_read(struct device *dev, uint32_t offset, 428 uint32_t mem_type, uint32_t data_len, 429 uint8_t *output); 430 extern int cnss_athdiag_write(struct device *dev, uint32_t offset, 431 uint32_t mem_type, uint32_t data_len, 432 uint8_t *input); 433 extern int cnss_set_fw_log_mode(struct device *dev, uint8_t fw_log_mode); 434 extern int cnss_set_pcie_gen_speed(struct device *dev, u8 pcie_gen_speed); 435 extern int cnss_get_mem_seg_count(enum cnss_remote_mem_type type, u32 *seg); 436 extern int cnss_get_mem_segment_info(enum cnss_remote_mem_type type, 437 struct cnss_mem_segment segment[], 438 u32 segment_count); 439 extern bool cnss_get_audio_shared_iommu_group_cap(struct device *dev); 440 extern int cnss_audio_smmu_map(struct device *dev, phys_addr_t paddr, 441 dma_addr_t iova, size_t size); 442 extern void cnss_audio_smmu_unmap(struct device *dev, dma_addr_t iova, 443 size_t size); 444 extern int cnss_get_fw_lpass_shared_mem(struct device *dev, dma_addr_t *iova, 445 size_t *size); 446 extern int cnss_get_pci_slot(struct device *dev); 447 extern int cnss_pci_get_reg_dump(struct device *dev, uint8_t *buffer, 448 uint32_t len); 449 extern struct kobject *cnss_get_wifi_kobj(struct device *dev); 450 extern int cnss_send_buffer_to_afcmem(struct device *dev, const uint8_t *afcdb, 451 uint32_t len, uint8_t slotid); 452 extern int cnss_reset_afcmem(struct device *dev, uint8_t slotid); 453 extern bool cnss_get_fw_cap(struct device *dev, enum cnss_fw_caps fw_cap); 454 extern bool cnss_audio_is_direct_link_supported(struct device *dev); 455 extern int cnss_set_wfc_mode(struct device *dev, struct cnss_wfc_cfg cfg); 456 extern int cnss_thermal_cdev_register(struct device *dev, 457 unsigned long max_state, 458 int tcdev_id); 459 extern void cnss_thermal_cdev_unregister(struct device *dev, int tcdev_id); 460 extern int cnss_get_curr_therm_cdev_state(struct device *dev, 461 unsigned long *thermal_state, 462 int tcdev_id); 463 extern int cnss_update_time_sync_period(struct device *dev, 464 uint32_t time_sync_period); 465 extern int cnss_reset_time_sync_period(struct device *dev); 466 extern int cnss_register_driver_async_data_cb(struct device *dev, void *cb_ctx, 467 int (*cb)(void *ctx, 468 uint16_t type, void *event, 469 int event_len)); 470 #endif /* _NET_CNSS2_H */ 471