1 /*
2  * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 #ifndef _REO_FLUSH_QUEUE_STATUS_H_
19 #define _REO_FLUSH_QUEUE_STATUS_H_
20 
21 #include "uniform_reo_status_header.h"
22 #define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 27
23 
24 struct reo_flush_queue_status {
25 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
26              uint32_t tlv32_ring_padding                                      : 32;
27              struct   uniform_reo_status_header                                 status_header;
28              uint32_t error_detected                                          :  1,
29                       reserved_2a                                             : 31;
30              uint32_t reserved_3a                                             : 32;
31              uint32_t reserved_4a                                             : 32;
32              uint32_t reserved_5a                                             : 32;
33              uint32_t reserved_6a                                             : 32;
34              uint32_t reserved_7a                                             : 32;
35              uint32_t reserved_8a                                             : 32;
36              uint32_t reserved_9a                                             : 32;
37              uint32_t reserved_10a                                            : 32;
38              uint32_t reserved_11a                                            : 32;
39              uint32_t reserved_12a                                            : 32;
40              uint32_t reserved_13a                                            : 32;
41              uint32_t reserved_14a                                            : 32;
42              uint32_t reserved_15a                                            : 32;
43              uint32_t reserved_16a                                            : 32;
44              uint32_t reserved_17a                                            : 32;
45              uint32_t reserved_18a                                            : 32;
46              uint32_t reserved_19a                                            : 32;
47              uint32_t reserved_20a                                            : 32;
48              uint32_t reserved_21a                                            : 32;
49              uint32_t reserved_22a                                            : 32;
50              uint32_t reserved_23a                                            : 32;
51              uint32_t reserved_24a                                            : 32;
52              uint32_t reserved_25a                                            : 28,
53                       looping_count                                           :  4;
54 #else
55              uint32_t tlv32_ring_padding                                      : 32;
56              struct   uniform_reo_status_header                                 status_header;
57              uint32_t reserved_2a                                             : 31,
58                       error_detected                                          :  1;
59              uint32_t reserved_3a                                             : 32;
60              uint32_t reserved_4a                                             : 32;
61              uint32_t reserved_5a                                             : 32;
62              uint32_t reserved_6a                                             : 32;
63              uint32_t reserved_7a                                             : 32;
64              uint32_t reserved_8a                                             : 32;
65              uint32_t reserved_9a                                             : 32;
66              uint32_t reserved_10a                                            : 32;
67              uint32_t reserved_11a                                            : 32;
68              uint32_t reserved_12a                                            : 32;
69              uint32_t reserved_13a                                            : 32;
70              uint32_t reserved_14a                                            : 32;
71              uint32_t reserved_15a                                            : 32;
72              uint32_t reserved_16a                                            : 32;
73              uint32_t reserved_17a                                            : 32;
74              uint32_t reserved_18a                                            : 32;
75              uint32_t reserved_19a                                            : 32;
76              uint32_t reserved_20a                                            : 32;
77              uint32_t reserved_21a                                            : 32;
78              uint32_t reserved_22a                                            : 32;
79              uint32_t reserved_23a                                            : 32;
80              uint32_t reserved_24a                                            : 32;
81              uint32_t looping_count                                           :  4,
82                       reserved_25a                                            : 28;
83 #endif
84 };
85 
86 #define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_OFFSET                            0x00000000
87 #define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_LSB                               0
88 #define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_MSB                               31
89 #define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_MASK                              0xffffffff
90 
91 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET               0x00000004
92 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB                  0
93 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB                  15
94 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK                 0x0000ffff
95 
96 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET              0x00000004
97 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB                 16
98 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB                 25
99 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK                0x03ff0000
100 
101 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET        0x00000004
102 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB           26
103 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB           27
104 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK          0x0c000000
105 
106 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET                     0x00000004
107 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB                        28
108 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB                        31
109 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK                       0xf0000000
110 
111 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET                       0x00000008
112 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB                          0
113 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB                          31
114 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK                         0xffffffff
115 
116 #define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_OFFSET                                0x0000000c
117 #define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_LSB                                   0
118 #define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MSB                                   0
119 #define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MASK                                  0x00000001
120 
121 #define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_OFFSET                                   0x0000000c
122 #define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_LSB                                      1
123 #define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MSB                                      31
124 #define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MASK                                     0xfffffffe
125 
126 #define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_OFFSET                                   0x00000010
127 #define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_LSB                                      0
128 #define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MSB                                      31
129 #define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MASK                                     0xffffffff
130 
131 #define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_OFFSET                                   0x00000014
132 #define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_LSB                                      0
133 #define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MSB                                      31
134 #define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MASK                                     0xffffffff
135 
136 #define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_OFFSET                                   0x00000018
137 #define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_LSB                                      0
138 #define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MSB                                      31
139 #define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MASK                                     0xffffffff
140 
141 #define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_OFFSET                                   0x0000001c
142 #define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_LSB                                      0
143 #define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MSB                                      31
144 #define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MASK                                     0xffffffff
145 
146 #define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_OFFSET                                   0x00000020
147 #define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_LSB                                      0
148 #define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MSB                                      31
149 #define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MASK                                     0xffffffff
150 
151 #define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_OFFSET                                   0x00000024
152 #define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_LSB                                      0
153 #define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MSB                                      31
154 #define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MASK                                     0xffffffff
155 
156 #define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_OFFSET                                   0x00000028
157 #define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_LSB                                      0
158 #define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MSB                                      31
159 #define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MASK                                     0xffffffff
160 
161 #define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_OFFSET                                  0x0000002c
162 #define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_LSB                                     0
163 #define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MSB                                     31
164 #define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MASK                                    0xffffffff
165 
166 #define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_OFFSET                                  0x00000030
167 #define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_LSB                                     0
168 #define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MSB                                     31
169 #define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MASK                                    0xffffffff
170 
171 #define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_OFFSET                                  0x00000034
172 #define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_LSB                                     0
173 #define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MSB                                     31
174 #define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MASK                                    0xffffffff
175 
176 #define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_OFFSET                                  0x00000038
177 #define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_LSB                                     0
178 #define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MSB                                     31
179 #define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MASK                                    0xffffffff
180 
181 #define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_OFFSET                                  0x0000003c
182 #define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_LSB                                     0
183 #define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MSB                                     31
184 #define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MASK                                    0xffffffff
185 
186 #define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_OFFSET                                  0x00000040
187 #define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_LSB                                     0
188 #define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MSB                                     31
189 #define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MASK                                    0xffffffff
190 
191 #define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_OFFSET                                  0x00000044
192 #define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_LSB                                     0
193 #define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MSB                                     31
194 #define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MASK                                    0xffffffff
195 
196 #define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_OFFSET                                  0x00000048
197 #define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_LSB                                     0
198 #define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MSB                                     31
199 #define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MASK                                    0xffffffff
200 
201 #define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_OFFSET                                  0x0000004c
202 #define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_LSB                                     0
203 #define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MSB                                     31
204 #define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MASK                                    0xffffffff
205 
206 #define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_OFFSET                                  0x00000050
207 #define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_LSB                                     0
208 #define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MSB                                     31
209 #define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MASK                                    0xffffffff
210 
211 #define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_OFFSET                                  0x00000054
212 #define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_LSB                                     0
213 #define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MSB                                     31
214 #define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MASK                                    0xffffffff
215 
216 #define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_OFFSET                                  0x00000058
217 #define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_LSB                                     0
218 #define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MSB                                     31
219 #define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MASK                                    0xffffffff
220 
221 #define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_OFFSET                                  0x0000005c
222 #define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_LSB                                     0
223 #define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MSB                                     31
224 #define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MASK                                    0xffffffff
225 
226 #define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_OFFSET                                  0x00000060
227 #define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_LSB                                     0
228 #define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MSB                                     31
229 #define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MASK                                    0xffffffff
230 
231 #define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_OFFSET                                  0x00000064
232 #define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_LSB                                     0
233 #define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MSB                                     31
234 #define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MASK                                    0xffffffff
235 
236 #define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_OFFSET                                  0x00000068
237 #define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_LSB                                     0
238 #define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MSB                                     27
239 #define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MASK                                    0x0fffffff
240 
241 #define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_OFFSET                                 0x00000068
242 #define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_LSB                                    28
243 #define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MSB                                    31
244 #define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MASK                                   0xf0000000
245 
246 #endif
247