1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _TX_MSDU_EXTENSION_H_ 23 #define _TX_MSDU_EXTENSION_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 28 29 struct tx_msdu_extension { 30 uint32_t tso_enable : 1, 31 reserved_0a : 6, 32 tcp_flag : 9, 33 tcp_flag_mask : 9, 34 reserved_0b : 7; 35 uint32_t l2_length : 16, 36 ip_length : 16; 37 uint32_t tcp_seq_number : 32; 38 uint32_t ip_identification : 16, 39 udp_length : 16; 40 uint32_t checksum_offset : 14, 41 partial_checksum_en : 1, 42 reserved_4a : 1, 43 payload_start_offset : 14, 44 reserved_4b : 2; 45 uint32_t payload_end_offset : 14, 46 reserved_5a : 2, 47 wds : 1, 48 reserved_5b : 15; 49 uint32_t buf0_ptr_31_0 : 32; 50 uint32_t buf0_ptr_39_32 : 8, 51 reserved_7a : 8, 52 buf0_len : 16; 53 uint32_t buf1_ptr_31_0 : 32; 54 uint32_t buf1_ptr_39_32 : 8, 55 reserved_9a : 8, 56 buf1_len : 16; 57 uint32_t buf2_ptr_31_0 : 32; 58 uint32_t buf2_ptr_39_32 : 8, 59 reserved_11a : 8, 60 buf2_len : 16; 61 uint32_t buf3_ptr_31_0 : 32; 62 uint32_t buf3_ptr_39_32 : 8, 63 reserved_13a : 8, 64 buf3_len : 16; 65 uint32_t buf4_ptr_31_0 : 32; 66 uint32_t buf4_ptr_39_32 : 8, 67 reserved_15a : 8, 68 buf4_len : 16; 69 uint32_t buf5_ptr_31_0 : 32; 70 uint32_t buf5_ptr_39_32 : 8, 71 reserved_17a : 8, 72 buf5_len : 16; 73 }; 74 75 #define TX_MSDU_EXTENSION_0_TSO_ENABLE_OFFSET 0x00000000 76 #define TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB 0 77 #define TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK 0x00000001 78 79 #define TX_MSDU_EXTENSION_0_RESERVED_0A_OFFSET 0x00000000 80 #define TX_MSDU_EXTENSION_0_RESERVED_0A_LSB 1 81 #define TX_MSDU_EXTENSION_0_RESERVED_0A_MASK 0x0000007e 82 83 #define TX_MSDU_EXTENSION_0_TCP_FLAG_OFFSET 0x00000000 84 #define TX_MSDU_EXTENSION_0_TCP_FLAG_LSB 7 85 #define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK 0x0000ff80 86 87 #define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_OFFSET 0x00000000 88 #define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_LSB 16 89 #define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_MASK 0x01ff0000 90 91 #define TX_MSDU_EXTENSION_0_RESERVED_0B_OFFSET 0x00000000 92 #define TX_MSDU_EXTENSION_0_RESERVED_0B_LSB 25 93 #define TX_MSDU_EXTENSION_0_RESERVED_0B_MASK 0xfe000000 94 95 #define TX_MSDU_EXTENSION_1_L2_LENGTH_OFFSET 0x00000004 96 #define TX_MSDU_EXTENSION_1_L2_LENGTH_LSB 0 97 #define TX_MSDU_EXTENSION_1_L2_LENGTH_MASK 0x0000ffff 98 99 #define TX_MSDU_EXTENSION_1_IP_LENGTH_OFFSET 0x00000004 100 #define TX_MSDU_EXTENSION_1_IP_LENGTH_LSB 16 101 #define TX_MSDU_EXTENSION_1_IP_LENGTH_MASK 0xffff0000 102 103 #define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_OFFSET 0x00000008 104 #define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_LSB 0 105 #define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_MASK 0xffffffff 106 107 #define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_OFFSET 0x0000000c 108 #define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_LSB 0 109 #define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_MASK 0x0000ffff 110 111 #define TX_MSDU_EXTENSION_3_UDP_LENGTH_OFFSET 0x0000000c 112 #define TX_MSDU_EXTENSION_3_UDP_LENGTH_LSB 16 113 #define TX_MSDU_EXTENSION_3_UDP_LENGTH_MASK 0xffff0000 114 115 #define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_OFFSET 0x00000010 116 #define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_LSB 0 117 #define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_MASK 0x00003fff 118 119 #define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 120 #define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_LSB 14 121 #define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_MASK 0x00004000 122 123 #define TX_MSDU_EXTENSION_4_RESERVED_4A_OFFSET 0x00000010 124 #define TX_MSDU_EXTENSION_4_RESERVED_4A_LSB 15 125 #define TX_MSDU_EXTENSION_4_RESERVED_4A_MASK 0x00008000 126 127 #define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_OFFSET 0x00000010 128 #define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_LSB 16 129 #define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_MASK 0x3fff0000 130 131 #define TX_MSDU_EXTENSION_4_RESERVED_4B_OFFSET 0x00000010 132 #define TX_MSDU_EXTENSION_4_RESERVED_4B_LSB 30 133 #define TX_MSDU_EXTENSION_4_RESERVED_4B_MASK 0xc0000000 134 135 #define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_OFFSET 0x00000014 136 #define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_LSB 0 137 #define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_MASK 0x00003fff 138 139 #define TX_MSDU_EXTENSION_5_RESERVED_5A_OFFSET 0x00000014 140 #define TX_MSDU_EXTENSION_5_RESERVED_5A_LSB 14 141 #define TX_MSDU_EXTENSION_5_RESERVED_5A_MASK 0x0000c000 142 143 #define TX_MSDU_EXTENSION_5_WDS_OFFSET 0x00000014 144 #define TX_MSDU_EXTENSION_5_WDS_LSB 16 145 #define TX_MSDU_EXTENSION_5_WDS_MASK 0x00010000 146 147 #define TX_MSDU_EXTENSION_5_RESERVED_5B_OFFSET 0x00000014 148 #define TX_MSDU_EXTENSION_5_RESERVED_5B_LSB 17 149 #define TX_MSDU_EXTENSION_5_RESERVED_5B_MASK 0xfffe0000 150 151 #define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 0x00000018 152 #define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_LSB 0 153 #define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 0xffffffff 154 155 #define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_OFFSET 0x0000001c 156 #define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_LSB 0 157 #define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 0x000000ff 158 159 #define TX_MSDU_EXTENSION_7_RESERVED_7A_OFFSET 0x0000001c 160 #define TX_MSDU_EXTENSION_7_RESERVED_7A_LSB 8 161 #define TX_MSDU_EXTENSION_7_RESERVED_7A_MASK 0x0000ff00 162 163 #define TX_MSDU_EXTENSION_7_BUF0_LEN_OFFSET 0x0000001c 164 #define TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 16 165 #define TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 0xffff0000 166 167 #define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_OFFSET 0x00000020 168 #define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_LSB 0 169 #define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_MASK 0xffffffff 170 171 #define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_OFFSET 0x00000024 172 #define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_LSB 0 173 #define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_MASK 0x000000ff 174 175 #define TX_MSDU_EXTENSION_9_RESERVED_9A_OFFSET 0x00000024 176 #define TX_MSDU_EXTENSION_9_RESERVED_9A_LSB 8 177 #define TX_MSDU_EXTENSION_9_RESERVED_9A_MASK 0x0000ff00 178 179 #define TX_MSDU_EXTENSION_9_BUF1_LEN_OFFSET 0x00000024 180 #define TX_MSDU_EXTENSION_9_BUF1_LEN_LSB 16 181 #define TX_MSDU_EXTENSION_9_BUF1_LEN_MASK 0xffff0000 182 183 #define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_OFFSET 0x00000028 184 #define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_LSB 0 185 #define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_MASK 0xffffffff 186 187 #define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_OFFSET 0x0000002c 188 #define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_LSB 0 189 #define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_MASK 0x000000ff 190 191 #define TX_MSDU_EXTENSION_11_RESERVED_11A_OFFSET 0x0000002c 192 #define TX_MSDU_EXTENSION_11_RESERVED_11A_LSB 8 193 #define TX_MSDU_EXTENSION_11_RESERVED_11A_MASK 0x0000ff00 194 195 #define TX_MSDU_EXTENSION_11_BUF2_LEN_OFFSET 0x0000002c 196 #define TX_MSDU_EXTENSION_11_BUF2_LEN_LSB 16 197 #define TX_MSDU_EXTENSION_11_BUF2_LEN_MASK 0xffff0000 198 199 #define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_OFFSET 0x00000030 200 #define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_LSB 0 201 #define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_MASK 0xffffffff 202 203 #define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_OFFSET 0x00000034 204 #define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_LSB 0 205 #define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_MASK 0x000000ff 206 207 #define TX_MSDU_EXTENSION_13_RESERVED_13A_OFFSET 0x00000034 208 #define TX_MSDU_EXTENSION_13_RESERVED_13A_LSB 8 209 #define TX_MSDU_EXTENSION_13_RESERVED_13A_MASK 0x0000ff00 210 211 #define TX_MSDU_EXTENSION_13_BUF3_LEN_OFFSET 0x00000034 212 #define TX_MSDU_EXTENSION_13_BUF3_LEN_LSB 16 213 #define TX_MSDU_EXTENSION_13_BUF3_LEN_MASK 0xffff0000 214 215 #define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_OFFSET 0x00000038 216 #define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_LSB 0 217 #define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_MASK 0xffffffff 218 219 #define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_OFFSET 0x0000003c 220 #define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_LSB 0 221 #define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_MASK 0x000000ff 222 223 #define TX_MSDU_EXTENSION_15_RESERVED_15A_OFFSET 0x0000003c 224 #define TX_MSDU_EXTENSION_15_RESERVED_15A_LSB 8 225 #define TX_MSDU_EXTENSION_15_RESERVED_15A_MASK 0x0000ff00 226 227 #define TX_MSDU_EXTENSION_15_BUF4_LEN_OFFSET 0x0000003c 228 #define TX_MSDU_EXTENSION_15_BUF4_LEN_LSB 16 229 #define TX_MSDU_EXTENSION_15_BUF4_LEN_MASK 0xffff0000 230 231 #define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_OFFSET 0x00000040 232 #define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_LSB 0 233 #define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_MASK 0xffffffff 234 235 #define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_OFFSET 0x00000044 236 #define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_LSB 0 237 #define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_MASK 0x000000ff 238 239 #define TX_MSDU_EXTENSION_17_RESERVED_17A_OFFSET 0x00000044 240 #define TX_MSDU_EXTENSION_17_RESERVED_17A_LSB 8 241 #define TX_MSDU_EXTENSION_17_RESERVED_17A_MASK 0x0000ff00 242 243 #define TX_MSDU_EXTENSION_17_BUF5_LEN_OFFSET 0x00000044 244 #define TX_MSDU_EXTENSION_17_BUF5_LEN_LSB 16 245 #define TX_MSDU_EXTENSION_17_BUF5_LEN_MASK 0xffff0000 246 247 #endif 248