1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _RX_MPDU_INFO_H_ 23 #define _RX_MPDU_INFO_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "rxpt_classify_info.h" 28 29 #define NUM_OF_DWORDS_RX_MPDU_INFO 23 30 31 struct rx_mpdu_info { 32 struct rxpt_classify_info rxpt_classify_info_details; 33 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 34 uint32_t rx_reo_queue_desc_addr_39_32 : 8, 35 receive_queue_number : 16, 36 pre_delim_err_warning : 1, 37 first_delim_err : 1, 38 reserved_2a : 6; 39 uint32_t pn_31_0 : 32; 40 uint32_t pn_63_32 : 32; 41 uint32_t pn_95_64 : 32; 42 uint32_t pn_127_96 : 32; 43 uint32_t epd_en : 1, 44 all_frames_shall_be_encrypted : 1, 45 encrypt_type : 4, 46 wep_key_width_for_variable_key : 2, 47 __reserved_g_0003 : 2, 48 bssid_hit : 1, 49 bssid_number : 4, 50 tid : 4, 51 reserved_7a : 13; 52 uint32_t peer_meta_data : 32; 53 uint32_t rxpcu_mpdu_filter_in_category : 2, 54 sw_frame_group_id : 7, 55 ndp_frame : 1, 56 phy_err : 1, 57 phy_err_during_mpdu_header : 1, 58 protocol_version_err : 1, 59 ast_based_lookup_valid : 1, 60 reserved_9a : 2, 61 phy_ppdu_id : 16; 62 uint32_t ast_index : 16, 63 sw_peer_id : 16; 64 uint32_t mpdu_frame_control_valid : 1, 65 mpdu_duration_valid : 1, 66 mac_addr_ad1_valid : 1, 67 mac_addr_ad2_valid : 1, 68 mac_addr_ad3_valid : 1, 69 mac_addr_ad4_valid : 1, 70 mpdu_sequence_control_valid : 1, 71 mpdu_qos_control_valid : 1, 72 mpdu_ht_control_valid : 1, 73 frame_encryption_info_valid : 1, 74 mpdu_fragment_number : 4, 75 more_fragment_flag : 1, 76 reserved_11a : 1, 77 fr_ds : 1, 78 to_ds : 1, 79 encrypted : 1, 80 mpdu_retry : 1, 81 mpdu_sequence_number : 12; 82 uint32_t key_id_octet : 8, 83 new_peer_entry : 1, 84 decrypt_needed : 1, 85 decap_type : 2, 86 rx_insert_vlan_c_tag_padding : 1, 87 rx_insert_vlan_s_tag_padding : 1, 88 strip_vlan_c_tag_decap : 1, 89 strip_vlan_s_tag_decap : 1, 90 pre_delim_count : 12, 91 ampdu_flag : 1, 92 bar_frame : 1, 93 raw_mpdu : 1, 94 reserved_12 : 1; 95 uint32_t mpdu_length : 14, 96 first_mpdu : 1, 97 mcast_bcast : 1, 98 ast_index_not_found : 1, 99 ast_index_timeout : 1, 100 power_mgmt : 1, 101 non_qos : 1, 102 null_data : 1, 103 mgmt_type : 1, 104 ctrl_type : 1, 105 more_data : 1, 106 eosp : 1, 107 fragment_flag : 1, 108 order : 1, 109 u_apsd_trigger : 1, 110 encrypt_required : 1, 111 directed : 1, 112 amsdu_present : 1, 113 reserved_13 : 1; 114 uint32_t mpdu_frame_control_field : 16, 115 mpdu_duration_field : 16; 116 uint32_t mac_addr_ad1_31_0 : 32; 117 uint32_t mac_addr_ad1_47_32 : 16, 118 mac_addr_ad2_15_0 : 16; 119 uint32_t mac_addr_ad2_47_16 : 32; 120 uint32_t mac_addr_ad3_31_0 : 32; 121 uint32_t mac_addr_ad3_47_32 : 16, 122 mpdu_sequence_control_field : 16; 123 uint32_t mac_addr_ad4_31_0 : 32; 124 uint32_t mac_addr_ad4_47_32 : 16, 125 mpdu_qos_control_field : 16; 126 uint32_t mpdu_ht_control_field : 32; 127 }; 128 129 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 130 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 131 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 132 133 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 134 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 135 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 136 137 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 138 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 139 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 140 141 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 142 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 143 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 144 145 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 146 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 147 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 148 149 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 150 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 151 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 152 153 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 154 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 155 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800 156 157 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 158 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13 159 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000 160 161 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 162 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15 163 #define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000 164 165 #define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 166 #define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 167 #define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 168 169 #define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 170 #define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 171 #define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 172 173 #define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 174 #define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_LSB 8 175 #define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 176 177 #define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 178 #define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_LSB 24 179 #define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_MASK 0x01000000 180 181 #define RX_MPDU_INFO_2_FIRST_DELIM_ERR_OFFSET 0x00000008 182 #define RX_MPDU_INFO_2_FIRST_DELIM_ERR_LSB 25 183 #define RX_MPDU_INFO_2_FIRST_DELIM_ERR_MASK 0x02000000 184 185 #define RX_MPDU_INFO_2_RESERVED_2A_OFFSET 0x00000008 186 #define RX_MPDU_INFO_2_RESERVED_2A_LSB 26 187 #define RX_MPDU_INFO_2_RESERVED_2A_MASK 0xfc000000 188 189 #define RX_MPDU_INFO_3_PN_31_0_OFFSET 0x0000000c 190 #define RX_MPDU_INFO_3_PN_31_0_LSB 0 191 #define RX_MPDU_INFO_3_PN_31_0_MASK 0xffffffff 192 193 #define RX_MPDU_INFO_4_PN_63_32_OFFSET 0x00000010 194 #define RX_MPDU_INFO_4_PN_63_32_LSB 0 195 #define RX_MPDU_INFO_4_PN_63_32_MASK 0xffffffff 196 197 #define RX_MPDU_INFO_5_PN_95_64_OFFSET 0x00000014 198 #define RX_MPDU_INFO_5_PN_95_64_LSB 0 199 #define RX_MPDU_INFO_5_PN_95_64_MASK 0xffffffff 200 201 #define RX_MPDU_INFO_6_PN_127_96_OFFSET 0x00000018 202 #define RX_MPDU_INFO_6_PN_127_96_LSB 0 203 #define RX_MPDU_INFO_6_PN_127_96_MASK 0xffffffff 204 205 #define RX_MPDU_INFO_7_EPD_EN_OFFSET 0x0000001c 206 #define RX_MPDU_INFO_7_EPD_EN_LSB 0 207 #define RX_MPDU_INFO_7_EPD_EN_MASK 0x00000001 208 209 #define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c 210 #define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 211 #define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 212 213 #define RX_MPDU_INFO_7_ENCRYPT_TYPE_OFFSET 0x0000001c 214 #define RX_MPDU_INFO_7_ENCRYPT_TYPE_LSB 2 215 #define RX_MPDU_INFO_7_ENCRYPT_TYPE_MASK 0x0000003c 216 217 #define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c 218 #define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 219 #define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 220 221 #define RX_MPDU_INFO_7_BSSID_HIT_OFFSET 0x0000001c 222 #define RX_MPDU_INFO_7_BSSID_HIT_LSB 10 223 #define RX_MPDU_INFO_7_BSSID_HIT_MASK 0x00000400 224 225 #define RX_MPDU_INFO_7_BSSID_NUMBER_OFFSET 0x0000001c 226 #define RX_MPDU_INFO_7_BSSID_NUMBER_LSB 11 227 #define RX_MPDU_INFO_7_BSSID_NUMBER_MASK 0x00007800 228 229 #define RX_MPDU_INFO_7_TID_OFFSET 0x0000001c 230 #define RX_MPDU_INFO_7_TID_LSB 15 231 #define RX_MPDU_INFO_7_TID_MASK 0x00078000 232 233 #define RX_MPDU_INFO_7_RESERVED_7A_OFFSET 0x0000001c 234 #define RX_MPDU_INFO_7_RESERVED_7A_LSB 19 235 #define RX_MPDU_INFO_7_RESERVED_7A_MASK 0xfff80000 236 237 #define RX_MPDU_INFO_8_PEER_META_DATA_OFFSET 0x00000020 238 #define RX_MPDU_INFO_8_PEER_META_DATA_LSB 0 239 #define RX_MPDU_INFO_8_PEER_META_DATA_MASK 0xffffffff 240 241 #define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 242 #define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 243 #define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 244 245 #define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET 0x00000024 246 #define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB 2 247 #define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK 0x000001fc 248 249 #define RX_MPDU_INFO_9_NDP_FRAME_OFFSET 0x00000024 250 #define RX_MPDU_INFO_9_NDP_FRAME_LSB 9 251 #define RX_MPDU_INFO_9_NDP_FRAME_MASK 0x00000200 252 253 #define RX_MPDU_INFO_9_PHY_ERR_OFFSET 0x00000024 254 #define RX_MPDU_INFO_9_PHY_ERR_LSB 10 255 #define RX_MPDU_INFO_9_PHY_ERR_MASK 0x00000400 256 257 #define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 258 #define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_LSB 11 259 #define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 260 261 #define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 262 #define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_LSB 12 263 #define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_MASK 0x00001000 264 265 #define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 266 #define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_LSB 13 267 #define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_MASK 0x00002000 268 269 #define RX_MPDU_INFO_9_RESERVED_9A_OFFSET 0x00000024 270 #define RX_MPDU_INFO_9_RESERVED_9A_LSB 14 271 #define RX_MPDU_INFO_9_RESERVED_9A_MASK 0x0000c000 272 273 #define RX_MPDU_INFO_9_PHY_PPDU_ID_OFFSET 0x00000024 274 #define RX_MPDU_INFO_9_PHY_PPDU_ID_LSB 16 275 #define RX_MPDU_INFO_9_PHY_PPDU_ID_MASK 0xffff0000 276 277 #define RX_MPDU_INFO_10_AST_INDEX_OFFSET 0x00000028 278 #define RX_MPDU_INFO_10_AST_INDEX_LSB 0 279 #define RX_MPDU_INFO_10_AST_INDEX_MASK 0x0000ffff 280 281 #define RX_MPDU_INFO_10_SW_PEER_ID_OFFSET 0x00000028 282 #define RX_MPDU_INFO_10_SW_PEER_ID_LSB 16 283 #define RX_MPDU_INFO_10_SW_PEER_ID_MASK 0xffff0000 284 285 #define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c 286 #define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB 0 287 #define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 288 289 #define RX_MPDU_INFO_11_MPDU_DURATION_VALID_OFFSET 0x0000002c 290 #define RX_MPDU_INFO_11_MPDU_DURATION_VALID_LSB 1 291 #define RX_MPDU_INFO_11_MPDU_DURATION_VALID_MASK 0x00000002 292 293 #define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c 294 #define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB 2 295 #define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK 0x00000004 296 297 #define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c 298 #define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB 3 299 #define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK 0x00000008 300 301 #define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c 302 #define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB 4 303 #define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK 0x00000010 304 305 #define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c 306 #define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB 5 307 #define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK 0x00000020 308 309 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c 310 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 311 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 312 313 #define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c 314 #define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB 7 315 #define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 316 317 #define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c 318 #define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_LSB 8 319 #define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_MASK 0x00000100 320 321 #define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c 322 #define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB 9 323 #define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 324 325 #define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c 326 #define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_LSB 10 327 #define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 328 329 #define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c 330 #define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_LSB 14 331 #define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_MASK 0x00004000 332 333 #define RX_MPDU_INFO_11_RESERVED_11A_OFFSET 0x0000002c 334 #define RX_MPDU_INFO_11_RESERVED_11A_LSB 15 335 #define RX_MPDU_INFO_11_RESERVED_11A_MASK 0x00008000 336 337 #define RX_MPDU_INFO_11_FR_DS_OFFSET 0x0000002c 338 #define RX_MPDU_INFO_11_FR_DS_LSB 16 339 #define RX_MPDU_INFO_11_FR_DS_MASK 0x00010000 340 341 #define RX_MPDU_INFO_11_TO_DS_OFFSET 0x0000002c 342 #define RX_MPDU_INFO_11_TO_DS_LSB 17 343 #define RX_MPDU_INFO_11_TO_DS_MASK 0x00020000 344 345 #define RX_MPDU_INFO_11_ENCRYPTED_OFFSET 0x0000002c 346 #define RX_MPDU_INFO_11_ENCRYPTED_LSB 18 347 #define RX_MPDU_INFO_11_ENCRYPTED_MASK 0x00040000 348 349 #define RX_MPDU_INFO_11_MPDU_RETRY_OFFSET 0x0000002c 350 #define RX_MPDU_INFO_11_MPDU_RETRY_LSB 19 351 #define RX_MPDU_INFO_11_MPDU_RETRY_MASK 0x00080000 352 353 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c 354 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB 20 355 #define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 356 357 #define RX_MPDU_INFO_12_KEY_ID_OCTET_OFFSET 0x00000030 358 #define RX_MPDU_INFO_12_KEY_ID_OCTET_LSB 0 359 #define RX_MPDU_INFO_12_KEY_ID_OCTET_MASK 0x000000ff 360 361 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_OFFSET 0x00000030 362 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_LSB 8 363 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_MASK 0x00000100 364 365 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_OFFSET 0x00000030 366 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_LSB 9 367 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_MASK 0x00000200 368 369 #define RX_MPDU_INFO_12_DECAP_TYPE_OFFSET 0x00000030 370 #define RX_MPDU_INFO_12_DECAP_TYPE_LSB 10 371 #define RX_MPDU_INFO_12_DECAP_TYPE_MASK 0x00000c00 372 373 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 374 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 375 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 376 377 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 378 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 379 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 380 381 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 382 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_LSB 14 383 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 384 385 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 386 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_LSB 15 387 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 388 389 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_OFFSET 0x00000030 390 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_LSB 16 391 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_MASK 0x0fff0000 392 393 #define RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET 0x00000030 394 #define RX_MPDU_INFO_12_AMPDU_FLAG_LSB 28 395 #define RX_MPDU_INFO_12_AMPDU_FLAG_MASK 0x10000000 396 397 #define RX_MPDU_INFO_12_BAR_FRAME_OFFSET 0x00000030 398 #define RX_MPDU_INFO_12_BAR_FRAME_LSB 29 399 #define RX_MPDU_INFO_12_BAR_FRAME_MASK 0x20000000 400 401 #define RX_MPDU_INFO_12_RAW_MPDU_OFFSET 0x00000030 402 #define RX_MPDU_INFO_12_RAW_MPDU_LSB 30 403 #define RX_MPDU_INFO_12_RAW_MPDU_MASK 0x40000000 404 405 #define RX_MPDU_INFO_12_RESERVED_12_OFFSET 0x00000030 406 #define RX_MPDU_INFO_12_RESERVED_12_LSB 31 407 #define RX_MPDU_INFO_12_RESERVED_12_MASK 0x80000000 408 409 #define RX_MPDU_INFO_13_MPDU_LENGTH_OFFSET 0x00000034 410 #define RX_MPDU_INFO_13_MPDU_LENGTH_LSB 0 411 #define RX_MPDU_INFO_13_MPDU_LENGTH_MASK 0x00003fff 412 413 #define RX_MPDU_INFO_13_FIRST_MPDU_OFFSET 0x00000034 414 #define RX_MPDU_INFO_13_FIRST_MPDU_LSB 14 415 #define RX_MPDU_INFO_13_FIRST_MPDU_MASK 0x00004000 416 417 #define RX_MPDU_INFO_13_MCAST_BCAST_OFFSET 0x00000034 418 #define RX_MPDU_INFO_13_MCAST_BCAST_LSB 15 419 #define RX_MPDU_INFO_13_MCAST_BCAST_MASK 0x00008000 420 421 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 422 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_LSB 16 423 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_MASK 0x00010000 424 425 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_OFFSET 0x00000034 426 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_LSB 17 427 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_MASK 0x00020000 428 429 #define RX_MPDU_INFO_13_POWER_MGMT_OFFSET 0x00000034 430 #define RX_MPDU_INFO_13_POWER_MGMT_LSB 18 431 #define RX_MPDU_INFO_13_POWER_MGMT_MASK 0x00040000 432 433 #define RX_MPDU_INFO_13_NON_QOS_OFFSET 0x00000034 434 #define RX_MPDU_INFO_13_NON_QOS_LSB 19 435 #define RX_MPDU_INFO_13_NON_QOS_MASK 0x00080000 436 437 #define RX_MPDU_INFO_13_NULL_DATA_OFFSET 0x00000034 438 #define RX_MPDU_INFO_13_NULL_DATA_LSB 20 439 #define RX_MPDU_INFO_13_NULL_DATA_MASK 0x00100000 440 441 #define RX_MPDU_INFO_13_MGMT_TYPE_OFFSET 0x00000034 442 #define RX_MPDU_INFO_13_MGMT_TYPE_LSB 21 443 #define RX_MPDU_INFO_13_MGMT_TYPE_MASK 0x00200000 444 445 #define RX_MPDU_INFO_13_CTRL_TYPE_OFFSET 0x00000034 446 #define RX_MPDU_INFO_13_CTRL_TYPE_LSB 22 447 #define RX_MPDU_INFO_13_CTRL_TYPE_MASK 0x00400000 448 449 #define RX_MPDU_INFO_13_MORE_DATA_OFFSET 0x00000034 450 #define RX_MPDU_INFO_13_MORE_DATA_LSB 23 451 #define RX_MPDU_INFO_13_MORE_DATA_MASK 0x00800000 452 453 #define RX_MPDU_INFO_13_EOSP_OFFSET 0x00000034 454 #define RX_MPDU_INFO_13_EOSP_LSB 24 455 #define RX_MPDU_INFO_13_EOSP_MASK 0x01000000 456 457 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_OFFSET 0x00000034 458 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_LSB 25 459 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_MASK 0x02000000 460 461 #define RX_MPDU_INFO_13_ORDER_OFFSET 0x00000034 462 #define RX_MPDU_INFO_13_ORDER_LSB 26 463 #define RX_MPDU_INFO_13_ORDER_MASK 0x04000000 464 465 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_OFFSET 0x00000034 466 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_LSB 27 467 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_MASK 0x08000000 468 469 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_OFFSET 0x00000034 470 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_LSB 28 471 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_MASK 0x10000000 472 473 #define RX_MPDU_INFO_13_DIRECTED_OFFSET 0x00000034 474 #define RX_MPDU_INFO_13_DIRECTED_LSB 29 475 #define RX_MPDU_INFO_13_DIRECTED_MASK 0x20000000 476 477 #define RX_MPDU_INFO_13_AMSDU_PRESENT_OFFSET 0x00000034 478 #define RX_MPDU_INFO_13_AMSDU_PRESENT_LSB 30 479 #define RX_MPDU_INFO_13_AMSDU_PRESENT_MASK 0x40000000 480 481 #define RX_MPDU_INFO_13_RESERVED_13_OFFSET 0x00000034 482 #define RX_MPDU_INFO_13_RESERVED_13_LSB 31 483 #define RX_MPDU_INFO_13_RESERVED_13_MASK 0x80000000 484 485 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 486 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB 0 487 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff 488 489 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_OFFSET 0x00000038 490 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_LSB 16 491 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_MASK 0xffff0000 492 493 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c 494 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB 0 495 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK 0xffffffff 496 497 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 498 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB 0 499 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK 0x0000ffff 500 501 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 502 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB 16 503 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK 0xffff0000 504 505 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 506 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB 0 507 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK 0xffffffff 508 509 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 510 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB 0 511 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK 0xffffffff 512 513 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c 514 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB 0 515 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK 0x0000ffff 516 517 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c 518 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 519 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 520 521 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 522 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB 0 523 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK 0xffffffff 524 525 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 526 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB 0 527 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK 0x0000ffff 528 529 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 530 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_LSB 16 531 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 532 533 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 534 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_LSB 0 535 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff 536 537 #endif 538