1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _REO_FLUSH_CACHE_H_ 23 #define _REO_FLUSH_CACHE_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "uniform_reo_cmd_header.h" 28 29 #define NUM_OF_DWORDS_REO_FLUSH_CACHE 9 30 31 struct reo_flush_cache { 32 struct uniform_reo_cmd_header cmd_header; 33 uint32_t flush_addr_31_0 : 32; 34 uint32_t flush_addr_39_32 : 8, 35 forward_all_mpdus_in_queue : 1, 36 release_cache_block_index : 1, 37 cache_block_resource_index : 2, 38 flush_without_invalidate : 1, 39 block_cache_usage_after_flush : 1, 40 flush_entire_cache : 1, 41 reserved_2b : 17; 42 uint32_t reserved_3a : 32; 43 uint32_t reserved_4a : 32; 44 uint32_t reserved_5a : 32; 45 uint32_t reserved_6a : 32; 46 uint32_t reserved_7a : 32; 47 uint32_t reserved_8a : 32; 48 }; 49 50 #define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 51 #define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 52 #define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff 53 54 #define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 55 #define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 56 #define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 57 58 #define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 59 #define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_LSB 17 60 #define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 61 62 #define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_OFFSET 0x00000004 63 #define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_LSB 0 64 #define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_MASK 0xffffffff 65 66 #define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_OFFSET 0x00000008 67 #define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_LSB 0 68 #define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_MASK 0x000000ff 69 70 #define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x00000008 71 #define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 72 #define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x00000100 73 74 #define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x00000008 75 #define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_LSB 9 76 #define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_MASK 0x00000200 77 78 #define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 79 #define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 80 #define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000c00 81 82 #define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x00000008 83 #define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_LSB 12 84 #define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_MASK 0x00001000 85 86 #define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x00000008 87 #define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 88 #define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x00002000 89 90 #define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_OFFSET 0x00000008 91 #define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_LSB 14 92 #define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_MASK 0x00004000 93 94 #define REO_FLUSH_CACHE_2_RESERVED_2B_OFFSET 0x00000008 95 #define REO_FLUSH_CACHE_2_RESERVED_2B_LSB 15 96 #define REO_FLUSH_CACHE_2_RESERVED_2B_MASK 0xffff8000 97 98 #define REO_FLUSH_CACHE_3_RESERVED_3A_OFFSET 0x0000000c 99 #define REO_FLUSH_CACHE_3_RESERVED_3A_LSB 0 100 #define REO_FLUSH_CACHE_3_RESERVED_3A_MASK 0xffffffff 101 102 #define REO_FLUSH_CACHE_4_RESERVED_4A_OFFSET 0x00000010 103 #define REO_FLUSH_CACHE_4_RESERVED_4A_LSB 0 104 #define REO_FLUSH_CACHE_4_RESERVED_4A_MASK 0xffffffff 105 106 #define REO_FLUSH_CACHE_5_RESERVED_5A_OFFSET 0x00000014 107 #define REO_FLUSH_CACHE_5_RESERVED_5A_LSB 0 108 #define REO_FLUSH_CACHE_5_RESERVED_5A_MASK 0xffffffff 109 110 #define REO_FLUSH_CACHE_6_RESERVED_6A_OFFSET 0x00000018 111 #define REO_FLUSH_CACHE_6_RESERVED_6A_LSB 0 112 #define REO_FLUSH_CACHE_6_RESERVED_6A_MASK 0xffffffff 113 114 #define REO_FLUSH_CACHE_7_RESERVED_7A_OFFSET 0x0000001c 115 #define REO_FLUSH_CACHE_7_RESERVED_7A_LSB 0 116 #define REO_FLUSH_CACHE_7_RESERVED_7A_MASK 0xffffffff 117 118 #define REO_FLUSH_CACHE_8_RESERVED_8A_OFFSET 0x00000020 119 #define REO_FLUSH_CACHE_8_RESERVED_8A_LSB 0 120 #define REO_FLUSH_CACHE_8_RESERVED_8A_MASK 0xffffffff 121 122 #endif 123