1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _TX_FES_STATUS_PROT_H_ 27 #define _TX_FES_STATUS_PROT_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "phytx_abort_request_info.h" 32 #define NUM_OF_DWORDS_TX_FES_STATUS_PROT 14 33 34 #define NUM_OF_QWORDS_TX_FES_STATUS_PROT 7 35 36 37 struct tx_fes_status_prot { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 uint32_t success : 1, 40 phytx_pkt_end_info_valid : 1, 41 phytx_abort_request_info_valid : 1, 42 reserved_0 : 20, 43 pkt_type : 4, 44 dot11ax_su_extended : 1, 45 rate_mcs : 4; 46 uint32_t frame_type : 2, 47 frame_subtype : 4, 48 rx_pwr_mgmt : 1, 49 status : 1, 50 duration_field : 16, 51 reserved_1a : 2, 52 agc_cbw : 3, 53 service_cbw : 3; 54 uint32_t start_of_frame_timestamp_15_0 : 16, 55 start_of_frame_timestamp_31_16 : 16; 56 uint32_t end_of_frame_timestamp_15_0 : 16, 57 end_of_frame_timestamp_31_16 : 16; 58 uint32_t tx_group_delay : 12, 59 timing_status : 2, 60 dpdtrain_done : 1, 61 reserved_4 : 1, 62 transmit_delay : 16; 63 uint32_t tpc_dbg_info_cmn_15_0 : 16, 64 tpc_dbg_info_cmn_31_16 : 16; 65 uint32_t tpc_dbg_info_cmn_47_32 : 16, 66 tpc_dbg_info_chn1_15_0 : 16; 67 uint32_t tpc_dbg_info_chn1_31_16 : 16, 68 tpc_dbg_info_chn1_47_32 : 16; 69 uint32_t tpc_dbg_info_chn1_63_48 : 16, 70 tpc_dbg_info_chn1_79_64 : 16; 71 uint32_t tpc_dbg_info_chn2_15_0 : 16, 72 tpc_dbg_info_chn2_31_16 : 16; 73 uint32_t tpc_dbg_info_chn2_47_32 : 16, 74 tpc_dbg_info_chn2_63_48 : 16; 75 uint32_t tpc_dbg_info_chn2_79_64 : 16; 76 struct phytx_abort_request_info phytx_abort_request_info_details; 77 uint32_t phytx_tx_end_sw_info_15_0 : 16, 78 phytx_tx_end_sw_info_31_16 : 16; 79 uint32_t phytx_tx_end_sw_info_47_32 : 16, 80 phytx_tx_end_sw_info_63_48 : 16; 81 #else 82 uint32_t rate_mcs : 4, 83 dot11ax_su_extended : 1, 84 pkt_type : 4, 85 reserved_0 : 20, 86 phytx_abort_request_info_valid : 1, 87 phytx_pkt_end_info_valid : 1, 88 success : 1; 89 uint32_t service_cbw : 3, 90 agc_cbw : 3, 91 reserved_1a : 2, 92 duration_field : 16, 93 status : 1, 94 rx_pwr_mgmt : 1, 95 frame_subtype : 4, 96 frame_type : 2; 97 uint32_t start_of_frame_timestamp_31_16 : 16, 98 start_of_frame_timestamp_15_0 : 16; 99 uint32_t end_of_frame_timestamp_31_16 : 16, 100 end_of_frame_timestamp_15_0 : 16; 101 uint32_t transmit_delay : 16, 102 reserved_4 : 1, 103 dpdtrain_done : 1, 104 timing_status : 2, 105 tx_group_delay : 12; 106 uint32_t tpc_dbg_info_cmn_31_16 : 16, 107 tpc_dbg_info_cmn_15_0 : 16; 108 uint32_t tpc_dbg_info_chn1_15_0 : 16, 109 tpc_dbg_info_cmn_47_32 : 16; 110 uint32_t tpc_dbg_info_chn1_47_32 : 16, 111 tpc_dbg_info_chn1_31_16 : 16; 112 uint32_t tpc_dbg_info_chn1_79_64 : 16, 113 tpc_dbg_info_chn1_63_48 : 16; 114 uint32_t tpc_dbg_info_chn2_31_16 : 16, 115 tpc_dbg_info_chn2_15_0 : 16; 116 uint32_t tpc_dbg_info_chn2_63_48 : 16, 117 tpc_dbg_info_chn2_47_32 : 16; 118 struct phytx_abort_request_info phytx_abort_request_info_details; 119 uint16_t tpc_dbg_info_chn2_79_64 : 16; 120 uint32_t phytx_tx_end_sw_info_31_16 : 16, 121 phytx_tx_end_sw_info_15_0 : 16; 122 uint32_t phytx_tx_end_sw_info_63_48 : 16, 123 phytx_tx_end_sw_info_47_32 : 16; 124 #endif 125 }; 126 127 128 129 130 #define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x0000000000000000 131 #define TX_FES_STATUS_PROT_SUCCESS_LSB 0 132 #define TX_FES_STATUS_PROT_SUCCESS_MSB 0 133 #define TX_FES_STATUS_PROT_SUCCESS_MASK 0x0000000000000001 134 135 136 137 138 #define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 139 #define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1 140 #define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1 141 #define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000002 142 143 144 145 146 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 147 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2 148 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2 149 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000004 150 151 152 153 154 #define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x0000000000000000 155 #define TX_FES_STATUS_PROT_RESERVED_0_LSB 3 156 #define TX_FES_STATUS_PROT_RESERVED_0_MSB 22 157 #define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x00000000007ffff8 158 159 160 161 162 #define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x0000000000000000 163 #define TX_FES_STATUS_PROT_PKT_TYPE_LSB 23 164 #define TX_FES_STATUS_PROT_PKT_TYPE_MSB 26 165 #define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x0000000007800000 166 167 168 169 170 #define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 171 #define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 27 172 #define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 27 173 #define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x0000000008000000 174 175 176 177 178 #define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x0000000000000000 179 #define TX_FES_STATUS_PROT_RATE_MCS_LSB 28 180 #define TX_FES_STATUS_PROT_RATE_MCS_MSB 31 181 #define TX_FES_STATUS_PROT_RATE_MCS_MASK 0x00000000f0000000 182 183 184 185 186 #define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x0000000000000000 187 #define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 32 188 #define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 33 189 #define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x0000000300000000 190 191 192 193 194 #define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x0000000000000000 195 #define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 34 196 #define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 37 197 #define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c00000000 198 199 200 201 202 #define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x0000000000000000 203 #define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 38 204 #define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 38 205 #define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x0000004000000000 206 207 208 209 210 #define TX_FES_STATUS_PROT_STATUS_OFFSET 0x0000000000000000 211 #define TX_FES_STATUS_PROT_STATUS_LSB 39 212 #define TX_FES_STATUS_PROT_STATUS_MSB 39 213 #define TX_FES_STATUS_PROT_STATUS_MASK 0x0000008000000000 214 215 216 217 218 #define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x0000000000000000 219 #define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 40 220 #define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 55 221 #define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff0000000000 222 223 224 225 226 #define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x0000000000000000 227 #define TX_FES_STATUS_PROT_RESERVED_1A_LSB 56 228 #define TX_FES_STATUS_PROT_RESERVED_1A_MSB 57 229 #define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x0300000000000000 230 231 232 233 234 #define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x0000000000000000 235 #define TX_FES_STATUS_PROT_AGC_CBW_LSB 58 236 #define TX_FES_STATUS_PROT_AGC_CBW_MSB 60 237 #define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c00000000000000 238 239 240 241 242 #define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x0000000000000000 243 #define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 61 244 #define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 63 245 #define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe000000000000000 246 247 248 249 250 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 251 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 252 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 253 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff 254 255 256 257 258 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 259 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_LSB 16 260 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MSB 31 261 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 262 263 264 265 266 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 267 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_LSB 32 268 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MSB 47 269 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 270 271 272 273 274 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 275 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_LSB 48 276 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MSB 63 277 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 278 279 280 281 282 #define TX_FES_STATUS_PROT_TX_GROUP_DELAY_OFFSET 0x0000000000000010 283 #define TX_FES_STATUS_PROT_TX_GROUP_DELAY_LSB 0 284 #define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MSB 11 285 #define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MASK 0x0000000000000fff 286 287 288 289 290 #define TX_FES_STATUS_PROT_TIMING_STATUS_OFFSET 0x0000000000000010 291 #define TX_FES_STATUS_PROT_TIMING_STATUS_LSB 12 292 #define TX_FES_STATUS_PROT_TIMING_STATUS_MSB 13 293 #define TX_FES_STATUS_PROT_TIMING_STATUS_MASK 0x0000000000003000 294 295 296 297 298 #define TX_FES_STATUS_PROT_DPDTRAIN_DONE_OFFSET 0x0000000000000010 299 #define TX_FES_STATUS_PROT_DPDTRAIN_DONE_LSB 14 300 #define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MSB 14 301 #define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MASK 0x0000000000004000 302 303 304 305 306 #define TX_FES_STATUS_PROT_RESERVED_4_OFFSET 0x0000000000000010 307 #define TX_FES_STATUS_PROT_RESERVED_4_LSB 15 308 #define TX_FES_STATUS_PROT_RESERVED_4_MSB 15 309 #define TX_FES_STATUS_PROT_RESERVED_4_MASK 0x0000000000008000 310 311 312 313 314 #define TX_FES_STATUS_PROT_TRANSMIT_DELAY_OFFSET 0x0000000000000010 315 #define TX_FES_STATUS_PROT_TRANSMIT_DELAY_LSB 16 316 #define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MSB 31 317 #define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MASK 0x00000000ffff0000 318 319 320 321 322 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010 323 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_LSB 32 324 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MSB 47 325 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff00000000 326 327 328 329 330 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000010 331 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_LSB 48 332 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MSB 63 333 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MASK 0xffff000000000000 334 335 336 337 338 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_OFFSET 0x0000000000000018 339 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_LSB 0 340 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MSB 15 341 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MASK 0x000000000000ffff 342 343 344 345 346 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018 347 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_LSB 16 348 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MSB 31 349 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MASK 0x00000000ffff0000 350 351 352 353 354 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018 355 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_LSB 32 356 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MSB 47 357 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff00000000 358 359 360 361 362 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000018 363 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_LSB 48 364 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MSB 63 365 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MASK 0xffff000000000000 366 367 368 369 370 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020 371 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_LSB 0 372 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MSB 15 373 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MASK 0x000000000000ffff 374 375 376 377 378 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020 379 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_LSB 16 380 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MSB 31 381 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MASK 0x00000000ffff0000 382 383 384 385 386 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020 387 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_LSB 32 388 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MSB 47 389 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff00000000 390 391 392 393 394 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000020 395 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_LSB 48 396 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MSB 63 397 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MASK 0xffff000000000000 398 399 400 401 402 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028 403 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_LSB 0 404 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MSB 15 405 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MASK 0x000000000000ffff 406 407 408 409 410 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028 411 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_LSB 16 412 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MSB 31 413 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MASK 0x00000000ffff0000 414 415 416 417 418 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028 419 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_LSB 32 420 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MSB 47 421 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff00000000 422 423 424 425 426 427 428 429 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000028 430 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 48 431 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 55 432 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x00ff000000000000 433 434 435 436 437 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000028 438 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 56 439 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 61 440 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x3f00000000000000 441 442 443 444 445 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000028 446 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 62 447 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 63 448 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0xc000000000000000 449 450 451 452 453 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030 454 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_LSB 0 455 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MSB 15 456 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff 457 458 459 460 461 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030 462 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_LSB 16 463 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MSB 31 464 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 465 466 467 468 469 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030 470 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_LSB 32 471 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MSB 47 472 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 473 474 475 476 477 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030 478 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_LSB 48 479 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MSB 63 480 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 481 482 483 484 #endif 485