1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _TCL_ENTRANCE_FROM_PPE_RING_H_ 27 #define _TCL_ENTRANCE_FROM_PPE_RING_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_TCL_ENTRANCE_FROM_PPE_RING 8 32 33 34 struct tcl_entrance_from_ppe_ring { 35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 36 uint32_t buffer_addr_lo : 32; 37 uint32_t buffer_addr_hi : 8, 38 drop_prec : 2, 39 fake_mac_header : 1, 40 known_ind : 1, 41 cpu_code_valid : 1, 42 tunnel_term_ind : 1, 43 tunnel_type : 1, 44 wifi_qos_flag : 1, 45 service_code : 9, 46 reserved_1b : 1, 47 int_pri : 4, 48 more : 1, 49 reserved_1a : 1; 50 uint32_t opaque_lo : 32; 51 uint32_t opaque_hi : 32; 52 uint32_t src_info : 16, 53 dst_info : 16; 54 uint32_t data_length : 18, 55 pool_id : 6, 56 wifi_qos : 8; 57 uint32_t data_offset : 12, 58 l4_csum_status : 1, 59 l3_csum_status : 1, 60 hash_flag : 2, 61 hash_value : 16; 62 uint32_t dscp : 8, 63 valid_toggle : 1, 64 pppoe_flag : 1, 65 svlan_flag : 1, 66 cvlan_flag : 1, 67 pid : 4, 68 l3_offset : 8, 69 l4_offset : 8; 70 #else 71 uint32_t buffer_addr_lo : 32; 72 uint32_t reserved_1a : 1, 73 more : 1, 74 int_pri : 4, 75 reserved_1b : 1, 76 service_code : 9, 77 wifi_qos_flag : 1, 78 tunnel_type : 1, 79 tunnel_term_ind : 1, 80 cpu_code_valid : 1, 81 known_ind : 1, 82 fake_mac_header : 1, 83 drop_prec : 2, 84 buffer_addr_hi : 8; 85 uint32_t opaque_lo : 32; 86 uint32_t opaque_hi : 32; 87 uint32_t dst_info : 16, 88 src_info : 16; 89 uint32_t wifi_qos : 8, 90 pool_id : 6, 91 data_length : 18; 92 uint32_t hash_value : 16, 93 hash_flag : 2, 94 l3_csum_status : 1, 95 l4_csum_status : 1, 96 data_offset : 12; 97 uint32_t l4_offset : 8, 98 l3_offset : 8, 99 pid : 4, 100 cvlan_flag : 1, 101 svlan_flag : 1, 102 pppoe_flag : 1, 103 valid_toggle : 1, 104 dscp : 8; 105 #endif 106 }; 107 108 109 110 111 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_OFFSET 0x00000000 112 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_LSB 0 113 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_MSB 31 114 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_MASK 0xffffffff 115 116 117 118 119 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_OFFSET 0x00000004 120 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_LSB 0 121 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_MSB 7 122 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_MASK 0x000000ff 123 124 125 126 127 #define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_OFFSET 0x00000004 128 #define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_LSB 8 129 #define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_MSB 9 130 #define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_MASK 0x00000300 131 132 133 134 135 #define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_OFFSET 0x00000004 136 #define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_LSB 10 137 #define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_MSB 10 138 #define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_MASK 0x00000400 139 140 141 142 143 #define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_OFFSET 0x00000004 144 #define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_LSB 11 145 #define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_MSB 11 146 #define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_MASK 0x00000800 147 148 149 150 151 #define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_OFFSET 0x00000004 152 #define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_LSB 12 153 #define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_MSB 12 154 #define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_MASK 0x00001000 155 156 157 158 159 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_OFFSET 0x00000004 160 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_LSB 13 161 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_MSB 13 162 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_MASK 0x00002000 163 164 165 166 167 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_OFFSET 0x00000004 168 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_LSB 14 169 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_MSB 14 170 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_MASK 0x00004000 171 172 173 174 175 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_OFFSET 0x00000004 176 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_LSB 15 177 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_MSB 15 178 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_MASK 0x00008000 179 180 181 182 183 #define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_OFFSET 0x00000004 184 #define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_LSB 16 185 #define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_MSB 24 186 #define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_MASK 0x01ff0000 187 188 189 190 191 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_OFFSET 0x00000004 192 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_LSB 25 193 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_MSB 25 194 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_MASK 0x02000000 195 196 197 198 199 #define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_OFFSET 0x00000004 200 #define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_LSB 26 201 #define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_MSB 29 202 #define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_MASK 0x3c000000 203 204 205 206 207 #define TCL_ENTRANCE_FROM_PPE_RING_MORE_OFFSET 0x00000004 208 #define TCL_ENTRANCE_FROM_PPE_RING_MORE_LSB 30 209 #define TCL_ENTRANCE_FROM_PPE_RING_MORE_MSB 30 210 #define TCL_ENTRANCE_FROM_PPE_RING_MORE_MASK 0x40000000 211 212 213 214 215 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_OFFSET 0x00000004 216 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_LSB 31 217 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_MSB 31 218 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_MASK 0x80000000 219 220 221 222 223 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_OFFSET 0x00000008 224 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_LSB 0 225 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_MSB 31 226 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_MASK 0xffffffff 227 228 229 230 231 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_OFFSET 0x0000000c 232 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_LSB 0 233 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_MSB 31 234 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_MASK 0xffffffff 235 236 237 238 239 #define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_OFFSET 0x00000010 240 #define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_LSB 0 241 #define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_MSB 15 242 #define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_MASK 0x0000ffff 243 244 245 246 247 #define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_OFFSET 0x00000010 248 #define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_LSB 16 249 #define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_MSB 31 250 #define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_MASK 0xffff0000 251 252 253 254 255 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_OFFSET 0x00000014 256 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_LSB 0 257 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_MSB 17 258 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_MASK 0x0003ffff 259 260 261 262 263 #define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_OFFSET 0x00000014 264 #define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_LSB 18 265 #define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_MSB 23 266 #define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_MASK 0x00fc0000 267 268 269 270 271 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_OFFSET 0x00000014 272 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_LSB 24 273 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_MSB 31 274 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_MASK 0xff000000 275 276 277 278 279 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_OFFSET 0x00000018 280 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_LSB 0 281 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_MSB 11 282 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_MASK 0x00000fff 283 284 285 286 287 #define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_OFFSET 0x00000018 288 #define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_LSB 12 289 #define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_MSB 12 290 #define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_MASK 0x00001000 291 292 293 294 295 #define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_OFFSET 0x00000018 296 #define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_LSB 13 297 #define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_MSB 13 298 #define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_MASK 0x00002000 299 300 301 302 303 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_OFFSET 0x00000018 304 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_LSB 14 305 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_MSB 15 306 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_MASK 0x0000c000 307 308 309 310 311 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_OFFSET 0x00000018 312 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_LSB 16 313 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_MSB 31 314 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_MASK 0xffff0000 315 316 317 318 319 #define TCL_ENTRANCE_FROM_PPE_RING_DSCP_OFFSET 0x0000001c 320 #define TCL_ENTRANCE_FROM_PPE_RING_DSCP_LSB 0 321 #define TCL_ENTRANCE_FROM_PPE_RING_DSCP_MSB 7 322 #define TCL_ENTRANCE_FROM_PPE_RING_DSCP_MASK 0x000000ff 323 324 325 326 327 #define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_OFFSET 0x0000001c 328 #define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_LSB 8 329 #define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_MSB 8 330 #define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_MASK 0x00000100 331 332 333 334 335 #define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_OFFSET 0x0000001c 336 #define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_LSB 9 337 #define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_MSB 9 338 #define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_MASK 0x00000200 339 340 341 342 343 #define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_OFFSET 0x0000001c 344 #define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_LSB 10 345 #define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_MSB 10 346 #define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_MASK 0x00000400 347 348 349 350 351 #define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_OFFSET 0x0000001c 352 #define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_LSB 11 353 #define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_MSB 11 354 #define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_MASK 0x00000800 355 356 357 358 359 #define TCL_ENTRANCE_FROM_PPE_RING_PID_OFFSET 0x0000001c 360 #define TCL_ENTRANCE_FROM_PPE_RING_PID_LSB 12 361 #define TCL_ENTRANCE_FROM_PPE_RING_PID_MSB 15 362 #define TCL_ENTRANCE_FROM_PPE_RING_PID_MASK 0x0000f000 363 364 365 366 367 #define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_OFFSET 0x0000001c 368 #define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_LSB 16 369 #define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_MSB 23 370 #define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_MASK 0x00ff0000 371 372 373 374 375 #define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_OFFSET 0x0000001c 376 #define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_LSB 24 377 #define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_MSB 31 378 #define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_MASK 0xff000000 379 380 381 382 #endif 383