1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _PDG_RESPONSE_RATE_SETTING_H_ 27 #define _PDG_RESPONSE_RATE_SETTING_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "mlo_sta_id_details.h" 32 #define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7 33 34 35 struct pdg_response_rate_setting { 36 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 37 uint32_t reserved_0a : 1, 38 tx_antenna_sector_ctrl : 24, 39 pkt_type : 4, 40 smoothing : 1, 41 ldpc : 1, 42 stbc : 1; 43 uint32_t alt_tx_pwr : 8, 44 alt_min_tx_pwr : 8, 45 alt_nss : 3, 46 alt_tx_chain_mask : 8, 47 alt_bw : 3, 48 stf_ltf_3db_boost : 1, 49 force_extra_symbol : 1; 50 uint32_t alt_rate_mcs : 4, 51 nss : 3, 52 dpd_enable : 1, 53 tx_pwr : 8, 54 min_tx_pwr : 8, 55 tx_chain_mask : 8; 56 uint32_t reserved_3a : 8, 57 sgi : 2, 58 rate_mcs : 4, 59 reserved_3b : 2, 60 tx_pwr_1 : 8, 61 alt_tx_pwr_1 : 8; 62 uint32_t aggregation : 1, 63 dot11ax_bss_color_id : 6, 64 dot11ax_spatial_reuse : 4, 65 dot11ax_cp_ltf_size : 2, 66 dot11ax_dcm : 1, 67 dot11ax_doppler_indication : 1, 68 dot11ax_su_extended : 1, 69 dot11ax_min_packet_extension : 2, 70 dot11ax_pe_nss : 3, 71 dot11ax_pe_content : 1, 72 dot11ax_pe_ltf_size : 2, 73 dot11ax_chain_csd_en : 1, 74 dot11ax_pe_chain_csd_en : 1, 75 dot11ax_dl_ul_flag : 1, 76 reserved_4a : 5; 77 uint32_t dot11ax_ext_ru_start_index : 4, 78 dot11ax_ext_ru_size : 4, 79 eht_duplicate_mode : 2, 80 he_sigb_dcm : 1, 81 he_sigb_0_mcs : 3, 82 num_he_sigb_sym : 5, 83 required_response_time_source : 1, 84 reserved_5a : 6, 85 u_sig_puncture_pattern_encoding : 6; 86 struct mlo_sta_id_details mlo_sta_id_details_rx; 87 uint16_t required_response_time : 12, 88 dot11be_params_placeholder : 4; 89 #else 90 uint32_t stbc : 1, 91 ldpc : 1, 92 smoothing : 1, 93 pkt_type : 4, 94 tx_antenna_sector_ctrl : 24, 95 reserved_0a : 1; 96 uint32_t force_extra_symbol : 1, 97 stf_ltf_3db_boost : 1, 98 alt_bw : 3, 99 alt_tx_chain_mask : 8, 100 alt_nss : 3, 101 alt_min_tx_pwr : 8, 102 alt_tx_pwr : 8; 103 uint32_t tx_chain_mask : 8, 104 min_tx_pwr : 8, 105 tx_pwr : 8, 106 dpd_enable : 1, 107 nss : 3, 108 alt_rate_mcs : 4; 109 uint32_t alt_tx_pwr_1 : 8, 110 tx_pwr_1 : 8, 111 reserved_3b : 2, 112 rate_mcs : 4, 113 sgi : 2, 114 reserved_3a : 8; 115 uint32_t reserved_4a : 5, 116 dot11ax_dl_ul_flag : 1, 117 dot11ax_pe_chain_csd_en : 1, 118 dot11ax_chain_csd_en : 1, 119 dot11ax_pe_ltf_size : 2, 120 dot11ax_pe_content : 1, 121 dot11ax_pe_nss : 3, 122 dot11ax_min_packet_extension : 2, 123 dot11ax_su_extended : 1, 124 dot11ax_doppler_indication : 1, 125 dot11ax_dcm : 1, 126 dot11ax_cp_ltf_size : 2, 127 dot11ax_spatial_reuse : 4, 128 dot11ax_bss_color_id : 6, 129 aggregation : 1; 130 uint32_t u_sig_puncture_pattern_encoding : 6, 131 reserved_5a : 6, 132 required_response_time_source : 1, 133 num_he_sigb_sym : 5, 134 he_sigb_0_mcs : 3, 135 he_sigb_dcm : 1, 136 eht_duplicate_mode : 2, 137 dot11ax_ext_ru_size : 4, 138 dot11ax_ext_ru_start_index : 4; 139 uint32_t dot11be_params_placeholder : 4, 140 required_response_time : 12; 141 struct mlo_sta_id_details mlo_sta_id_details_rx; 142 #endif 143 }; 144 145 146 147 148 #define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET 0x00000000 149 #define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB 0 150 #define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB 0 151 #define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK 0x00000001 152 153 154 155 156 #define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000 157 #define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB 1 158 #define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB 24 159 #define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe 160 161 162 163 164 #define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET 0x00000000 165 #define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB 25 166 #define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB 28 167 #define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK 0x1e000000 168 169 170 171 172 #define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET 0x00000000 173 #define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB 29 174 #define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB 29 175 #define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK 0x20000000 176 177 178 179 180 #define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET 0x00000000 181 #define PDG_RESPONSE_RATE_SETTING_LDPC_LSB 30 182 #define PDG_RESPONSE_RATE_SETTING_LDPC_MSB 30 183 #define PDG_RESPONSE_RATE_SETTING_LDPC_MASK 0x40000000 184 185 186 187 188 #define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET 0x00000000 189 #define PDG_RESPONSE_RATE_SETTING_STBC_LSB 31 190 #define PDG_RESPONSE_RATE_SETTING_STBC_MSB 31 191 #define PDG_RESPONSE_RATE_SETTING_STBC_MASK 0x80000000 192 193 194 195 196 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET 0x00000004 197 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB 0 198 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB 7 199 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK 0x000000ff 200 201 202 203 204 #define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET 0x00000004 205 #define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB 8 206 #define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB 15 207 #define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK 0x0000ff00 208 209 210 211 212 #define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET 0x00000004 213 #define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB 16 214 #define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB 18 215 #define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK 0x00070000 216 217 218 219 220 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 221 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB 19 222 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB 26 223 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK 0x07f80000 224 225 226 227 228 #define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET 0x00000004 229 #define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB 27 230 #define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB 29 231 #define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK 0x38000000 232 233 234 235 236 #define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET 0x00000004 237 #define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB 30 238 #define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB 30 239 #define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK 0x40000000 240 241 242 243 244 #define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004 245 #define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB 31 246 #define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB 31 247 #define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK 0x80000000 248 249 250 251 252 #define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET 0x00000008 253 #define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB 0 254 #define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB 3 255 #define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK 0x0000000f 256 257 258 259 260 #define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET 0x00000008 261 #define PDG_RESPONSE_RATE_SETTING_NSS_LSB 4 262 #define PDG_RESPONSE_RATE_SETTING_NSS_MSB 6 263 #define PDG_RESPONSE_RATE_SETTING_NSS_MASK 0x00000070 264 265 266 267 268 #define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET 0x00000008 269 #define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB 7 270 #define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB 7 271 #define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK 0x00000080 272 273 274 275 276 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET 0x00000008 277 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB 8 278 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB 15 279 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK 0x0000ff00 280 281 282 283 284 #define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET 0x00000008 285 #define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB 16 286 #define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB 23 287 #define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK 0x00ff0000 288 289 290 291 292 #define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET 0x00000008 293 #define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB 24 294 #define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB 31 295 #define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK 0xff000000 296 297 298 299 300 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET 0x0000000c 301 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB 0 302 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB 7 303 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK 0x000000ff 304 305 306 307 308 #define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET 0x0000000c 309 #define PDG_RESPONSE_RATE_SETTING_SGI_LSB 8 310 #define PDG_RESPONSE_RATE_SETTING_SGI_MSB 9 311 #define PDG_RESPONSE_RATE_SETTING_SGI_MASK 0x00000300 312 313 314 315 316 #define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET 0x0000000c 317 #define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB 10 318 #define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB 13 319 #define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK 0x00003c00 320 321 322 323 324 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_OFFSET 0x0000000c 325 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_LSB 14 326 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MSB 15 327 #define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MASK 0x0000c000 328 329 330 331 332 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET 0x0000000c 333 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB 16 334 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB 23 335 #define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK 0x00ff0000 336 337 338 339 340 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET 0x0000000c 341 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB 24 342 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB 31 343 #define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK 0xff000000 344 345 346 347 348 #define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET 0x00000010 349 #define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB 0 350 #define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB 0 351 #define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK 0x00000001 352 353 354 355 356 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010 357 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB 1 358 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB 6 359 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e 360 361 362 363 364 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010 365 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB 7 366 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB 10 367 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 368 369 370 371 372 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010 373 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB 11 374 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB 12 375 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 376 377 378 379 380 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET 0x00000010 381 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB 13 382 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB 13 383 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK 0x00002000 384 385 386 387 388 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010 389 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB 14 390 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB 14 391 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 392 393 394 395 396 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET 0x00000010 397 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB 15 398 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB 15 399 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK 0x00008000 400 401 402 403 404 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010 405 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 406 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 407 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 408 409 410 411 412 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET 0x00000010 413 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB 18 414 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB 20 415 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK 0x001c0000 416 417 418 419 420 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET 0x00000010 421 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB 21 422 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB 21 423 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK 0x00200000 424 425 426 427 428 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010 429 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB 22 430 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB 23 431 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 432 433 434 435 436 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010 437 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB 24 438 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB 24 439 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 440 441 442 443 444 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010 445 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 446 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 447 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 448 449 450 451 452 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010 453 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB 26 454 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB 26 455 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK 0x04000000 456 457 458 459 460 #define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET 0x00000010 461 #define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB 27 462 #define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB 31 463 #define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK 0xf8000000 464 465 466 467 468 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014 469 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB 0 470 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB 3 471 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f 472 473 474 475 476 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014 477 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB 4 478 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB 7 479 #define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 480 481 482 483 484 #define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET 0x00000014 485 #define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB 8 486 #define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB 9 487 #define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK 0x00000300 488 489 490 491 492 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET 0x00000014 493 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB 10 494 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB 10 495 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK 0x00000400 496 497 498 499 500 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET 0x00000014 501 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB 11 502 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB 13 503 #define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK 0x00003800 504 505 506 507 508 #define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET 0x00000014 509 #define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB 14 510 #define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB 18 511 #define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK 0x0007c000 512 513 514 515 516 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014 517 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 518 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 519 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 520 521 522 523 524 #define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET 0x00000014 525 #define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB 20 526 #define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB 25 527 #define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK 0x03f00000 528 529 530 531 532 #define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014 533 #define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 534 #define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 535 #define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 536 537 538 539 540 541 542 543 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018 544 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 545 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 546 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff 547 548 549 550 551 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018 552 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 553 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 554 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 555 556 557 558 559 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018 560 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 561 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 562 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 563 564 565 566 567 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018 568 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 569 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 570 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 571 572 573 574 575 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018 576 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 577 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 578 #define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 579 580 581 582 583 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018 584 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB 16 585 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB 27 586 #define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 587 588 589 590 591 #define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018 592 #define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 593 #define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 594 #define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 595 596 597 598 #endif 599