1 
2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 
19 
20 
21 
22 
23 
24 
25 
26 #ifndef _PDG_RESPONSE_H_
27 #define _PDG_RESPONSE_H_
28 #if !defined(__ASSEMBLER__)
29 #endif
30 
31 #include "pdg_response_rate_setting.h"
32 #define NUM_OF_DWORDS_PDG_RESPONSE 12
33 
34 #define NUM_OF_QWORDS_PDG_RESPONSE 6
35 
36 
37 struct pdg_response {
38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
39              struct   pdg_response_rate_setting                                 hw_response_rate_info;
40              uint32_t hw_response_tx_duration                                 : 16,
41                       rx_duration_field                                       : 16;
42              uint32_t punctured_response_transmission                         :  1,
43                       cca_subband_channel_bonding_mask                        : 16,
44                       scrambler_seed_override                                 :  2,
45                       response_density_valid                                  :  1,
46                       response_density                                        :  5,
47                       more_data                                               :  1,
48                       duration_indication                                     :  1,
49                       relayed_frame                                           :  1,
50                       address_indicator                                       :  1,
51                       bandwidth                                               :  3;
52              uint32_t ack_id                                                  : 16,
53                       block_ack_bitmap                                        : 16;
54              uint32_t response_frame_type                                     :  4,
55                       ack_id_ext                                              : 10,
56                       ftm_en                                                  :  1,
57                       group_id                                                :  6,
58                       sta_partial_aid                                         : 11;
59              uint32_t ndp_ba_start_seq_ctrl                                   : 12,
60                       active_channel                                          :  3,
61                       txop_duration_all_ones                                  :  1,
62                       frame_length                                            : 16;
63 #else
64              struct   pdg_response_rate_setting                                 hw_response_rate_info;
65              uint32_t rx_duration_field                                       : 16,
66                       hw_response_tx_duration                                 : 16;
67              uint32_t bandwidth                                               :  3,
68                       address_indicator                                       :  1,
69                       relayed_frame                                           :  1,
70                       duration_indication                                     :  1,
71                       more_data                                               :  1,
72                       response_density                                        :  5,
73                       response_density_valid                                  :  1,
74                       scrambler_seed_override                                 :  2,
75                       cca_subband_channel_bonding_mask                        : 16,
76                       punctured_response_transmission                         :  1;
77              uint32_t block_ack_bitmap                                        : 16,
78                       ack_id                                                  : 16;
79              uint32_t sta_partial_aid                                         : 11,
80                       group_id                                                :  6,
81                       ftm_en                                                  :  1,
82                       ack_id_ext                                              : 10,
83                       response_frame_type                                     :  4;
84              uint32_t frame_length                                            : 16,
85                       txop_duration_all_ones                                  :  1,
86                       active_channel                                          :  3,
87                       ndp_ba_start_seq_ctrl                                   : 12;
88 #endif
89 };
90 
91 
92 
93 
94 
95 
96 
97 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET                       0x0000000000000000
98 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB                          0
99 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB                          0
100 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK                         0x0000000000000001
101 
102 
103 
104 
105 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET            0x0000000000000000
106 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB               1
107 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB               24
108 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK              0x0000000001fffffe
109 
110 
111 
112 
113 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET                          0x0000000000000000
114 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB                             25
115 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB                             28
116 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK                            0x000000001e000000
117 
118 
119 
120 
121 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET                         0x0000000000000000
122 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB                            29
123 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB                            29
124 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK                           0x0000000020000000
125 
126 
127 
128 
129 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET                              0x0000000000000000
130 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB                                 30
131 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB                                 30
132 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK                                0x0000000040000000
133 
134 
135 
136 
137 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET                              0x0000000000000000
138 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB                                 31
139 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB                                 31
140 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK                                0x0000000080000000
141 
142 
143 
144 
145 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET                        0x0000000000000000
146 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB                           32
147 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB                           39
148 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK                          0x000000ff00000000
149 
150 
151 
152 
153 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET                    0x0000000000000000
154 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB                       40
155 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB                       47
156 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK                      0x0000ff0000000000
157 
158 
159 
160 
161 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET                           0x0000000000000000
162 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB                              48
163 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB                              50
164 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK                             0x0007000000000000
165 
166 
167 
168 
169 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET                 0x0000000000000000
170 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB                    51
171 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB                    58
172 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK                   0x07f8000000000000
173 
174 
175 
176 
177 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET                            0x0000000000000000
178 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB                               59
179 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB                               61
180 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK                              0x3800000000000000
181 
182 
183 
184 
185 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET                 0x0000000000000000
186 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB                    62
187 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB                    62
188 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK                   0x4000000000000000
189 
190 
191 
192 
193 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET                0x0000000000000000
194 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB                   63
195 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB                   63
196 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK                  0x8000000000000000
197 
198 
199 
200 
201 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET                      0x0000000000000008
202 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB                         0
203 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB                         3
204 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK                        0x000000000000000f
205 
206 
207 
208 
209 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET                               0x0000000000000008
210 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB                                  4
211 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB                                  6
212 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK                                 0x0000000000000070
213 
214 
215 
216 
217 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET                        0x0000000000000008
218 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB                           7
219 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB                           7
220 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK                          0x0000000000000080
221 
222 
223 
224 
225 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET                            0x0000000000000008
226 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB                               8
227 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB                               15
228 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK                              0x000000000000ff00
229 
230 
231 
232 
233 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET                        0x0000000000000008
234 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB                           16
235 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB                           23
236 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK                          0x0000000000ff0000
237 
238 
239 
240 
241 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET                     0x0000000000000008
242 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB                        24
243 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB                        31
244 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK                       0x00000000ff000000
245 
246 
247 
248 
249 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET                       0x0000000000000008
250 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB                          32
251 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB                          39
252 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK                         0x000000ff00000000
253 
254 
255 
256 
257 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET                               0x0000000000000008
258 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB                                  40
259 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB                                  41
260 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK                                 0x0000030000000000
261 
262 
263 
264 
265 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET                          0x0000000000000008
266 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB                             42
267 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB                             45
268 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK                            0x00003c0000000000
269 
270 
271 
272 
273 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_OFFSET                       0x0000000000000008
274 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_LSB                          46
275 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MSB                          47
276 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MASK                         0x0000c00000000000
277 
278 
279 
280 
281 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET                          0x0000000000000008
282 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB                             48
283 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB                             55
284 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK                            0x00ff000000000000
285 
286 
287 
288 
289 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET                      0x0000000000000008
290 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB                         56
291 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB                         63
292 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK                        0xff00000000000000
293 
294 
295 
296 
297 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET                       0x0000000000000010
298 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB                          0
299 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB                          0
300 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK                         0x0000000000000001
301 
302 
303 
304 
305 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET              0x0000000000000010
306 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB                 1
307 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB                 6
308 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK                0x000000000000007e
309 
310 
311 
312 
313 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET             0x0000000000000010
314 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB                7
315 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB                10
316 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK               0x0000000000000780
317 
318 
319 
320 
321 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET               0x0000000000000010
322 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB                  11
323 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB                  12
324 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK                 0x0000000000001800
325 
326 
327 
328 
329 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET                       0x0000000000000010
330 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB                          13
331 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB                          13
332 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK                         0x0000000000002000
333 
334 
335 
336 
337 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET        0x0000000000000010
338 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB           14
339 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB           14
340 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK          0x0000000000004000
341 
342 
343 
344 
345 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET               0x0000000000000010
346 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB                  15
347 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB                  15
348 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK                 0x0000000000008000
349 
350 
351 
352 
353 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET      0x0000000000000010
354 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB         16
355 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB         17
356 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK        0x0000000000030000
357 
358 
359 
360 
361 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET                    0x0000000000000010
362 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB                       18
363 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB                       20
364 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK                      0x00000000001c0000
365 
366 
367 
368 
369 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET                0x0000000000000010
370 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB                   21
371 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB                   21
372 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK                  0x0000000000200000
373 
374 
375 
376 
377 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET               0x0000000000000010
378 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB                  22
379 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB                  23
380 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK                 0x0000000000c00000
381 
382 
383 
384 
385 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET              0x0000000000000010
386 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB                 24
387 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB                 24
388 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK                0x0000000001000000
389 
390 
391 
392 
393 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET           0x0000000000000010
394 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB              25
395 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB              25
396 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK             0x0000000002000000
397 
398 
399 
400 
401 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET                0x0000000000000010
402 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB                   26
403 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB                   26
404 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK                  0x0000000004000000
405 
406 
407 
408 
409 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET                       0x0000000000000010
410 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB                          27
411 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB                          31
412 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK                         0x00000000f8000000
413 
414 
415 
416 
417 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET        0x0000000000000010
418 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB           32
419 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB           35
420 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK          0x0000000f00000000
421 
422 
423 
424 
425 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET               0x0000000000000010
426 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB                  36
427 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB                  39
428 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK                 0x000000f000000000
429 
430 
431 
432 
433 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET                0x0000000000000010
434 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB                   40
435 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB                   41
436 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK                  0x0000030000000000
437 
438 
439 
440 
441 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET                       0x0000000000000010
442 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB                          42
443 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB                          42
444 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK                         0x0000040000000000
445 
446 
447 
448 
449 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET                     0x0000000000000010
450 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB                        43
451 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB                        45
452 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK                       0x0000380000000000
453 
454 
455 
456 
457 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET                   0x0000000000000010
458 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB                      46
459 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB                      50
460 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK                     0x0007c00000000000
461 
462 
463 
464 
465 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET     0x0000000000000010
466 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB        51
467 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB        51
468 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK       0x0008000000000000
469 
470 
471 
472 
473 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET                       0x0000000000000010
474 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB                          52
475 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB                          57
476 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK                         0x03f0000000000000
477 
478 
479 
480 
481 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET   0x0000000000000010
482 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB      58
483 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB      63
484 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK     0xfc00000000000000
485 
486 
487 
488 
489 
490 
491 
492 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000018
493 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
494 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
495 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff
496 
497 
498 
499 
500 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000018
501 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
502 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
503 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400
504 
505 
506 
507 
508 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000018
509 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
510 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
511 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800
512 
513 
514 
515 
516 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000018
517 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
518 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
519 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000
520 
521 
522 
523 
524 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000018
525 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB    13
526 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB    15
527 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK   0x000000000000e000
528 
529 
530 
531 
532 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET            0x0000000000000018
533 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB               16
534 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB               27
535 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK              0x000000000fff0000
536 
537 
538 
539 
540 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET        0x0000000000000018
541 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB           28
542 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB           31
543 #define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK          0x00000000f0000000
544 
545 
546 
547 
548 #define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET                                 0x0000000000000018
549 #define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB                                    32
550 #define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB                                    47
551 #define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK                                   0x0000ffff00000000
552 
553 
554 
555 
556 #define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET                                       0x0000000000000018
557 #define PDG_RESPONSE_RX_DURATION_FIELD_LSB                                          48
558 #define PDG_RESPONSE_RX_DURATION_FIELD_MSB                                          63
559 #define PDG_RESPONSE_RX_DURATION_FIELD_MASK                                         0xffff000000000000
560 
561 
562 
563 
564 #define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET                         0x0000000000000020
565 #define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB                            0
566 #define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB                            0
567 #define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK                           0x0000000000000001
568 
569 
570 
571 
572 #define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET                        0x0000000000000020
573 #define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB                           1
574 #define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB                           16
575 #define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK                          0x000000000001fffe
576 
577 
578 
579 
580 #define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET                                 0x0000000000000020
581 #define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB                                    17
582 #define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB                                    18
583 #define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK                                   0x0000000000060000
584 
585 
586 
587 
588 #define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET                                  0x0000000000000020
589 #define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB                                     19
590 #define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB                                     19
591 #define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK                                    0x0000000000080000
592 
593 
594 
595 
596 #define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET                                        0x0000000000000020
597 #define PDG_RESPONSE_RESPONSE_DENSITY_LSB                                           20
598 #define PDG_RESPONSE_RESPONSE_DENSITY_MSB                                           24
599 #define PDG_RESPONSE_RESPONSE_DENSITY_MASK                                          0x0000000001f00000
600 
601 
602 
603 
604 #define PDG_RESPONSE_MORE_DATA_OFFSET                                               0x0000000000000020
605 #define PDG_RESPONSE_MORE_DATA_LSB                                                  25
606 #define PDG_RESPONSE_MORE_DATA_MSB                                                  25
607 #define PDG_RESPONSE_MORE_DATA_MASK                                                 0x0000000002000000
608 
609 
610 
611 
612 #define PDG_RESPONSE_DURATION_INDICATION_OFFSET                                     0x0000000000000020
613 #define PDG_RESPONSE_DURATION_INDICATION_LSB                                        26
614 #define PDG_RESPONSE_DURATION_INDICATION_MSB                                        26
615 #define PDG_RESPONSE_DURATION_INDICATION_MASK                                       0x0000000004000000
616 
617 
618 
619 
620 #define PDG_RESPONSE_RELAYED_FRAME_OFFSET                                           0x0000000000000020
621 #define PDG_RESPONSE_RELAYED_FRAME_LSB                                              27
622 #define PDG_RESPONSE_RELAYED_FRAME_MSB                                              27
623 #define PDG_RESPONSE_RELAYED_FRAME_MASK                                             0x0000000008000000
624 
625 
626 
627 
628 #define PDG_RESPONSE_ADDRESS_INDICATOR_OFFSET                                       0x0000000000000020
629 #define PDG_RESPONSE_ADDRESS_INDICATOR_LSB                                          28
630 #define PDG_RESPONSE_ADDRESS_INDICATOR_MSB                                          28
631 #define PDG_RESPONSE_ADDRESS_INDICATOR_MASK                                         0x0000000010000000
632 
633 
634 
635 
636 #define PDG_RESPONSE_BANDWIDTH_OFFSET                                               0x0000000000000020
637 #define PDG_RESPONSE_BANDWIDTH_LSB                                                  29
638 #define PDG_RESPONSE_BANDWIDTH_MSB                                                  31
639 #define PDG_RESPONSE_BANDWIDTH_MASK                                                 0x00000000e0000000
640 
641 
642 
643 
644 #define PDG_RESPONSE_ACK_ID_OFFSET                                                  0x0000000000000020
645 #define PDG_RESPONSE_ACK_ID_LSB                                                     32
646 #define PDG_RESPONSE_ACK_ID_MSB                                                     47
647 #define PDG_RESPONSE_ACK_ID_MASK                                                    0x0000ffff00000000
648 
649 
650 
651 
652 #define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET                                        0x0000000000000020
653 #define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB                                           48
654 #define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB                                           63
655 #define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK                                          0xffff000000000000
656 
657 
658 
659 
660 #define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET                                     0x0000000000000028
661 #define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB                                        0
662 #define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB                                        3
663 #define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK                                       0x000000000000000f
664 
665 
666 
667 
668 #define PDG_RESPONSE_ACK_ID_EXT_OFFSET                                              0x0000000000000028
669 #define PDG_RESPONSE_ACK_ID_EXT_LSB                                                 4
670 #define PDG_RESPONSE_ACK_ID_EXT_MSB                                                 13
671 #define PDG_RESPONSE_ACK_ID_EXT_MASK                                                0x0000000000003ff0
672 
673 
674 
675 
676 #define PDG_RESPONSE_FTM_EN_OFFSET                                                  0x0000000000000028
677 #define PDG_RESPONSE_FTM_EN_LSB                                                     14
678 #define PDG_RESPONSE_FTM_EN_MSB                                                     14
679 #define PDG_RESPONSE_FTM_EN_MASK                                                    0x0000000000004000
680 
681 
682 
683 
684 #define PDG_RESPONSE_GROUP_ID_OFFSET                                                0x0000000000000028
685 #define PDG_RESPONSE_GROUP_ID_LSB                                                   15
686 #define PDG_RESPONSE_GROUP_ID_MSB                                                   20
687 #define PDG_RESPONSE_GROUP_ID_MASK                                                  0x00000000001f8000
688 
689 
690 
691 
692 #define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET                                         0x0000000000000028
693 #define PDG_RESPONSE_STA_PARTIAL_AID_LSB                                            21
694 #define PDG_RESPONSE_STA_PARTIAL_AID_MSB                                            31
695 #define PDG_RESPONSE_STA_PARTIAL_AID_MASK                                           0x00000000ffe00000
696 
697 
698 
699 
700 #define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET                                   0x0000000000000028
701 #define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB                                      32
702 #define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB                                      43
703 #define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK                                     0x00000fff00000000
704 
705 
706 
707 
708 #define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET                                          0x0000000000000028
709 #define PDG_RESPONSE_ACTIVE_CHANNEL_LSB                                             44
710 #define PDG_RESPONSE_ACTIVE_CHANNEL_MSB                                             46
711 #define PDG_RESPONSE_ACTIVE_CHANNEL_MASK                                            0x0000700000000000
712 
713 
714 
715 
716 #define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET                                  0x0000000000000028
717 #define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB                                     47
718 #define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB                                     47
719 #define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK                                    0x0000800000000000
720 
721 
722 
723 
724 #define PDG_RESPONSE_FRAME_LENGTH_OFFSET                                            0x0000000000000028
725 #define PDG_RESPONSE_FRAME_LENGTH_LSB                                               48
726 #define PDG_RESPONSE_FRAME_LENGTH_MSB                                               63
727 #define PDG_RESPONSE_FRAME_LENGTH_MASK                                              0xffff000000000000
728 
729 
730 
731 #endif
732