1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _MACTX_PHY_DESC_H_ 27 #define _MACTX_PHY_DESC_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_MACTX_PHY_DESC 4 32 33 #define NUM_OF_QWORDS_MACTX_PHY_DESC 2 34 35 36 struct mactx_phy_desc { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t reserved_0a : 16, 39 bf_type : 2, 40 wait_sifs : 2, 41 dot11b_preamble_type : 1, 42 pkt_type : 4, 43 su_or_mu : 2, 44 mu_type : 1, 45 bandwidth : 3, 46 channel_capture : 1; 47 uint32_t mcs : 4, 48 global_ofdma_mimo_enable : 1, 49 reserved_1a : 1, 50 stbc : 1, 51 dot11ax_su_extended : 1, 52 dot11ax_trigger_frame_embedded : 1, 53 tx_pwr_shared : 8, 54 tx_pwr_unshared : 8, 55 measure_power : 1, 56 tpc_glut_self_cal : 1, 57 back_to_back_transmission_expected : 1, 58 heavy_clip_nss : 3, 59 txbf_per_packet_no_csd_no_walsh : 1; 60 uint32_t ndp : 2, 61 ul_flag : 1, 62 triggered : 1, 63 ap_pkt_bw : 3, 64 ru_position_start : 8, 65 pcu_ppdu_setup_start_reason : 3, 66 tlv_source : 1, 67 reserved_2a : 2, 68 nss : 3, 69 stream_offset : 3, 70 reserved_2b : 2, 71 clpc_enable : 1, 72 mu_ndp : 1, 73 response_expected : 1; 74 uint32_t rx_chain_mask : 8, 75 rx_chain_mask_valid : 1, 76 ant_sel_valid : 1, 77 ant_sel : 1, 78 cp_setting : 2, 79 he_ppdu_subtype : 2, 80 active_channel : 3, 81 generate_phyrx_tx_start_timing : 1, 82 ltf_size : 2, 83 ru_size_updated_v2 : 4, 84 reserved_3c : 1, 85 u_sig_puncture_pattern_encoding : 6; 86 #else 87 uint32_t channel_capture : 1, 88 bandwidth : 3, 89 mu_type : 1, 90 su_or_mu : 2, 91 pkt_type : 4, 92 dot11b_preamble_type : 1, 93 wait_sifs : 2, 94 bf_type : 2, 95 reserved_0a : 16; 96 uint32_t txbf_per_packet_no_csd_no_walsh : 1, 97 heavy_clip_nss : 3, 98 back_to_back_transmission_expected : 1, 99 tpc_glut_self_cal : 1, 100 measure_power : 1, 101 tx_pwr_unshared : 8, 102 tx_pwr_shared : 8, 103 dot11ax_trigger_frame_embedded : 1, 104 dot11ax_su_extended : 1, 105 stbc : 1, 106 reserved_1a : 1, 107 global_ofdma_mimo_enable : 1, 108 mcs : 4; 109 uint32_t response_expected : 1, 110 mu_ndp : 1, 111 clpc_enable : 1, 112 reserved_2b : 2, 113 stream_offset : 3, 114 nss : 3, 115 reserved_2a : 2, 116 tlv_source : 1, 117 pcu_ppdu_setup_start_reason : 3, 118 ru_position_start : 8, 119 ap_pkt_bw : 3, 120 triggered : 1, 121 ul_flag : 1, 122 ndp : 2; 123 uint32_t u_sig_puncture_pattern_encoding : 6, 124 reserved_3c : 1, 125 ru_size_updated_v2 : 4, 126 ltf_size : 2, 127 generate_phyrx_tx_start_timing : 1, 128 active_channel : 3, 129 he_ppdu_subtype : 2, 130 cp_setting : 2, 131 ant_sel : 1, 132 ant_sel_valid : 1, 133 rx_chain_mask_valid : 1, 134 rx_chain_mask : 8; 135 #endif 136 }; 137 138 139 140 141 #define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x0000000000000000 142 #define MACTX_PHY_DESC_RESERVED_0A_LSB 0 143 #define MACTX_PHY_DESC_RESERVED_0A_MSB 15 144 #define MACTX_PHY_DESC_RESERVED_0A_MASK 0x000000000000ffff 145 146 147 148 149 #define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x0000000000000000 150 #define MACTX_PHY_DESC_BF_TYPE_LSB 16 151 #define MACTX_PHY_DESC_BF_TYPE_MSB 17 152 #define MACTX_PHY_DESC_BF_TYPE_MASK 0x0000000000030000 153 154 155 156 157 #define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x0000000000000000 158 #define MACTX_PHY_DESC_WAIT_SIFS_LSB 18 159 #define MACTX_PHY_DESC_WAIT_SIFS_MSB 19 160 #define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x00000000000c0000 161 162 163 164 165 #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x0000000000000000 166 #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20 167 #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20 168 #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x0000000000100000 169 170 171 172 173 #define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x0000000000000000 174 #define MACTX_PHY_DESC_PKT_TYPE_LSB 21 175 #define MACTX_PHY_DESC_PKT_TYPE_MSB 24 176 #define MACTX_PHY_DESC_PKT_TYPE_MASK 0x0000000001e00000 177 178 179 180 181 #define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x0000000000000000 182 #define MACTX_PHY_DESC_SU_OR_MU_LSB 25 183 #define MACTX_PHY_DESC_SU_OR_MU_MSB 26 184 #define MACTX_PHY_DESC_SU_OR_MU_MASK 0x0000000006000000 185 186 187 188 189 #define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x0000000000000000 190 #define MACTX_PHY_DESC_MU_TYPE_LSB 27 191 #define MACTX_PHY_DESC_MU_TYPE_MSB 27 192 #define MACTX_PHY_DESC_MU_TYPE_MASK 0x0000000008000000 193 194 195 196 197 #define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x0000000000000000 198 #define MACTX_PHY_DESC_BANDWIDTH_LSB 28 199 #define MACTX_PHY_DESC_BANDWIDTH_MSB 30 200 #define MACTX_PHY_DESC_BANDWIDTH_MASK 0x0000000070000000 201 202 203 204 205 #define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x0000000000000000 206 #define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31 207 #define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31 208 #define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x0000000080000000 209 210 211 212 213 #define MACTX_PHY_DESC_MCS_OFFSET 0x0000000000000000 214 #define MACTX_PHY_DESC_MCS_LSB 32 215 #define MACTX_PHY_DESC_MCS_MSB 35 216 #define MACTX_PHY_DESC_MCS_MASK 0x0000000f00000000 217 218 219 220 221 #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x0000000000000000 222 #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 36 223 #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 36 224 #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x0000001000000000 225 226 227 228 229 #define MACTX_PHY_DESC_RESERVED_1A_OFFSET 0x0000000000000000 230 #define MACTX_PHY_DESC_RESERVED_1A_LSB 37 231 #define MACTX_PHY_DESC_RESERVED_1A_MSB 37 232 #define MACTX_PHY_DESC_RESERVED_1A_MASK 0x0000002000000000 233 234 235 236 237 #define MACTX_PHY_DESC_STBC_OFFSET 0x0000000000000000 238 #define MACTX_PHY_DESC_STBC_LSB 38 239 #define MACTX_PHY_DESC_STBC_MSB 38 240 #define MACTX_PHY_DESC_STBC_MASK 0x0000004000000000 241 242 243 244 245 #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 246 #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 39 247 #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 39 248 #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x0000008000000000 249 250 251 252 253 #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000000 254 #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 40 255 #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 40 256 #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000010000000000 257 258 259 260 261 #define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x0000000000000000 262 #define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 41 263 #define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 48 264 #define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe0000000000 265 266 267 268 269 #define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x0000000000000000 270 #define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 49 271 #define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 56 272 #define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe000000000000 273 274 275 276 277 #define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x0000000000000000 278 #define MACTX_PHY_DESC_MEASURE_POWER_LSB 57 279 #define MACTX_PHY_DESC_MEASURE_POWER_MSB 57 280 #define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x0200000000000000 281 282 283 284 285 #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x0000000000000000 286 #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 58 287 #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 58 288 #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x0400000000000000 289 290 291 292 293 #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x0000000000000000 294 #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 59 295 #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 59 296 #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x0800000000000000 297 298 299 300 301 #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x0000000000000000 302 #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 60 303 #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 62 304 #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x7000000000000000 305 306 307 308 309 #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x0000000000000000 310 #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 63 311 #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 63 312 #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x8000000000000000 313 314 315 316 317 #define MACTX_PHY_DESC_NDP_OFFSET 0x0000000000000008 318 #define MACTX_PHY_DESC_NDP_LSB 0 319 #define MACTX_PHY_DESC_NDP_MSB 1 320 #define MACTX_PHY_DESC_NDP_MASK 0x0000000000000003 321 322 323 324 325 #define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x0000000000000008 326 #define MACTX_PHY_DESC_UL_FLAG_LSB 2 327 #define MACTX_PHY_DESC_UL_FLAG_MSB 2 328 #define MACTX_PHY_DESC_UL_FLAG_MASK 0x0000000000000004 329 330 331 332 333 #define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x0000000000000008 334 #define MACTX_PHY_DESC_TRIGGERED_LSB 3 335 #define MACTX_PHY_DESC_TRIGGERED_MSB 3 336 #define MACTX_PHY_DESC_TRIGGERED_MASK 0x0000000000000008 337 338 339 340 341 #define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x0000000000000008 342 #define MACTX_PHY_DESC_AP_PKT_BW_LSB 4 343 #define MACTX_PHY_DESC_AP_PKT_BW_MSB 6 344 #define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x0000000000000070 345 346 347 348 349 #define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x0000000000000008 350 #define MACTX_PHY_DESC_RU_POSITION_START_LSB 7 351 #define MACTX_PHY_DESC_RU_POSITION_START_MSB 14 352 #define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x0000000000007f80 353 354 355 356 357 #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x0000000000000008 358 #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 15 359 #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 17 360 #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x0000000000038000 361 362 363 364 365 #define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x0000000000000008 366 #define MACTX_PHY_DESC_TLV_SOURCE_LSB 18 367 #define MACTX_PHY_DESC_TLV_SOURCE_MSB 18 368 #define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x0000000000040000 369 370 371 372 373 #define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x0000000000000008 374 #define MACTX_PHY_DESC_RESERVED_2A_LSB 19 375 #define MACTX_PHY_DESC_RESERVED_2A_MSB 20 376 #define MACTX_PHY_DESC_RESERVED_2A_MASK 0x0000000000180000 377 378 379 380 381 #define MACTX_PHY_DESC_NSS_OFFSET 0x0000000000000008 382 #define MACTX_PHY_DESC_NSS_LSB 21 383 #define MACTX_PHY_DESC_NSS_MSB 23 384 #define MACTX_PHY_DESC_NSS_MASK 0x0000000000e00000 385 386 387 388 389 #define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x0000000000000008 390 #define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24 391 #define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26 392 #define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x0000000007000000 393 394 395 396 397 #define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x0000000000000008 398 #define MACTX_PHY_DESC_RESERVED_2B_LSB 27 399 #define MACTX_PHY_DESC_RESERVED_2B_MSB 28 400 #define MACTX_PHY_DESC_RESERVED_2B_MASK 0x0000000018000000 401 402 403 404 405 #define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x0000000000000008 406 #define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29 407 #define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29 408 #define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x0000000020000000 409 410 411 412 413 #define MACTX_PHY_DESC_MU_NDP_OFFSET 0x0000000000000008 414 #define MACTX_PHY_DESC_MU_NDP_LSB 30 415 #define MACTX_PHY_DESC_MU_NDP_MSB 30 416 #define MACTX_PHY_DESC_MU_NDP_MASK 0x0000000040000000 417 418 419 420 421 #define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x0000000000000008 422 #define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31 423 #define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31 424 #define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x0000000080000000 425 426 427 428 429 #define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000000000008 430 #define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 32 431 #define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 39 432 #define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff00000000 433 434 435 436 437 #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000000000008 438 #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 40 439 #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 40 440 #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x0000010000000000 441 442 443 444 445 #define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000000000008 446 #define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 41 447 #define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 41 448 #define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x0000020000000000 449 450 451 452 453 #define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000000000008 454 #define MACTX_PHY_DESC_ANT_SEL_LSB 42 455 #define MACTX_PHY_DESC_ANT_SEL_MSB 42 456 #define MACTX_PHY_DESC_ANT_SEL_MASK 0x0000040000000000 457 458 459 460 461 #define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000000000008 462 #define MACTX_PHY_DESC_CP_SETTING_LSB 43 463 #define MACTX_PHY_DESC_CP_SETTING_MSB 44 464 #define MACTX_PHY_DESC_CP_SETTING_MASK 0x0000180000000000 465 466 467 468 469 #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000000000008 470 #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 45 471 #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 46 472 #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x0000600000000000 473 474 475 476 477 #define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000000000008 478 #define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 47 479 #define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 49 480 #define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x0003800000000000 481 482 483 484 485 #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000000000008 486 #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 50 487 #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 50 488 #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x0004000000000000 489 490 491 492 493 #define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000000000008 494 #define MACTX_PHY_DESC_LTF_SIZE_LSB 51 495 #define MACTX_PHY_DESC_LTF_SIZE_MSB 52 496 #define MACTX_PHY_DESC_LTF_SIZE_MASK 0x0018000000000000 497 498 499 500 501 #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000000000008 502 #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 53 503 #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 56 504 #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e0000000000000 505 506 507 508 509 #define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000000000008 510 #define MACTX_PHY_DESC_RESERVED_3C_LSB 57 511 #define MACTX_PHY_DESC_RESERVED_3C_MSB 57 512 #define MACTX_PHY_DESC_RESERVED_3C_MASK 0x0200000000000000 513 514 515 516 517 #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000008 518 #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 519 #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 520 #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 521 522 523 524 #endif 525