1 2 /* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _WBM_RELEASE_RING_H_ 27 #define _WBM_RELEASE_RING_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "buffer_addr_info.h" 32 #define NUM_OF_DWORDS_WBM_RELEASE_RING 8 33 34 35 struct wbm_release_ring { 36 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 37 struct buffer_addr_info released_buff_or_desc_addr_info; 38 uint32_t release_source_module : 3, 39 reserved_2a : 3, 40 buffer_or_desc_type : 3, 41 reserved_2b : 22, 42 wbm_internal_error : 1; 43 uint32_t reserved_3a : 32; 44 uint32_t reserved_4a : 32; 45 uint32_t reserved_5a : 32; 46 uint32_t reserved_6a : 32; 47 uint32_t reserved_7a : 28, 48 looping_count : 4; 49 #else 50 struct buffer_addr_info released_buff_or_desc_addr_info; 51 uint32_t wbm_internal_error : 1, 52 reserved_2b : 22, 53 buffer_or_desc_type : 3, 54 reserved_2a : 3, 55 release_source_module : 3; 56 uint32_t reserved_3a : 32; 57 uint32_t reserved_4a : 32; 58 uint32_t reserved_5a : 32; 59 uint32_t reserved_6a : 32; 60 uint32_t looping_count : 4, 61 reserved_7a : 28; 62 #endif 63 }; 64 65 66 67 68 69 70 71 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 72 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 73 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 74 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 75 76 77 78 79 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 80 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 81 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 82 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 83 84 85 86 87 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 88 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 89 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 90 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 91 92 93 94 95 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 96 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 97 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 98 #define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 99 100 101 102 103 #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 104 #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0 105 #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB 2 106 #define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 107 108 109 110 111 #define WBM_RELEASE_RING_RESERVED_2A_OFFSET 0x00000008 112 #define WBM_RELEASE_RING_RESERVED_2A_LSB 3 113 #define WBM_RELEASE_RING_RESERVED_2A_MSB 5 114 #define WBM_RELEASE_RING_RESERVED_2A_MASK 0x00000038 115 116 117 118 119 #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 120 #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6 121 #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB 8 122 #define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 123 124 125 126 127 #define WBM_RELEASE_RING_RESERVED_2B_OFFSET 0x00000008 128 #define WBM_RELEASE_RING_RESERVED_2B_LSB 9 129 #define WBM_RELEASE_RING_RESERVED_2B_MSB 30 130 #define WBM_RELEASE_RING_RESERVED_2B_MASK 0x7ffffe00 131 132 133 134 135 #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET 0x00000008 136 #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB 31 137 #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB 31 138 #define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK 0x80000000 139 140 141 142 143 #define WBM_RELEASE_RING_RESERVED_3A_OFFSET 0x0000000c 144 #define WBM_RELEASE_RING_RESERVED_3A_LSB 0 145 #define WBM_RELEASE_RING_RESERVED_3A_MSB 31 146 #define WBM_RELEASE_RING_RESERVED_3A_MASK 0xffffffff 147 148 149 150 151 #define WBM_RELEASE_RING_RESERVED_4A_OFFSET 0x00000010 152 #define WBM_RELEASE_RING_RESERVED_4A_LSB 0 153 #define WBM_RELEASE_RING_RESERVED_4A_MSB 31 154 #define WBM_RELEASE_RING_RESERVED_4A_MASK 0xffffffff 155 156 157 158 159 #define WBM_RELEASE_RING_RESERVED_5A_OFFSET 0x00000014 160 #define WBM_RELEASE_RING_RESERVED_5A_LSB 0 161 #define WBM_RELEASE_RING_RESERVED_5A_MSB 31 162 #define WBM_RELEASE_RING_RESERVED_5A_MASK 0xffffffff 163 164 165 166 167 #define WBM_RELEASE_RING_RESERVED_6A_OFFSET 0x00000018 168 #define WBM_RELEASE_RING_RESERVED_6A_LSB 0 169 #define WBM_RELEASE_RING_RESERVED_6A_MSB 31 170 #define WBM_RELEASE_RING_RESERVED_6A_MASK 0xffffffff 171 172 173 174 175 #define WBM_RELEASE_RING_RESERVED_7A_OFFSET 0x0000001c 176 #define WBM_RELEASE_RING_RESERVED_7A_LSB 0 177 #define WBM_RELEASE_RING_RESERVED_7A_MSB 27 178 #define WBM_RELEASE_RING_RESERVED_7A_MASK 0x0fffffff 179 180 181 182 183 #define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET 0x0000001c 184 #define WBM_RELEASE_RING_LOOPING_COUNT_LSB 28 185 #define WBM_RELEASE_RING_LOOPING_COUNT_MSB 31 186 #define WBM_RELEASE_RING_LOOPING_COUNT_MASK 0xf0000000 187 188 189 190 #endif 191