1 
2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
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25 
26 #ifndef _TXPCU_BUFFER_STATUS_H_
27 #define _TXPCU_BUFFER_STATUS_H_
28 #if !defined(__ASSEMBLER__)
29 #endif
30 
31 #include "txpcu_buffer_basics.h"
32 #define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2
33 
34 #define NUM_OF_QWORDS_TXPCU_BUFFER_STATUS 1
35 
36 
37 struct txpcu_buffer_status {
38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
39              struct   txpcu_buffer_basics                                       txpcu_basix_buffer_info;
40              uint32_t reserved                                                : 15,
41                       msdu_end                                                :  1,
42                       tx_data_sync_value                                      : 16;
43 #else
44              struct   txpcu_buffer_basics                                       txpcu_basix_buffer_info;
45              uint32_t tx_data_sync_value                                      : 16,
46                       msdu_end                                                :  1,
47                       reserved                                                : 15;
48 #endif
49 };
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56 
57 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET         0x0000000000000000
58 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB            0
59 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB            7
60 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK           0x00000000000000ff
61 
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64 
65 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000
66 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB   8
67 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB   15
68 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK  0x000000000000ff00
69 
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73 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET        0x0000000000000000
74 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB           16
75 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB           31
76 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK          0x00000000ffff0000
77 
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80 
81 #define TXPCU_BUFFER_STATUS_RESERVED_OFFSET                                         0x0000000000000000
82 #define TXPCU_BUFFER_STATUS_RESERVED_LSB                                            32
83 #define TXPCU_BUFFER_STATUS_RESERVED_MSB                                            46
84 #define TXPCU_BUFFER_STATUS_RESERVED_MASK                                           0x00007fff00000000
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88 
89 #define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET                                         0x0000000000000000
90 #define TXPCU_BUFFER_STATUS_MSDU_END_LSB                                            47
91 #define TXPCU_BUFFER_STATUS_MSDU_END_MSB                                            47
92 #define TXPCU_BUFFER_STATUS_MSDU_END_MASK                                           0x0000800000000000
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96 
97 #define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET                               0x0000000000000000
98 #define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB                                  48
99 #define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB                                  63
100 #define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK                                 0xffff000000000000
101 
102 
103 
104 #endif
105