1 2 /* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _TCL_DATA_CMD_H_ 27 #define _TCL_DATA_CMD_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "buffer_addr_info.h" 32 #define NUM_OF_DWORDS_TCL_DATA_CMD 8 33 34 35 struct tcl_data_cmd { 36 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 37 struct buffer_addr_info buf_addr_info; 38 uint32_t tcl_cmd_type : 1, 39 buf_or_ext_desc_type : 1, 40 bank_id : 6, 41 tx_notify_frame : 3, 42 header_length_read_sel : 1, 43 buffer_timestamp : 19, 44 buffer_timestamp_valid : 1; 45 uint32_t reserved_3a : 16, 46 tcl_cmd_number : 16; 47 uint32_t data_length : 16, 48 ipv4_checksum_en : 1, 49 udp_over_ipv4_checksum_en : 1, 50 udp_over_ipv6_checksum_en : 1, 51 tcp_over_ipv4_checksum_en : 1, 52 tcp_over_ipv6_checksum_en : 1, 53 to_fw : 1, 54 reserved_4a : 1, 55 packet_offset : 9; 56 uint32_t hlos_tid_overwrite : 1, 57 flow_override_enable : 1, 58 who_classify_info_sel : 2, 59 hlos_tid : 4, 60 flow_override : 1, 61 pmac_id : 2, 62 msdu_color : 2, 63 reserved_5a : 11, 64 vdev_id : 8; 65 uint32_t search_index : 20, 66 cache_set_num : 4, 67 index_lookup_override : 1, 68 reserved_6a : 7; 69 uint32_t reserved_7a : 20, 70 ring_id : 8, 71 looping_count : 4; 72 #else 73 struct buffer_addr_info buf_addr_info; 74 uint32_t buffer_timestamp_valid : 1, 75 buffer_timestamp : 19, 76 header_length_read_sel : 1, 77 tx_notify_frame : 3, 78 bank_id : 6, 79 buf_or_ext_desc_type : 1, 80 tcl_cmd_type : 1; 81 uint32_t tcl_cmd_number : 16, 82 reserved_3a : 16; 83 uint32_t packet_offset : 9, 84 reserved_4a : 1, 85 to_fw : 1, 86 tcp_over_ipv6_checksum_en : 1, 87 tcp_over_ipv4_checksum_en : 1, 88 udp_over_ipv6_checksum_en : 1, 89 udp_over_ipv4_checksum_en : 1, 90 ipv4_checksum_en : 1, 91 data_length : 16; 92 uint32_t vdev_id : 8, 93 reserved_5a : 11, 94 msdu_color : 2, 95 pmac_id : 2, 96 flow_override : 1, 97 hlos_tid : 4, 98 who_classify_info_sel : 2, 99 flow_override_enable : 1, 100 hlos_tid_overwrite : 1; 101 uint32_t reserved_6a : 7, 102 index_lookup_override : 1, 103 cache_set_num : 4, 104 search_index : 20; 105 uint32_t looping_count : 4, 106 ring_id : 8, 107 reserved_7a : 20; 108 #endif 109 }; 110 111 112 113 114 115 116 117 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 118 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 119 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 120 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 121 122 123 124 125 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 126 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 127 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 128 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 129 130 131 132 133 #define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 134 #define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 135 #define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 136 #define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 137 138 139 140 141 #define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 142 #define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 143 #define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 144 #define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 145 146 147 148 149 #define TCL_DATA_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 150 #define TCL_DATA_CMD_TCL_CMD_TYPE_LSB 0 151 #define TCL_DATA_CMD_TCL_CMD_TYPE_MSB 0 152 #define TCL_DATA_CMD_TCL_CMD_TYPE_MASK 0x00000001 153 154 155 156 157 #define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 158 #define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 1 159 #define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MSB 1 160 #define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 0x00000002 161 162 163 164 165 #define TCL_DATA_CMD_BANK_ID_OFFSET 0x00000008 166 #define TCL_DATA_CMD_BANK_ID_LSB 2 167 #define TCL_DATA_CMD_BANK_ID_MSB 7 168 #define TCL_DATA_CMD_BANK_ID_MASK 0x000000fc 169 170 171 172 173 #define TCL_DATA_CMD_TX_NOTIFY_FRAME_OFFSET 0x00000008 174 #define TCL_DATA_CMD_TX_NOTIFY_FRAME_LSB 8 175 #define TCL_DATA_CMD_TX_NOTIFY_FRAME_MSB 10 176 #define TCL_DATA_CMD_TX_NOTIFY_FRAME_MASK 0x00000700 177 178 179 180 181 #define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_OFFSET 0x00000008 182 #define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_LSB 11 183 #define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MSB 11 184 #define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MASK 0x00000800 185 186 187 188 189 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_OFFSET 0x00000008 190 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_LSB 12 191 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_MSB 30 192 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_MASK 0x7ffff000 193 194 195 196 197 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000008 198 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_LSB 31 199 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MSB 31 200 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MASK 0x80000000 201 202 203 204 205 #define TCL_DATA_CMD_RESERVED_3A_OFFSET 0x0000000c 206 #define TCL_DATA_CMD_RESERVED_3A_LSB 0 207 #define TCL_DATA_CMD_RESERVED_3A_MSB 15 208 #define TCL_DATA_CMD_RESERVED_3A_MASK 0x0000ffff 209 210 211 212 213 #define TCL_DATA_CMD_TCL_CMD_NUMBER_OFFSET 0x0000000c 214 #define TCL_DATA_CMD_TCL_CMD_NUMBER_LSB 16 215 #define TCL_DATA_CMD_TCL_CMD_NUMBER_MSB 31 216 #define TCL_DATA_CMD_TCL_CMD_NUMBER_MASK 0xffff0000 217 218 219 220 221 #define TCL_DATA_CMD_DATA_LENGTH_OFFSET 0x00000010 222 #define TCL_DATA_CMD_DATA_LENGTH_LSB 0 223 #define TCL_DATA_CMD_DATA_LENGTH_MSB 15 224 #define TCL_DATA_CMD_DATA_LENGTH_MASK 0x0000ffff 225 226 227 228 229 #define TCL_DATA_CMD_IPV4_CHECKSUM_EN_OFFSET 0x00000010 230 #define TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB 16 231 #define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MSB 16 232 #define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MASK 0x00010000 233 234 235 236 237 #define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010 238 #define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17 239 #define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MSB 17 240 #define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000 241 242 243 244 245 #define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010 246 #define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18 247 #define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MSB 18 248 #define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000 249 250 251 252 253 #define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010 254 #define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19 255 #define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MSB 19 256 #define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000 257 258 259 260 261 #define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010 262 #define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20 263 #define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MSB 20 264 #define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000 265 266 267 268 269 #define TCL_DATA_CMD_TO_FW_OFFSET 0x00000010 270 #define TCL_DATA_CMD_TO_FW_LSB 21 271 #define TCL_DATA_CMD_TO_FW_MSB 21 272 #define TCL_DATA_CMD_TO_FW_MASK 0x00200000 273 274 275 276 277 #define TCL_DATA_CMD_RESERVED_4A_OFFSET 0x00000010 278 #define TCL_DATA_CMD_RESERVED_4A_LSB 22 279 #define TCL_DATA_CMD_RESERVED_4A_MSB 22 280 #define TCL_DATA_CMD_RESERVED_4A_MASK 0x00400000 281 282 283 284 285 #define TCL_DATA_CMD_PACKET_OFFSET_OFFSET 0x00000010 286 #define TCL_DATA_CMD_PACKET_OFFSET_LSB 23 287 #define TCL_DATA_CMD_PACKET_OFFSET_MSB 31 288 #define TCL_DATA_CMD_PACKET_OFFSET_MASK 0xff800000 289 290 291 292 293 #define TCL_DATA_CMD_HLOS_TID_OVERWRITE_OFFSET 0x00000014 294 #define TCL_DATA_CMD_HLOS_TID_OVERWRITE_LSB 0 295 #define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MSB 0 296 #define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MASK 0x00000001 297 298 299 300 301 #define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_OFFSET 0x00000014 302 #define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_LSB 1 303 #define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MSB 1 304 #define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MASK 0x00000002 305 306 307 308 309 #define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_OFFSET 0x00000014 310 #define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_LSB 2 311 #define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MSB 3 312 #define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MASK 0x0000000c 313 314 315 316 317 #define TCL_DATA_CMD_HLOS_TID_OFFSET 0x00000014 318 #define TCL_DATA_CMD_HLOS_TID_LSB 4 319 #define TCL_DATA_CMD_HLOS_TID_MSB 7 320 #define TCL_DATA_CMD_HLOS_TID_MASK 0x000000f0 321 322 323 324 325 #define TCL_DATA_CMD_FLOW_OVERRIDE_OFFSET 0x00000014 326 #define TCL_DATA_CMD_FLOW_OVERRIDE_LSB 8 327 #define TCL_DATA_CMD_FLOW_OVERRIDE_MSB 8 328 #define TCL_DATA_CMD_FLOW_OVERRIDE_MASK 0x00000100 329 330 331 332 333 #define TCL_DATA_CMD_PMAC_ID_OFFSET 0x00000014 334 #define TCL_DATA_CMD_PMAC_ID_LSB 9 335 #define TCL_DATA_CMD_PMAC_ID_MSB 10 336 #define TCL_DATA_CMD_PMAC_ID_MASK 0x00000600 337 338 339 340 341 #define TCL_DATA_CMD_MSDU_COLOR_OFFSET 0x00000014 342 #define TCL_DATA_CMD_MSDU_COLOR_LSB 11 343 #define TCL_DATA_CMD_MSDU_COLOR_MSB 12 344 #define TCL_DATA_CMD_MSDU_COLOR_MASK 0x00001800 345 346 347 348 349 #define TCL_DATA_CMD_RESERVED_5A_OFFSET 0x00000014 350 #define TCL_DATA_CMD_RESERVED_5A_LSB 13 351 #define TCL_DATA_CMD_RESERVED_5A_MSB 23 352 #define TCL_DATA_CMD_RESERVED_5A_MASK 0x00ffe000 353 354 355 356 357 #define TCL_DATA_CMD_VDEV_ID_OFFSET 0x00000014 358 #define TCL_DATA_CMD_VDEV_ID_LSB 24 359 #define TCL_DATA_CMD_VDEV_ID_MSB 31 360 #define TCL_DATA_CMD_VDEV_ID_MASK 0xff000000 361 362 363 364 365 #define TCL_DATA_CMD_SEARCH_INDEX_OFFSET 0x00000018 366 #define TCL_DATA_CMD_SEARCH_INDEX_LSB 0 367 #define TCL_DATA_CMD_SEARCH_INDEX_MSB 19 368 #define TCL_DATA_CMD_SEARCH_INDEX_MASK 0x000fffff 369 370 371 372 373 #define TCL_DATA_CMD_CACHE_SET_NUM_OFFSET 0x00000018 374 #define TCL_DATA_CMD_CACHE_SET_NUM_LSB 20 375 #define TCL_DATA_CMD_CACHE_SET_NUM_MSB 23 376 #define TCL_DATA_CMD_CACHE_SET_NUM_MASK 0x00f00000 377 378 379 380 381 #define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_OFFSET 0x00000018 382 #define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_LSB 24 383 #define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MSB 24 384 #define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MASK 0x01000000 385 386 387 388 389 #define TCL_DATA_CMD_RESERVED_6A_OFFSET 0x00000018 390 #define TCL_DATA_CMD_RESERVED_6A_LSB 25 391 #define TCL_DATA_CMD_RESERVED_6A_MSB 31 392 #define TCL_DATA_CMD_RESERVED_6A_MASK 0xfe000000 393 394 395 396 397 #define TCL_DATA_CMD_RESERVED_7A_OFFSET 0x0000001c 398 #define TCL_DATA_CMD_RESERVED_7A_LSB 0 399 #define TCL_DATA_CMD_RESERVED_7A_MSB 19 400 #define TCL_DATA_CMD_RESERVED_7A_MASK 0x000fffff 401 402 403 404 405 #define TCL_DATA_CMD_RING_ID_OFFSET 0x0000001c 406 #define TCL_DATA_CMD_RING_ID_LSB 20 407 #define TCL_DATA_CMD_RING_ID_MSB 27 408 #define TCL_DATA_CMD_RING_ID_MASK 0x0ff00000 409 410 411 412 413 #define TCL_DATA_CMD_LOOPING_COUNT_OFFSET 0x0000001c 414 #define TCL_DATA_CMD_LOOPING_COUNT_LSB 28 415 #define TCL_DATA_CMD_LOOPING_COUNT_MSB 31 416 #define TCL_DATA_CMD_LOOPING_COUNT_MASK 0xf0000000 417 418 419 420 #endif 421