1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_FRAME_BITMAP_ACK_H_ 27 #define _RX_FRAME_BITMAP_ACK_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 14 32 33 #define NUM_OF_QWORDS_RX_FRAME_BITMAP_ACK 7 34 35 36 struct rx_frame_bitmap_ack { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t no_bitmap_available : 1, 39 explicit_ack : 1, 40 explict_ack_type : 3, 41 ba_bitmap_size : 2, 42 reserved_0a : 3, 43 ba_tid : 4, 44 sta_full_aid : 13, 45 reserved_0b : 5; 46 uint32_t addr1_31_0 : 32; 47 uint32_t addr1_47_32 : 16, 48 addr2_15_0 : 16; 49 uint32_t addr2_47_16 : 32; 50 uint32_t ba_ts_ctrl : 16, 51 ba_ts_seq : 16; 52 uint32_t ba_ts_bitmap_31_0 : 32; 53 uint32_t ba_ts_bitmap_63_32 : 32; 54 uint32_t ba_ts_bitmap_95_64 : 32; 55 uint32_t ba_ts_bitmap_127_96 : 32; 56 uint32_t ba_ts_bitmap_159_128 : 32; 57 uint32_t ba_ts_bitmap_191_160 : 32; 58 uint32_t ba_ts_bitmap_223_192 : 32; 59 uint32_t ba_ts_bitmap_255_224 : 32; 60 uint32_t tlv64_padding : 32; 61 #else 62 uint32_t reserved_0b : 5, 63 sta_full_aid : 13, 64 ba_tid : 4, 65 reserved_0a : 3, 66 ba_bitmap_size : 2, 67 explict_ack_type : 3, 68 explicit_ack : 1, 69 no_bitmap_available : 1; 70 uint32_t addr1_31_0 : 32; 71 uint32_t addr2_15_0 : 16, 72 addr1_47_32 : 16; 73 uint32_t addr2_47_16 : 32; 74 uint32_t ba_ts_seq : 16, 75 ba_ts_ctrl : 16; 76 uint32_t ba_ts_bitmap_31_0 : 32; 77 uint32_t ba_ts_bitmap_63_32 : 32; 78 uint32_t ba_ts_bitmap_95_64 : 32; 79 uint32_t ba_ts_bitmap_127_96 : 32; 80 uint32_t ba_ts_bitmap_159_128 : 32; 81 uint32_t ba_ts_bitmap_191_160 : 32; 82 uint32_t ba_ts_bitmap_223_192 : 32; 83 uint32_t ba_ts_bitmap_255_224 : 32; 84 uint32_t tlv64_padding : 32; 85 #endif 86 }; 87 88 89 90 91 #define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET 0x0000000000000000 92 #define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB 0 93 #define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB 0 94 #define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK 0x0000000000000001 95 96 97 98 99 #define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET 0x0000000000000000 100 #define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB 1 101 #define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB 1 102 #define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK 0x0000000000000002 103 104 105 106 107 #define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET 0x0000000000000000 108 #define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB 2 109 #define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB 4 110 #define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK 0x000000000000001c 111 112 113 114 115 #define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 116 #define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 117 #define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 118 #define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 119 120 121 122 123 #define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 124 #define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB 7 125 #define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB 9 126 #define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK 0x0000000000000380 127 128 129 130 131 #define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 132 #define RX_FRAME_BITMAP_ACK_BA_TID_LSB 10 133 #define RX_FRAME_BITMAP_ACK_BA_TID_MSB 13 134 #define RX_FRAME_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 135 136 137 138 139 #define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 140 #define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB 14 141 #define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB 26 142 #define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 143 144 145 146 147 #define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 148 #define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB 27 149 #define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB 31 150 #define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK 0x00000000f8000000 151 152 153 154 155 #define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000000 156 #define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB 32 157 #define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB 63 158 #define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff00000000 159 160 161 162 163 #define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 164 #define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB 0 165 #define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB 15 166 #define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK 0x000000000000ffff 167 168 169 170 171 #define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 172 #define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB 16 173 #define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB 31 174 #define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK 0x00000000ffff0000 175 176 177 178 179 #define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000008 180 #define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB 32 181 #define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB 63 182 #define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff00000000 183 184 185 186 187 #define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 188 #define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB 0 189 #define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB 15 190 #define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK 0x000000000000ffff 191 192 193 194 195 #define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 196 #define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB 16 197 #define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB 31 198 #define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK 0x00000000ffff0000 199 200 201 202 203 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000010 204 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 32 205 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 63 206 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff00000000 207 208 209 210 211 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 212 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 213 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 214 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0x00000000ffffffff 215 216 217 218 219 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000018 220 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 32 221 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 63 222 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff00000000 223 224 225 226 227 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 228 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 229 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 230 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0x00000000ffffffff 231 232 233 234 235 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000020 236 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 32 237 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 63 238 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff00000000 239 240 241 242 243 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 244 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 245 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 246 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0x00000000ffffffff 247 248 249 250 251 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000028 252 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 32 253 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 63 254 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff00000000 255 256 257 258 259 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 260 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 261 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 262 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0x00000000ffffffff 263 264 265 266 267 #define RX_FRAME_BITMAP_ACK_TLV64_PADDING_OFFSET 0x0000000000000030 268 #define RX_FRAME_BITMAP_ACK_TLV64_PADDING_LSB 32 269 #define RX_FRAME_BITMAP_ACK_TLV64_PADDING_MSB 63 270 #define RX_FRAME_BITMAP_ACK_TLV64_PADDING_MASK 0xffffffff00000000 271 272 273 274 #endif 275