1 2 /* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_ATTENTION_H_ 27 #define _RX_ATTENTION_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_RX_ATTENTION 4 32 33 #define NUM_OF_QWORDS_RX_ATTENTION 2 34 35 36 struct rx_attention { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t rxpcu_mpdu_filter_in_category : 2, 39 sw_frame_group_id : 7, 40 reserved_0 : 7, 41 phy_ppdu_id : 16; 42 uint32_t first_mpdu : 1, 43 reserved_1a : 1, 44 mcast_bcast : 1, 45 ast_index_not_found : 1, 46 ast_index_timeout : 1, 47 power_mgmt : 1, 48 non_qos : 1, 49 null_data : 1, 50 mgmt_type : 1, 51 ctrl_type : 1, 52 more_data : 1, 53 eosp : 1, 54 a_msdu_error : 1, 55 fragment_flag : 1, 56 order : 1, 57 cce_match : 1, 58 overflow_err : 1, 59 msdu_length_err : 1, 60 tcp_udp_chksum_fail : 1, 61 ip_chksum_fail : 1, 62 sa_idx_invalid : 1, 63 da_idx_invalid : 1, 64 reserved_1b : 1, 65 rx_in_tx_decrypt_byp : 1, 66 encrypt_required : 1, 67 directed : 1, 68 buffer_fragment : 1, 69 mpdu_length_err : 1, 70 tkip_mic_err : 1, 71 decrypt_err : 1, 72 unencrypted_frame_err : 1, 73 fcs_err : 1; 74 uint32_t flow_idx_timeout : 1, 75 flow_idx_invalid : 1, 76 wifi_parser_error : 1, 77 amsdu_parser_error : 1, 78 sa_idx_timeout : 1, 79 da_idx_timeout : 1, 80 msdu_limit_error : 1, 81 da_is_valid : 1, 82 da_is_mcbc : 1, 83 sa_is_valid : 1, 84 decrypt_status_code : 3, 85 rx_bitmap_not_updated : 1, 86 reserved_2 : 17, 87 msdu_done : 1; 88 uint32_t tlv64_padding : 32; 89 #else 90 uint32_t phy_ppdu_id : 16, 91 reserved_0 : 7, 92 sw_frame_group_id : 7, 93 rxpcu_mpdu_filter_in_category : 2; 94 uint32_t fcs_err : 1, 95 unencrypted_frame_err : 1, 96 decrypt_err : 1, 97 tkip_mic_err : 1, 98 mpdu_length_err : 1, 99 buffer_fragment : 1, 100 directed : 1, 101 encrypt_required : 1, 102 rx_in_tx_decrypt_byp : 1, 103 reserved_1b : 1, 104 da_idx_invalid : 1, 105 sa_idx_invalid : 1, 106 ip_chksum_fail : 1, 107 tcp_udp_chksum_fail : 1, 108 msdu_length_err : 1, 109 overflow_err : 1, 110 cce_match : 1, 111 order : 1, 112 fragment_flag : 1, 113 a_msdu_error : 1, 114 eosp : 1, 115 more_data : 1, 116 ctrl_type : 1, 117 mgmt_type : 1, 118 null_data : 1, 119 non_qos : 1, 120 power_mgmt : 1, 121 ast_index_timeout : 1, 122 ast_index_not_found : 1, 123 mcast_bcast : 1, 124 reserved_1a : 1, 125 first_mpdu : 1; 126 uint32_t msdu_done : 1, 127 reserved_2 : 17, 128 rx_bitmap_not_updated : 1, 129 decrypt_status_code : 3, 130 sa_is_valid : 1, 131 da_is_mcbc : 1, 132 da_is_valid : 1, 133 msdu_limit_error : 1, 134 da_idx_timeout : 1, 135 sa_idx_timeout : 1, 136 amsdu_parser_error : 1, 137 wifi_parser_error : 1, 138 flow_idx_invalid : 1, 139 flow_idx_timeout : 1; 140 uint32_t tlv64_padding : 32; 141 #endif 142 }; 143 144 145 146 147 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 148 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 149 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 150 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 151 152 153 154 155 #define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 156 #define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2 157 #define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8 158 #define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 159 160 161 162 163 #define RX_ATTENTION_RESERVED_0_OFFSET 0x0000000000000000 164 #define RX_ATTENTION_RESERVED_0_LSB 9 165 #define RX_ATTENTION_RESERVED_0_MSB 15 166 #define RX_ATTENTION_RESERVED_0_MASK 0x000000000000fe00 167 168 169 170 171 #define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x0000000000000000 172 #define RX_ATTENTION_PHY_PPDU_ID_LSB 16 173 #define RX_ATTENTION_PHY_PPDU_ID_MSB 31 174 #define RX_ATTENTION_PHY_PPDU_ID_MASK 0x00000000ffff0000 175 176 177 178 179 #define RX_ATTENTION_FIRST_MPDU_OFFSET 0x0000000000000000 180 #define RX_ATTENTION_FIRST_MPDU_LSB 32 181 #define RX_ATTENTION_FIRST_MPDU_MSB 32 182 #define RX_ATTENTION_FIRST_MPDU_MASK 0x0000000100000000 183 184 185 186 187 #define RX_ATTENTION_RESERVED_1A_OFFSET 0x0000000000000000 188 #define RX_ATTENTION_RESERVED_1A_LSB 33 189 #define RX_ATTENTION_RESERVED_1A_MSB 33 190 #define RX_ATTENTION_RESERVED_1A_MASK 0x0000000200000000 191 192 193 194 195 #define RX_ATTENTION_MCAST_BCAST_OFFSET 0x0000000000000000 196 #define RX_ATTENTION_MCAST_BCAST_LSB 34 197 #define RX_ATTENTION_MCAST_BCAST_MSB 34 198 #define RX_ATTENTION_MCAST_BCAST_MASK 0x0000000400000000 199 200 201 202 203 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000000 204 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 35 205 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 35 206 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x0000000800000000 207 208 209 210 211 #define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000000 212 #define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 36 213 #define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 36 214 #define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x0000001000000000 215 216 217 218 219 #define RX_ATTENTION_POWER_MGMT_OFFSET 0x0000000000000000 220 #define RX_ATTENTION_POWER_MGMT_LSB 37 221 #define RX_ATTENTION_POWER_MGMT_MSB 37 222 #define RX_ATTENTION_POWER_MGMT_MASK 0x0000002000000000 223 224 225 226 227 #define RX_ATTENTION_NON_QOS_OFFSET 0x0000000000000000 228 #define RX_ATTENTION_NON_QOS_LSB 38 229 #define RX_ATTENTION_NON_QOS_MSB 38 230 #define RX_ATTENTION_NON_QOS_MASK 0x0000004000000000 231 232 233 234 235 #define RX_ATTENTION_NULL_DATA_OFFSET 0x0000000000000000 236 #define RX_ATTENTION_NULL_DATA_LSB 39 237 #define RX_ATTENTION_NULL_DATA_MSB 39 238 #define RX_ATTENTION_NULL_DATA_MASK 0x0000008000000000 239 240 241 242 243 #define RX_ATTENTION_MGMT_TYPE_OFFSET 0x0000000000000000 244 #define RX_ATTENTION_MGMT_TYPE_LSB 40 245 #define RX_ATTENTION_MGMT_TYPE_MSB 40 246 #define RX_ATTENTION_MGMT_TYPE_MASK 0x0000010000000000 247 248 249 250 251 #define RX_ATTENTION_CTRL_TYPE_OFFSET 0x0000000000000000 252 #define RX_ATTENTION_CTRL_TYPE_LSB 41 253 #define RX_ATTENTION_CTRL_TYPE_MSB 41 254 #define RX_ATTENTION_CTRL_TYPE_MASK 0x0000020000000000 255 256 257 258 259 #define RX_ATTENTION_MORE_DATA_OFFSET 0x0000000000000000 260 #define RX_ATTENTION_MORE_DATA_LSB 42 261 #define RX_ATTENTION_MORE_DATA_MSB 42 262 #define RX_ATTENTION_MORE_DATA_MASK 0x0000040000000000 263 264 265 266 267 #define RX_ATTENTION_EOSP_OFFSET 0x0000000000000000 268 #define RX_ATTENTION_EOSP_LSB 43 269 #define RX_ATTENTION_EOSP_MSB 43 270 #define RX_ATTENTION_EOSP_MASK 0x0000080000000000 271 272 273 274 275 #define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x0000000000000000 276 #define RX_ATTENTION_A_MSDU_ERROR_LSB 44 277 #define RX_ATTENTION_A_MSDU_ERROR_MSB 44 278 #define RX_ATTENTION_A_MSDU_ERROR_MASK 0x0000100000000000 279 280 281 282 283 #define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x0000000000000000 284 #define RX_ATTENTION_FRAGMENT_FLAG_LSB 45 285 #define RX_ATTENTION_FRAGMENT_FLAG_MSB 45 286 #define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x0000200000000000 287 288 289 290 291 #define RX_ATTENTION_ORDER_OFFSET 0x0000000000000000 292 #define RX_ATTENTION_ORDER_LSB 46 293 #define RX_ATTENTION_ORDER_MSB 46 294 #define RX_ATTENTION_ORDER_MASK 0x0000400000000000 295 296 297 298 299 #define RX_ATTENTION_CCE_MATCH_OFFSET 0x0000000000000000 300 #define RX_ATTENTION_CCE_MATCH_LSB 47 301 #define RX_ATTENTION_CCE_MATCH_MSB 47 302 #define RX_ATTENTION_CCE_MATCH_MASK 0x0000800000000000 303 304 305 306 307 #define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x0000000000000000 308 #define RX_ATTENTION_OVERFLOW_ERR_LSB 48 309 #define RX_ATTENTION_OVERFLOW_ERR_MSB 48 310 #define RX_ATTENTION_OVERFLOW_ERR_MASK 0x0001000000000000 311 312 313 314 315 #define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 316 #define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 49 317 #define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 49 318 #define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x0002000000000000 319 320 321 322 323 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000000 324 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 50 325 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 50 326 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x0004000000000000 327 328 329 330 331 #define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x0000000000000000 332 #define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 51 333 #define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 51 334 #define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x0008000000000000 335 336 337 338 339 #define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x0000000000000000 340 #define RX_ATTENTION_SA_IDX_INVALID_LSB 52 341 #define RX_ATTENTION_SA_IDX_INVALID_MSB 52 342 #define RX_ATTENTION_SA_IDX_INVALID_MASK 0x0010000000000000 343 344 345 346 347 #define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x0000000000000000 348 #define RX_ATTENTION_DA_IDX_INVALID_LSB 53 349 #define RX_ATTENTION_DA_IDX_INVALID_MSB 53 350 #define RX_ATTENTION_DA_IDX_INVALID_MASK 0x0020000000000000 351 352 353 354 355 #define RX_ATTENTION_RESERVED_1B_OFFSET 0x0000000000000000 356 #define RX_ATTENTION_RESERVED_1B_LSB 54 357 #define RX_ATTENTION_RESERVED_1B_MSB 54 358 #define RX_ATTENTION_RESERVED_1B_MASK 0x0040000000000000 359 360 361 362 363 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 364 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 55 365 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 55 366 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x0080000000000000 367 368 369 370 371 #define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x0000000000000000 372 #define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 56 373 #define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 56 374 #define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x0100000000000000 375 376 377 378 379 #define RX_ATTENTION_DIRECTED_OFFSET 0x0000000000000000 380 #define RX_ATTENTION_DIRECTED_LSB 57 381 #define RX_ATTENTION_DIRECTED_MSB 57 382 #define RX_ATTENTION_DIRECTED_MASK 0x0200000000000000 383 384 385 386 387 #define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x0000000000000000 388 #define RX_ATTENTION_BUFFER_FRAGMENT_LSB 58 389 #define RX_ATTENTION_BUFFER_FRAGMENT_MSB 58 390 #define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x0400000000000000 391 392 393 394 395 #define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 396 #define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 59 397 #define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 59 398 #define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x0800000000000000 399 400 401 402 403 #define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x0000000000000000 404 #define RX_ATTENTION_TKIP_MIC_ERR_LSB 60 405 #define RX_ATTENTION_TKIP_MIC_ERR_MSB 60 406 #define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x1000000000000000 407 408 409 410 411 #define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x0000000000000000 412 #define RX_ATTENTION_DECRYPT_ERR_LSB 61 413 #define RX_ATTENTION_DECRYPT_ERR_MSB 61 414 #define RX_ATTENTION_DECRYPT_ERR_MASK 0x2000000000000000 415 416 417 418 419 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 420 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 62 421 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 62 422 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x4000000000000000 423 424 425 426 427 #define RX_ATTENTION_FCS_ERR_OFFSET 0x0000000000000000 428 #define RX_ATTENTION_FCS_ERR_LSB 63 429 #define RX_ATTENTION_FCS_ERR_MSB 63 430 #define RX_ATTENTION_FCS_ERR_MASK 0x8000000000000000 431 432 433 434 435 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000008 436 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0 437 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0 438 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x0000000000000001 439 440 441 442 443 #define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x0000000000000008 444 #define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1 445 #define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1 446 #define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x0000000000000002 447 448 449 450 451 #define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x0000000000000008 452 #define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2 453 #define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2 454 #define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x0000000000000004 455 456 457 458 459 #define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000008 460 #define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3 461 #define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3 462 #define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x0000000000000008 463 464 465 466 467 #define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x0000000000000008 468 #define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4 469 #define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4 470 #define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x0000000000000010 471 472 473 474 475 #define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x0000000000000008 476 #define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5 477 #define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5 478 #define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x0000000000000020 479 480 481 482 483 #define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000008 484 #define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6 485 #define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6 486 #define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x0000000000000040 487 488 489 490 491 #define RX_ATTENTION_DA_IS_VALID_OFFSET 0x0000000000000008 492 #define RX_ATTENTION_DA_IS_VALID_LSB 7 493 #define RX_ATTENTION_DA_IS_VALID_MSB 7 494 #define RX_ATTENTION_DA_IS_VALID_MASK 0x0000000000000080 495 496 497 498 499 #define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x0000000000000008 500 #define RX_ATTENTION_DA_IS_MCBC_LSB 8 501 #define RX_ATTENTION_DA_IS_MCBC_MSB 8 502 #define RX_ATTENTION_DA_IS_MCBC_MASK 0x0000000000000100 503 504 505 506 507 #define RX_ATTENTION_SA_IS_VALID_OFFSET 0x0000000000000008 508 #define RX_ATTENTION_SA_IS_VALID_LSB 9 509 #define RX_ATTENTION_SA_IS_VALID_MSB 9 510 #define RX_ATTENTION_SA_IS_VALID_MASK 0x0000000000000200 511 512 513 514 515 #define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000008 516 #define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10 517 #define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12 518 #define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x0000000000001c00 519 520 521 522 523 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000008 524 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13 525 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13 526 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x0000000000002000 527 528 529 530 531 #define RX_ATTENTION_RESERVED_2_OFFSET 0x0000000000000008 532 #define RX_ATTENTION_RESERVED_2_LSB 14 533 #define RX_ATTENTION_RESERVED_2_MSB 30 534 #define RX_ATTENTION_RESERVED_2_MASK 0x000000007fffc000 535 536 537 538 539 #define RX_ATTENTION_MSDU_DONE_OFFSET 0x0000000000000008 540 #define RX_ATTENTION_MSDU_DONE_LSB 31 541 #define RX_ATTENTION_MSDU_DONE_MSB 31 542 #define RX_ATTENTION_MSDU_DONE_MASK 0x0000000080000000 543 544 545 546 547 #define RX_ATTENTION_TLV64_PADDING_OFFSET 0x0000000000000008 548 #define RX_ATTENTION_TLV64_PADDING_LSB 32 549 #define RX_ATTENTION_TLV64_PADDING_MSB 63 550 #define RX_ATTENTION_TLV64_PADDING_MASK 0xffffffff00000000 551 552 553 554 #endif 555