1 
2 /* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
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25 
26 #ifndef _HE_SIG_B1_MU_INFO_H_
27 #define _HE_SIG_B1_MU_INFO_H_
28 #if !defined(__ASSEMBLER__)
29 #endif
30 
31 #define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1
32 
33 
34 struct he_sig_b1_mu_info {
35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
36              uint32_t ru_allocation                                           :  8,
37                       reserved_0                                              : 23,
38                       rx_integrity_check_passed                               :  1;
39 #else
40              uint32_t rx_integrity_check_passed                               :  1,
41                       reserved_0                                              : 23,
42                       ru_allocation                                           :  8;
43 #endif
44 };
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48 
49 #define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET                                      0x00000000
50 #define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB                                         0
51 #define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB                                         7
52 #define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK                                        0x000000ff
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57 #define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET                                         0x00000000
58 #define HE_SIG_B1_MU_INFO_RESERVED_0_LSB                                            8
59 #define HE_SIG_B1_MU_INFO_RESERVED_0_MSB                                            30
60 #define HE_SIG_B1_MU_INFO_RESERVED_0_MASK                                           0x7fffff00
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65 #define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                          0x00000000
66 #define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                             31
67 #define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                             31
68 #define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                            0x80000000
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71 
72 #endif
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