1 /*
2  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef _RX_MPDU_END_H_
18 #define _RX_MPDU_END_H_
19 #if !defined(__ASSEMBLER__)
20 #endif
21 
22 
23 // ################ START SUMMARY #################
24 //
25 //	Dword	Fields
26 //	0	rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16]
27 //	1	reserved_1a[10:0], unsup_ktype_short_frame[11], rx_in_tx_decrypt_byp[12], overflow_err[13], mpdu_length_err[14], tkip_mic_err[15], decrypt_err[16], unencrypted_frame_err[17], pn_fields_contain_valid_info[18], fcs_err[19], msdu_length_err[20], rxdma0_destination_ring[22:21], rxdma1_destination_ring[24:23], decrypt_status_code[27:25], rx_bitmap_not_updated[28], reserved_1b[31:29]
28 //
29 // ################ END SUMMARY #################
30 
31 #define NUM_OF_DWORDS_RX_MPDU_END 2
32 
33 struct rx_mpdu_end {
34              uint32_t rxpcu_mpdu_filter_in_category   :  2, //[1:0]
35                       sw_frame_group_id               :  7, //[8:2]
36                       reserved_0                      :  7, //[15:9]
37                       phy_ppdu_id                     : 16; //[31:16]
38              uint32_t reserved_1a                     : 11, //[10:0]
39                       unsup_ktype_short_frame         :  1, //[11]
40                       rx_in_tx_decrypt_byp            :  1, //[12]
41                       overflow_err                    :  1, //[13]
42                       mpdu_length_err                 :  1, //[14]
43                       tkip_mic_err                    :  1, //[15]
44                       decrypt_err                     :  1, //[16]
45                       unencrypted_frame_err           :  1, //[17]
46                       pn_fields_contain_valid_info    :  1, //[18]
47                       fcs_err                         :  1, //[19]
48                       msdu_length_err                 :  1, //[20]
49                       rxdma0_destination_ring         :  2, //[22:21]
50                       rxdma1_destination_ring         :  2, //[24:23]
51                       decrypt_status_code             :  3, //[27:25]
52                       rx_bitmap_not_updated           :  1, //[28]
53                       reserved_1b                     :  3; //[31:29]
54 };
55 
56 /*
57 
58 rxpcu_mpdu_filter_in_category
59 
60 			Field indicates what the reason was that this MPDU frame
61 			was allowed to come into the receive path by RXPCU
62 
63 			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
64 			frame filter programming of rxpcu
65 
66 			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
67 			regular frame filter and would have been dropped, were it
68 			not for the frame fitting into the 'monitor_client'
69 			category.
70 
71 			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
72 			regular frame filter and also did not pass the
73 			rxpcu_monitor_client filter. It would have been dropped
74 			accept that it did pass the 'monitor_other' category.
75 
76 			<legal 0-2>
77 
78 sw_frame_group_id
79 
80 			SW processes frames based on certain classifications.
81 			This field indicates to what sw classification this MPDU is
82 			mapped.
83 
84 			The classification is given in priority order
85 
86 
87 
88 			<enum 0 sw_frame_group_NDP_frame>
89 
90 
91 
92 			<enum 1 sw_frame_group_Multicast_data>
93 
94 			<enum 2 sw_frame_group_Unicast_data>
95 
96 			<enum 3 sw_frame_group_Null_data > This includes mpdus
97 			of type Data Null as well as QoS Data Null
98 
99 
100 
101 			<enum 4 sw_frame_group_mgmt_0000 >
102 
103 			<enum 5 sw_frame_group_mgmt_0001 >
104 
105 			<enum 6 sw_frame_group_mgmt_0010 >
106 
107 			<enum 7 sw_frame_group_mgmt_0011 >
108 
109 			<enum 8 sw_frame_group_mgmt_0100 >
110 
111 			<enum 9 sw_frame_group_mgmt_0101 >
112 
113 			<enum 10 sw_frame_group_mgmt_0110 >
114 
115 			<enum 11 sw_frame_group_mgmt_0111 >
116 
117 			<enum 12 sw_frame_group_mgmt_1000 >
118 
119 			<enum 13 sw_frame_group_mgmt_1001 >
120 
121 			<enum 14 sw_frame_group_mgmt_1010 >
122 
123 			<enum 15 sw_frame_group_mgmt_1011 >
124 
125 			<enum 16 sw_frame_group_mgmt_1100 >
126 
127 			<enum 17 sw_frame_group_mgmt_1101 >
128 
129 			<enum 18 sw_frame_group_mgmt_1110 >
130 
131 			<enum 19 sw_frame_group_mgmt_1111 >
132 
133 
134 
135 			<enum 20 sw_frame_group_ctrl_0000 >
136 
137 			<enum 21 sw_frame_group_ctrl_0001 >
138 
139 			<enum 22 sw_frame_group_ctrl_0010 >
140 
141 			<enum 23 sw_frame_group_ctrl_0011 >
142 
143 			<enum 24 sw_frame_group_ctrl_0100 >
144 
145 			<enum 25 sw_frame_group_ctrl_0101 >
146 
147 			<enum 26 sw_frame_group_ctrl_0110 >
148 
149 			<enum 27 sw_frame_group_ctrl_0111 >
150 
151 			<enum 28 sw_frame_group_ctrl_1000 >
152 
153 			<enum 29 sw_frame_group_ctrl_1001 >
154 
155 			<enum 30 sw_frame_group_ctrl_1010 >
156 
157 			<enum 31 sw_frame_group_ctrl_1011 >
158 
159 			<enum 32 sw_frame_group_ctrl_1100 >
160 
161 			<enum 33 sw_frame_group_ctrl_1101 >
162 
163 			<enum 34 sw_frame_group_ctrl_1110 >
164 
165 			<enum 35 sw_frame_group_ctrl_1111 >
166 
167 
168 
169 			<enum 36 sw_frame_group_unsupported> This covers type 3
170 			and protocol version != 0
171 
172 
173 
174 
175 
176 
177 			<legal 0-37>
178 
179 reserved_0
180 
181 			<legal 0>
182 
183 phy_ppdu_id
184 
185 			A ppdu counter value that PHY increments for every PPDU
186 			received. The counter value wraps around
187 
188 			<legal all>
189 
190 reserved_1a
191 
192 			<legal 0>
193 
194 unsup_ktype_short_frame
195 
196 			This bit will be '1' when WEP or TKIP or WAPI key type
197 			is received for 11ah short frame.  Crypto will bypass the
198 			received packet without decryption to RxOLE after setting
199 			this bit.
200 
201 rx_in_tx_decrypt_byp
202 
203 			Indicates that RX packet is not decrypted as Crypto is
204 			busy with TX packet processing.
205 
206 overflow_err
207 
208 			RXPCU Receive FIFO ran out of space to receive the full
209 			MPDU. Therefor this MPDU is terminated early and is thus
210 			corrupted.
211 
212 
213 
214 			This MPDU will not be ACKed.
215 
216 			RXPCU might still be able to correctly receive the
217 			following MPDUs in the PPDU if enough fifo space became
218 			available in time
219 
220 mpdu_length_err
221 
222 			Set by RXPCU if the expected MPDU length does not
223 			correspond with the actually received number of bytes in the
224 			MPDU.
225 
226 tkip_mic_err
227 
228 			Set by RX CRYPTO when CRYPTO detected a TKIP MIC error
229 			for this MPDU
230 
231 decrypt_err
232 
233 			Set by RX CRYPTO when CRYPTO detected a decrypt error
234 			for this MPDU or CRYPTO received an encrypted frame, but did
235 			not get a valid corresponding key id in the peer entry.
236 
237 unencrypted_frame_err
238 
239 			Set by RX CRYPTO when CRYPTO detected an unencrypted
240 			frame while in the peer entry field
241 			'All_frames_shall_be_encrypted' is set.
242 
243 pn_fields_contain_valid_info
244 
245 			Set by RX CRYPTO to indicate that there is a valid PN
246 			field present in this MPDU
247 
248 fcs_err
249 
250 			Set by RXPCU when there is an FCS error detected for
251 			this MPDU
252 
253 			NOTE that when this field is set, all other (error)
254 			field settings should be ignored as modules could have made
255 			wrong decisions based on the corrupted data.
256 
257 msdu_length_err
258 
259 			Set by RXOLE when there is an msdu length error detected
260 			in at least 1 of the MSDUs embedded within the MPDU
261 
262 rxdma0_destination_ring
263 
264 			The ring to which RXDMA0 shall push the frame, assuming
265 			no MPDU level errors are detected. In case of MPDU level
266 			errors, RXDMA0 might change the RXDMA0 destination
267 
268 
269 
270 			<enum 0  rxdma_release_ring >  RXDMA0 shall push the
271 			frame to the Release ring. Effectively this means the frame
272 			needs to be dropped.
273 
274 
275 
276 			<enum 1  rxdma2fw_ring >  RXDMA0 shall push the frame to
277 			the FW ring
278 
279 
280 
281 			<enum 2  rxdma2sw_ring >  RXDMA0 shall push the frame to
282 			the SW ring
283 
284 
285 
286 			<enum 3  rxdma2reo_ring >  RXDMA0 shall push the frame
287 			to the REO entrance ring
288 
289 
290 
291 			<legal all>
292 
293 rxdma1_destination_ring
294 
295 			The ring to which RXDMA1 shall push the frame, assuming
296 			no MPDU level errors are detected. In case of MPDU level
297 			errors, RXDMA1 might change the RXDMA destination
298 
299 
300 
301 			<enum 0  rxdma_release_ring >  RXDMA1 shall push the
302 			frame to the Release ring. Effectively this means the frame
303 			needs to be dropped.
304 
305 
306 
307 			<enum 1  rxdma2fw_ring >  RXDMA1 shall push the frame to
308 			the FW ring
309 
310 
311 
312 			<enum 2  rxdma2sw_ring >  RXDMA1 shall push the frame to
313 			the SW ring
314 
315 
316 
317 			<enum 3  rxdma2reo_ring >  RXDMA1 shall push the frame
318 			to the REO entrance ring
319 
320 
321 
322 			<legal all>
323 
324 decrypt_status_code
325 
326 			Field provides insight into the decryption performed
327 
328 
329 
330 			<enum 0 decrypt_ok> Frame had protection enabled and
331 			decrypted properly
332 
333 			<enum 1 decrypt_unprotected_frame > Frame is unprotected
334 			and hence bypassed
335 
336 			<enum 2 decrypt_data_err > Frame has protection enabled
337 			and could not be properly decrypted due to MIC/ICV mismatch
338 			etc.
339 
340 			<enum 3 decrypt_key_invalid > Frame has protection
341 			enabled but the key that was required to decrypt this frame
342 			was not valid
343 
344 			<enum 4 decrypt_peer_entry_invalid > Frame has
345 			protection enabled but the key that was required to decrypt
346 			this frame was not valid
347 
348 			<enum 5 decrypt_other > Reserved for other indications
349 
350 
351 
352 			<legal 0 - 5>
353 
354 rx_bitmap_not_updated
355 
356 			Frame is received, but RXPCU could not update the
357 			receive bitmap due to (temporary) fifo contraints.
358 
359 			<legal all>
360 
361 reserved_1b
362 
363 			<legal 0>
364 */
365 
366 
367 /* Description		RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY
368 
369 			Field indicates what the reason was that this MPDU frame
370 			was allowed to come into the receive path by RXPCU
371 
372 			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
373 			frame filter programming of rxpcu
374 
375 			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
376 			regular frame filter and would have been dropped, were it
377 			not for the frame fitting into the 'monitor_client'
378 			category.
379 
380 			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
381 			regular frame filter and also did not pass the
382 			rxpcu_monitor_client filter. It would have been dropped
383 			accept that it did pass the 'monitor_other' category.
384 
385 			<legal 0-2>
386 */
387 #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET           0x00000000
388 #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB              0
389 #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK             0x00000003
390 
391 /* Description		RX_MPDU_END_0_SW_FRAME_GROUP_ID
392 
393 			SW processes frames based on certain classifications.
394 			This field indicates to what sw classification this MPDU is
395 			mapped.
396 
397 			The classification is given in priority order
398 
399 
400 
401 			<enum 0 sw_frame_group_NDP_frame>
402 
403 
404 
405 			<enum 1 sw_frame_group_Multicast_data>
406 
407 			<enum 2 sw_frame_group_Unicast_data>
408 
409 			<enum 3 sw_frame_group_Null_data > This includes mpdus
410 			of type Data Null as well as QoS Data Null
411 
412 
413 
414 			<enum 4 sw_frame_group_mgmt_0000 >
415 
416 			<enum 5 sw_frame_group_mgmt_0001 >
417 
418 			<enum 6 sw_frame_group_mgmt_0010 >
419 
420 			<enum 7 sw_frame_group_mgmt_0011 >
421 
422 			<enum 8 sw_frame_group_mgmt_0100 >
423 
424 			<enum 9 sw_frame_group_mgmt_0101 >
425 
426 			<enum 10 sw_frame_group_mgmt_0110 >
427 
428 			<enum 11 sw_frame_group_mgmt_0111 >
429 
430 			<enum 12 sw_frame_group_mgmt_1000 >
431 
432 			<enum 13 sw_frame_group_mgmt_1001 >
433 
434 			<enum 14 sw_frame_group_mgmt_1010 >
435 
436 			<enum 15 sw_frame_group_mgmt_1011 >
437 
438 			<enum 16 sw_frame_group_mgmt_1100 >
439 
440 			<enum 17 sw_frame_group_mgmt_1101 >
441 
442 			<enum 18 sw_frame_group_mgmt_1110 >
443 
444 			<enum 19 sw_frame_group_mgmt_1111 >
445 
446 
447 
448 			<enum 20 sw_frame_group_ctrl_0000 >
449 
450 			<enum 21 sw_frame_group_ctrl_0001 >
451 
452 			<enum 22 sw_frame_group_ctrl_0010 >
453 
454 			<enum 23 sw_frame_group_ctrl_0011 >
455 
456 			<enum 24 sw_frame_group_ctrl_0100 >
457 
458 			<enum 25 sw_frame_group_ctrl_0101 >
459 
460 			<enum 26 sw_frame_group_ctrl_0110 >
461 
462 			<enum 27 sw_frame_group_ctrl_0111 >
463 
464 			<enum 28 sw_frame_group_ctrl_1000 >
465 
466 			<enum 29 sw_frame_group_ctrl_1001 >
467 
468 			<enum 30 sw_frame_group_ctrl_1010 >
469 
470 			<enum 31 sw_frame_group_ctrl_1011 >
471 
472 			<enum 32 sw_frame_group_ctrl_1100 >
473 
474 			<enum 33 sw_frame_group_ctrl_1101 >
475 
476 			<enum 34 sw_frame_group_ctrl_1110 >
477 
478 			<enum 35 sw_frame_group_ctrl_1111 >
479 
480 
481 
482 			<enum 36 sw_frame_group_unsupported> This covers type 3
483 			and protocol version != 0
484 
485 
486 
487 
488 
489 
490 			<legal 0-37>
491 */
492 #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_OFFSET                       0x00000000
493 #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_LSB                          2
494 #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_MASK                         0x000001fc
495 
496 /* Description		RX_MPDU_END_0_RESERVED_0
497 
498 			<legal 0>
499 */
500 #define RX_MPDU_END_0_RESERVED_0_OFFSET                              0x00000000
501 #define RX_MPDU_END_0_RESERVED_0_LSB                                 9
502 #define RX_MPDU_END_0_RESERVED_0_MASK                                0x0000fe00
503 
504 /* Description		RX_MPDU_END_0_PHY_PPDU_ID
505 
506 			A ppdu counter value that PHY increments for every PPDU
507 			received. The counter value wraps around
508 
509 			<legal all>
510 */
511 #define RX_MPDU_END_0_PHY_PPDU_ID_OFFSET                             0x00000000
512 #define RX_MPDU_END_0_PHY_PPDU_ID_LSB                                16
513 #define RX_MPDU_END_0_PHY_PPDU_ID_MASK                               0xffff0000
514 
515 /* Description		RX_MPDU_END_1_RESERVED_1A
516 
517 			<legal 0>
518 */
519 #define RX_MPDU_END_1_RESERVED_1A_OFFSET                             0x00000004
520 #define RX_MPDU_END_1_RESERVED_1A_LSB                                0
521 #define RX_MPDU_END_1_RESERVED_1A_MASK                               0x000007ff
522 
523 /* Description		RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME
524 
525 			This bit will be '1' when WEP or TKIP or WAPI key type
526 			is received for 11ah short frame.  Crypto will bypass the
527 			received packet without decryption to RxOLE after setting
528 			this bit.
529 */
530 #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_OFFSET                 0x00000004
531 #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_LSB                    11
532 #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_MASK                   0x00000800
533 
534 /* Description		RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP
535 
536 			Indicates that RX packet is not decrypted as Crypto is
537 			busy with TX packet processing.
538 */
539 #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET                    0x00000004
540 #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB                       12
541 #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK                      0x00001000
542 
543 /* Description		RX_MPDU_END_1_OVERFLOW_ERR
544 
545 			RXPCU Receive FIFO ran out of space to receive the full
546 			MPDU. Therefor this MPDU is terminated early and is thus
547 			corrupted.
548 
549 
550 
551 			This MPDU will not be ACKed.
552 
553 			RXPCU might still be able to correctly receive the
554 			following MPDUs in the PPDU if enough fifo space became
555 			available in time
556 */
557 #define RX_MPDU_END_1_OVERFLOW_ERR_OFFSET                            0x00000004
558 #define RX_MPDU_END_1_OVERFLOW_ERR_LSB                               13
559 #define RX_MPDU_END_1_OVERFLOW_ERR_MASK                              0x00002000
560 
561 /* Description		RX_MPDU_END_1_MPDU_LENGTH_ERR
562 
563 			Set by RXPCU if the expected MPDU length does not
564 			correspond with the actually received number of bytes in the
565 			MPDU.
566 */
567 #define RX_MPDU_END_1_MPDU_LENGTH_ERR_OFFSET                         0x00000004
568 #define RX_MPDU_END_1_MPDU_LENGTH_ERR_LSB                            14
569 #define RX_MPDU_END_1_MPDU_LENGTH_ERR_MASK                           0x00004000
570 
571 /* Description		RX_MPDU_END_1_TKIP_MIC_ERR
572 
573 			Set by RX CRYPTO when CRYPTO detected a TKIP MIC error
574 			for this MPDU
575 */
576 #define RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET                            0x00000004
577 #define RX_MPDU_END_1_TKIP_MIC_ERR_LSB                               15
578 #define RX_MPDU_END_1_TKIP_MIC_ERR_MASK                              0x00008000
579 
580 /* Description		RX_MPDU_END_1_DECRYPT_ERR
581 
582 			Set by RX CRYPTO when CRYPTO detected a decrypt error
583 			for this MPDU or CRYPTO received an encrypted frame, but did
584 			not get a valid corresponding key id in the peer entry.
585 */
586 #define RX_MPDU_END_1_DECRYPT_ERR_OFFSET                             0x00000004
587 #define RX_MPDU_END_1_DECRYPT_ERR_LSB                                16
588 #define RX_MPDU_END_1_DECRYPT_ERR_MASK                               0x00010000
589 
590 /* Description		RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR
591 
592 			Set by RX CRYPTO when CRYPTO detected an unencrypted
593 			frame while in the peer entry field
594 			'All_frames_shall_be_encrypted' is set.
595 */
596 #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_OFFSET                   0x00000004
597 #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_LSB                      17
598 #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_MASK                     0x00020000
599 
600 /* Description		RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO
601 
602 			Set by RX CRYPTO to indicate that there is a valid PN
603 			field present in this MPDU
604 */
605 #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET            0x00000004
606 #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_LSB               18
607 #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_MASK              0x00040000
608 
609 /* Description		RX_MPDU_END_1_FCS_ERR
610 
611 			Set by RXPCU when there is an FCS error detected for
612 			this MPDU
613 
614 			NOTE that when this field is set, all other (error)
615 			field settings should be ignored as modules could have made
616 			wrong decisions based on the corrupted data.
617 */
618 #define RX_MPDU_END_1_FCS_ERR_OFFSET                                 0x00000004
619 #define RX_MPDU_END_1_FCS_ERR_LSB                                    19
620 #define RX_MPDU_END_1_FCS_ERR_MASK                                   0x00080000
621 
622 /* Description		RX_MPDU_END_1_MSDU_LENGTH_ERR
623 
624 			Set by RXOLE when there is an msdu length error detected
625 			in at least 1 of the MSDUs embedded within the MPDU
626 */
627 #define RX_MPDU_END_1_MSDU_LENGTH_ERR_OFFSET                         0x00000004
628 #define RX_MPDU_END_1_MSDU_LENGTH_ERR_LSB                            20
629 #define RX_MPDU_END_1_MSDU_LENGTH_ERR_MASK                           0x00100000
630 
631 /* Description		RX_MPDU_END_1_RXDMA0_DESTINATION_RING
632 
633 			The ring to which RXDMA0 shall push the frame, assuming
634 			no MPDU level errors are detected. In case of MPDU level
635 			errors, RXDMA0 might change the RXDMA0 destination
636 
637 
638 
639 			<enum 0  rxdma_release_ring >  RXDMA0 shall push the
640 			frame to the Release ring. Effectively this means the frame
641 			needs to be dropped.
642 
643 
644 
645 			<enum 1  rxdma2fw_ring >  RXDMA0 shall push the frame to
646 			the FW ring
647 
648 
649 
650 			<enum 2  rxdma2sw_ring >  RXDMA0 shall push the frame to
651 			the SW ring
652 
653 
654 
655 			<enum 3  rxdma2reo_ring >  RXDMA0 shall push the frame
656 			to the REO entrance ring
657 
658 
659 
660 			<legal all>
661 */
662 #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_OFFSET                 0x00000004
663 #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_LSB                    21
664 #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_MASK                   0x00600000
665 
666 /* Description		RX_MPDU_END_1_RXDMA1_DESTINATION_RING
667 
668 			The ring to which RXDMA1 shall push the frame, assuming
669 			no MPDU level errors are detected. In case of MPDU level
670 			errors, RXDMA1 might change the RXDMA destination
671 
672 
673 
674 			<enum 0  rxdma_release_ring >  RXDMA1 shall push the
675 			frame to the Release ring. Effectively this means the frame
676 			needs to be dropped.
677 
678 
679 
680 			<enum 1  rxdma2fw_ring >  RXDMA1 shall push the frame to
681 			the FW ring
682 
683 
684 
685 			<enum 2  rxdma2sw_ring >  RXDMA1 shall push the frame to
686 			the SW ring
687 
688 
689 
690 			<enum 3  rxdma2reo_ring >  RXDMA1 shall push the frame
691 			to the REO entrance ring
692 
693 
694 
695 			<legal all>
696 */
697 #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_OFFSET                 0x00000004
698 #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_LSB                    23
699 #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_MASK                   0x01800000
700 
701 /* Description		RX_MPDU_END_1_DECRYPT_STATUS_CODE
702 
703 			Field provides insight into the decryption performed
704 
705 
706 
707 			<enum 0 decrypt_ok> Frame had protection enabled and
708 			decrypted properly
709 
710 			<enum 1 decrypt_unprotected_frame > Frame is unprotected
711 			and hence bypassed
712 
713 			<enum 2 decrypt_data_err > Frame has protection enabled
714 			and could not be properly decrypted due to MIC/ICV mismatch
715 			etc.
716 
717 			<enum 3 decrypt_key_invalid > Frame has protection
718 			enabled but the key that was required to decrypt this frame
719 			was not valid
720 
721 			<enum 4 decrypt_peer_entry_invalid > Frame has
722 			protection enabled but the key that was required to decrypt
723 			this frame was not valid
724 
725 			<enum 5 decrypt_other > Reserved for other indications
726 
727 
728 
729 			<legal 0 - 5>
730 */
731 #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_OFFSET                     0x00000004
732 #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_LSB                        25
733 #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_MASK                       0x0e000000
734 
735 /* Description		RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED
736 
737 			Frame is received, but RXPCU could not update the
738 			receive bitmap due to (temporary) fifo contraints.
739 
740 			<legal all>
741 */
742 #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_OFFSET                   0x00000004
743 #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_LSB                      28
744 #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_MASK                     0x10000000
745 
746 /* Description		RX_MPDU_END_1_RESERVED_1B
747 
748 			<legal 0>
749 */
750 #define RX_MPDU_END_1_RESERVED_1B_OFFSET                             0x00000004
751 #define RX_MPDU_END_1_RESERVED_1B_LSB                                29
752 #define RX_MPDU_END_1_RESERVED_1B_MASK                               0xe0000000
753 
754 
755 #endif // _RX_MPDU_END_H_
756