1 /* 2 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 /////////////////////////////////////////////////////////////////////////////////////////////// 18 // reo_reg_seq_hwioreg.h : automatically generated by Autoseq 3.8 7/1/2019 19 // User Name:pbechana 20 // 21 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 22 // 23 /////////////////////////////////////////////////////////////////////////////////////////////// 24 25 #ifndef __REO_REG_SEQ_REG_H__ 26 #define __REO_REG_SEQ_REG_H__ 27 28 #include "seq_hwio.h" 29 #include "reo_reg_seq_hwiobase.h" 30 #ifdef SCALE_INCLUDES 31 #include "HALhwio.h" 32 #else 33 #include "msmhwio.h" 34 #endif 35 36 37 /////////////////////////////////////////////////////////////////////////////////////////////// 38 // Register Data for Block REO_REG 39 /////////////////////////////////////////////////////////////////////////////////////////////// 40 41 //// Register REO_R0_GENERAL_ENABLE //// 42 43 #define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) (x+0x00000000) 44 #define HWIO_REO_R0_GENERAL_ENABLE_PHYS(x) (x+0x00000000) 45 #define HWIO_REO_R0_GENERAL_ENABLE_RMSK 0x7fffffff 46 #define HWIO_REO_R0_GENERAL_ENABLE_SHFT 0 47 #define HWIO_REO_R0_GENERAL_ENABLE_IN(x) \ 48 in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), HWIO_REO_R0_GENERAL_ENABLE_RMSK) 49 #define HWIO_REO_R0_GENERAL_ENABLE_INM(x, mask) \ 50 in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask) 51 #define HWIO_REO_R0_GENERAL_ENABLE_OUT(x, val) \ 52 out_dword( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), val) 53 #define HWIO_REO_R0_GENERAL_ENABLE_OUTM(x, mask, val) \ 54 do {\ 55 HWIO_INTLOCK(); \ 56 out_dword_masked_ns(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask, val, HWIO_REO_R0_GENERAL_ENABLE_IN(x)); \ 57 HWIO_INTFREE();\ 58 } while (0) 59 60 #define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_BMSK 0x40000000 61 #define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_SHFT 0x1e 62 63 #define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_BMSK 0x20000000 64 #define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_SHFT 0x1d 65 66 #define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_BMSK 0x1c000000 67 #define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_SHFT 0x1a 68 69 #define HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK 0x03800000 70 #define HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_SHFT 0x17 71 72 #define HWIO_REO_R0_GENERAL_ENABLE_SW2REO1_RING_ENABLE_BMSK 0x00400000 73 #define HWIO_REO_R0_GENERAL_ENABLE_SW2REO1_RING_ENABLE_SHFT 0x16 74 75 #define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_BMSK 0x00200000 76 #define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_SHFT 0x15 77 78 #define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_BMSK 0x00100000 79 #define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_SHFT 0x14 80 81 #define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_BMSK 0x00080000 82 #define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_SHFT 0x13 83 84 #define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_BMSK 0x00040000 85 #define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_SHFT 0x12 86 87 #define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_BMSK 0x00020000 88 #define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_SHFT 0x11 89 90 #define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_BMSK 0x00010000 91 #define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_SHFT 0x10 92 93 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_BMSK 0x00008000 94 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_SHFT 0xf 95 96 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_BMSK 0x00004000 97 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_SHFT 0xe 98 99 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_BMSK 0x00002000 100 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_SHFT 0xd 101 102 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_BMSK 0x00001000 103 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_SHFT 0xc 104 105 #define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_BMSK 0x00000800 106 #define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_SHFT 0xb 107 108 #define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_BMSK 0x00000700 109 #define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_SHFT 0x8 110 111 #define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_BMSK 0x00000080 112 #define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_SHFT 0x7 113 114 #define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_BMSK 0x00000070 115 #define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_SHFT 0x4 116 117 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK 0x00000008 118 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT 0x3 119 120 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK 0x00000004 121 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT 0x2 122 123 #define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_BMSK 0x00000002 124 #define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_SHFT 0x1 125 126 #define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_BMSK 0x00000001 127 #define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_SHFT 0x0 128 129 //// Register REO_R0_DESTINATION_RING_CTRL_IX_0 //// 130 131 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x) (x+0x00000004) 132 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_PHYS(x) (x+0x00000004) 133 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK 0xffffff00 134 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_SHFT 8 135 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x) \ 136 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK) 137 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_INM(x, mask) \ 138 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask) 139 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUT(x, val) \ 140 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), val) 141 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUTM(x, mask, val) \ 142 do {\ 143 HWIO_INTLOCK(); \ 144 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x)); \ 145 HWIO_INTFREE();\ 146 } while (0) 147 148 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_BMSK 0xe0000000 149 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 0x1d 150 151 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_BMSK 0x1c000000 152 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 0x1a 153 154 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_BMSK 0x03800000 155 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 0x17 156 157 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_BMSK 0x00700000 158 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 0x14 159 160 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_BMSK 0x000e0000 161 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 0x11 162 163 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_BMSK 0x0001c000 164 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 0xe 165 166 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_BMSK 0x00003800 167 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 0xb 168 169 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_BMSK 0x00000700 170 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0x8 171 172 //// Register REO_R0_DESTINATION_RING_CTRL_IX_1 //// 173 174 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x) (x+0x00000008) 175 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_PHYS(x) (x+0x00000008) 176 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK 0xffffff00 177 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_SHFT 8 178 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x) \ 179 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK) 180 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_INM(x, mask) \ 181 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask) 182 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUT(x, val) \ 183 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), val) 184 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUTM(x, mask, val) \ 185 do {\ 186 HWIO_INTLOCK(); \ 187 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x)); \ 188 HWIO_INTFREE();\ 189 } while (0) 190 191 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_BMSK 0xe0000000 192 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_SHFT 0x1d 193 194 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_BMSK 0x1c000000 195 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_SHFT 0x1a 196 197 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_BMSK 0x03800000 198 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_SHFT 0x17 199 200 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_BMSK 0x00700000 201 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_SHFT 0x14 202 203 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_BMSK 0x000e0000 204 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_SHFT 0x11 205 206 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_BMSK 0x0001c000 207 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_SHFT 0xe 208 209 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_BMSK 0x00003800 210 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_SHFT 0xb 211 212 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_BMSK 0x00000700 213 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_SHFT 0x8 214 215 //// Register REO_R0_DESTINATION_RING_CTRL_IX_2 //// 216 217 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) (x+0x0000000c) 218 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_PHYS(x) (x+0x0000000c) 219 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK 0xffffff00 220 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_SHFT 8 221 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x) \ 222 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK) 223 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_INM(x, mask) \ 224 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask) 225 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUT(x, val) \ 226 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), val) 227 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUTM(x, mask, val) \ 228 do {\ 229 HWIO_INTLOCK(); \ 230 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x)); \ 231 HWIO_INTFREE();\ 232 } while (0) 233 234 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_BMSK 0xe0000000 235 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 0x1d 236 237 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_BMSK 0x1c000000 238 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 0x1a 239 240 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_BMSK 0x03800000 241 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 0x17 242 243 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_BMSK 0x00700000 244 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 0x14 245 246 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_BMSK 0x000e0000 247 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 0x11 248 249 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_BMSK 0x0001c000 250 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 0xe 251 252 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_BMSK 0x00003800 253 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 0xb 254 255 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_BMSK 0x00000700 256 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0x8 257 258 //// Register REO_R0_DESTINATION_RING_CTRL_IX_3 //// 259 260 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) (x+0x00000010) 261 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_PHYS(x) (x+0x00000010) 262 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK 0xffffff00 263 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_SHFT 8 264 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x) \ 265 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK) 266 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_INM(x, mask) \ 267 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask) 268 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUT(x, val) \ 269 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), val) 270 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUTM(x, mask, val) \ 271 do {\ 272 HWIO_INTLOCK(); \ 273 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x)); \ 274 HWIO_INTFREE();\ 275 } while (0) 276 277 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_BMSK 0xe0000000 278 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 0x1d 279 280 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_BMSK 0x1c000000 281 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 0x1a 282 283 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_BMSK 0x03800000 284 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 0x17 285 286 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_BMSK 0x00700000 287 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 0x14 288 289 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_BMSK 0x000e0000 290 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 0x11 291 292 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_BMSK 0x0001c000 293 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 0xe 294 295 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_BMSK 0x00003800 296 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 0xb 297 298 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_BMSK 0x00000700 299 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0x8 300 301 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_0 //// 302 303 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x) (x+0x00000014) 304 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_PHYS(x) (x+0x00000014) 305 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK 0xffffff00 306 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_SHFT 8 307 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x) \ 308 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK) 309 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_INM(x, mask) \ 310 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask) 311 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUT(x, val) \ 312 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), val) 313 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUTM(x, mask, val) \ 314 do {\ 315 HWIO_INTLOCK(); \ 316 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x)); \ 317 HWIO_INTFREE();\ 318 } while (0) 319 320 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_BMSK 0xe0000000 321 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_SHFT 0x1d 322 323 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_BMSK 0x1c000000 324 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_SHFT 0x1a 325 326 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_BMSK 0x03800000 327 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_SHFT 0x17 328 329 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_BMSK 0x00700000 330 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_SHFT 0x14 331 332 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_BMSK 0x000e0000 333 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_SHFT 0x11 334 335 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_BMSK 0x0001c000 336 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_SHFT 0xe 337 338 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_BMSK 0x00003800 339 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_SHFT 0xb 340 341 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK 0x00000700 342 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_SHFT 0x8 343 344 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_1 //// 345 346 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x) (x+0x00000018) 347 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_PHYS(x) (x+0x00000018) 348 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK 0xffffff00 349 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_SHFT 8 350 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x) \ 351 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK) 352 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_INM(x, mask) \ 353 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask) 354 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUT(x, val) \ 355 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), val) 356 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUTM(x, mask, val) \ 357 do {\ 358 HWIO_INTLOCK(); \ 359 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x)); \ 360 HWIO_INTFREE();\ 361 } while (0) 362 363 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_BMSK 0xe0000000 364 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_SHFT 0x1d 365 366 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_BMSK 0x1c000000 367 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_SHFT 0x1a 368 369 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_BMSK 0x03800000 370 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_SHFT 0x17 371 372 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_BMSK 0x00700000 373 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_SHFT 0x14 374 375 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_BMSK 0x000e0000 376 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_SHFT 0x11 377 378 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_BMSK 0x0001c000 379 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_SHFT 0xe 380 381 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_BMSK 0x00003800 382 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_SHFT 0xb 383 384 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_BMSK 0x00000700 385 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_SHFT 0x8 386 387 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_2 //// 388 389 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x) (x+0x0000001c) 390 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_PHYS(x) (x+0x0000001c) 391 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK 0xffffff00 392 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_SHFT 8 393 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x) \ 394 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK) 395 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_INM(x, mask) \ 396 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask) 397 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUT(x, val) \ 398 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), val) 399 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUTM(x, mask, val) \ 400 do {\ 401 HWIO_INTLOCK(); \ 402 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x)); \ 403 HWIO_INTFREE();\ 404 } while (0) 405 406 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_BMSK 0xe0000000 407 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_SHFT 0x1d 408 409 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_BMSK 0x1c000000 410 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_SHFT 0x1a 411 412 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_BMSK 0x03800000 413 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_SHFT 0x17 414 415 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_BMSK 0x00700000 416 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_SHFT 0x14 417 418 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_BMSK 0x000e0000 419 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_SHFT 0x11 420 421 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_BMSK 0x0001c000 422 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_SHFT 0xe 423 424 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_BMSK 0x00003800 425 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_SHFT 0xb 426 427 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_BMSK 0x00000700 428 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_SHFT 0x8 429 430 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_3 //// 431 432 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x) (x+0x00000020) 433 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_PHYS(x) (x+0x00000020) 434 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK 0xffffff00 435 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_SHFT 8 436 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x) \ 437 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK) 438 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_INM(x, mask) \ 439 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask) 440 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUT(x, val) \ 441 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), val) 442 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUTM(x, mask, val) \ 443 do {\ 444 HWIO_INTLOCK(); \ 445 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x)); \ 446 HWIO_INTFREE();\ 447 } while (0) 448 449 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_BMSK 0xe0000000 450 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_SHFT 0x1d 451 452 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_BMSK 0x1c000000 453 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_SHFT 0x1a 454 455 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_BMSK 0x03800000 456 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_SHFT 0x17 457 458 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_BMSK 0x00700000 459 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_SHFT 0x14 460 461 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_BMSK 0x000e0000 462 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_SHFT 0x11 463 464 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_BMSK 0x0001c000 465 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_SHFT 0xe 466 467 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_BMSK 0x00003800 468 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_SHFT 0xb 469 470 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_BMSK 0x00000700 471 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_SHFT 0x8 472 473 //// Register REO_R0_TIMESTAMP //// 474 475 #define HWIO_REO_R0_TIMESTAMP_ADDR(x) (x+0x00000024) 476 #define HWIO_REO_R0_TIMESTAMP_PHYS(x) (x+0x00000024) 477 #define HWIO_REO_R0_TIMESTAMP_RMSK 0xffffffff 478 #define HWIO_REO_R0_TIMESTAMP_SHFT 0 479 #define HWIO_REO_R0_TIMESTAMP_IN(x) \ 480 in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), HWIO_REO_R0_TIMESTAMP_RMSK) 481 #define HWIO_REO_R0_TIMESTAMP_INM(x, mask) \ 482 in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), mask) 483 #define HWIO_REO_R0_TIMESTAMP_OUT(x, val) \ 484 out_dword( HWIO_REO_R0_TIMESTAMP_ADDR(x), val) 485 #define HWIO_REO_R0_TIMESTAMP_OUTM(x, mask, val) \ 486 do {\ 487 HWIO_INTLOCK(); \ 488 out_dword_masked_ns(HWIO_REO_R0_TIMESTAMP_ADDR(x), mask, val, HWIO_REO_R0_TIMESTAMP_IN(x)); \ 489 HWIO_INTFREE();\ 490 } while (0) 491 492 #define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_BMSK 0xffffffff 493 #define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_SHFT 0x0 494 495 //// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_0 //// 496 497 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) (x+0x00000028) 498 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_PHYS(x) (x+0x00000028) 499 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK 0x3fffffff 500 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_SHFT 0 501 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x) \ 502 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK) 503 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_INM(x, mask) \ 504 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask) 505 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUT(x, val) \ 506 out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), val) 507 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUTM(x, mask, val) \ 508 do {\ 509 HWIO_INTLOCK(); \ 510 out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x)); \ 511 HWIO_INTFREE();\ 512 } while (0) 513 514 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_9_BMSK 0x38000000 515 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_9_SHFT 0x1b 516 517 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_8_BMSK 0x07000000 518 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_8_SHFT 0x18 519 520 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0x00e00000 521 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 0x15 522 523 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0x001c0000 524 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 0x12 525 526 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0x00038000 527 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 0xf 528 529 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0x00007000 530 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 0xc 531 532 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0x00000e00 533 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 0x9 534 535 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0x000001c0 536 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 0x6 537 538 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0x00000038 539 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 0x3 540 541 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0x00000007 542 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0x0 543 544 //// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_1 //// 545 546 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) (x+0x0000002c) 547 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_PHYS(x) (x+0x0000002c) 548 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK 0x0003ffff 549 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_SHFT 0 550 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x) \ 551 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK) 552 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_INM(x, mask) \ 553 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask) 554 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUT(x, val) \ 555 out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), val) 556 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUTM(x, mask, val) \ 557 do {\ 558 HWIO_INTLOCK(); \ 559 out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x)); \ 560 HWIO_INTFREE();\ 561 } while (0) 562 563 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_BMSK 0x00038000 564 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_SHFT 0xf 565 566 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_BMSK 0x00007000 567 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 0xc 568 569 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_BMSK 0x00000e00 570 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 0x9 571 572 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_BMSK 0x000001c0 573 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 0x6 574 575 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_BMSK 0x00000038 576 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 0x3 577 578 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_BMSK 0x00000007 579 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 0x0 580 581 //// Register REO_R0_IDLE_REQ_CTRL //// 582 583 #define HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x) (x+0x00000030) 584 #define HWIO_REO_R0_IDLE_REQ_CTRL_PHYS(x) (x+0x00000030) 585 #define HWIO_REO_R0_IDLE_REQ_CTRL_RMSK 0x00000003 586 #define HWIO_REO_R0_IDLE_REQ_CTRL_SHFT 0 587 #define HWIO_REO_R0_IDLE_REQ_CTRL_IN(x) \ 588 in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), HWIO_REO_R0_IDLE_REQ_CTRL_RMSK) 589 #define HWIO_REO_R0_IDLE_REQ_CTRL_INM(x, mask) \ 590 in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask) 591 #define HWIO_REO_R0_IDLE_REQ_CTRL_OUT(x, val) \ 592 out_dword( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), val) 593 #define HWIO_REO_R0_IDLE_REQ_CTRL_OUTM(x, mask, val) \ 594 do {\ 595 HWIO_INTLOCK(); \ 596 out_dword_masked_ns(HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask, val, HWIO_REO_R0_IDLE_REQ_CTRL_IN(x)); \ 597 HWIO_INTFREE();\ 598 } while (0) 599 600 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_BMSK 0x00000002 601 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_SHFT 0x1 602 603 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_BMSK 0x00000001 604 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_SHFT 0x0 605 606 //// Register REO_R0_RXDMA2REO0_RING_BASE_LSB //// 607 608 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x) (x+0x00000034) 609 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_PHYS(x) (x+0x00000034) 610 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK 0xffffffff 611 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_SHFT 0 612 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x) \ 613 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK) 614 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_INM(x, mask) \ 615 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask) 616 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUT(x, val) \ 617 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), val) 618 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUTM(x, mask, val) \ 619 do {\ 620 HWIO_INTLOCK(); \ 621 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x)); \ 622 HWIO_INTFREE();\ 623 } while (0) 624 625 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 626 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 627 628 //// Register REO_R0_RXDMA2REO0_RING_BASE_MSB //// 629 630 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x) (x+0x00000038) 631 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_PHYS(x) (x+0x00000038) 632 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK 0x00ffffff 633 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_SHFT 0 634 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x) \ 635 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK) 636 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_INM(x, mask) \ 637 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask) 638 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUT(x, val) \ 639 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), val) 640 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUTM(x, mask, val) \ 641 do {\ 642 HWIO_INTLOCK(); \ 643 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x)); \ 644 HWIO_INTFREE();\ 645 } while (0) 646 647 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 648 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_SHFT 0x8 649 650 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 651 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 652 653 //// Register REO_R0_RXDMA2REO0_RING_ID //// 654 655 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x) (x+0x0000003c) 656 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_PHYS(x) (x+0x0000003c) 657 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK 0x000000ff 658 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_SHFT 0 659 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x) \ 660 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK) 661 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_INM(x, mask) \ 662 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask) 663 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUT(x, val) \ 664 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), val) 665 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUTM(x, mask, val) \ 666 do {\ 667 HWIO_INTLOCK(); \ 668 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x)); \ 669 HWIO_INTFREE();\ 670 } while (0) 671 672 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 673 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_SHFT 0x0 674 675 //// Register REO_R0_RXDMA2REO0_RING_STATUS //// 676 677 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x) (x+0x00000040) 678 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_PHYS(x) (x+0x00000040) 679 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK 0xffffffff 680 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_SHFT 0 681 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x) \ 682 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK) 683 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_INM(x, mask) \ 684 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask) 685 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUT(x, val) \ 686 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), val) 687 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUTM(x, mask, val) \ 688 do {\ 689 HWIO_INTLOCK(); \ 690 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x)); \ 691 HWIO_INTFREE();\ 692 } while (0) 693 694 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 695 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 696 697 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 698 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 699 700 //// Register REO_R0_RXDMA2REO0_RING_MISC //// 701 702 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x) (x+0x00000044) 703 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_PHYS(x) (x+0x00000044) 704 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK 0x003fffff 705 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SHFT 0 706 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x) \ 707 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK) 708 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_INM(x, mask) \ 709 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask) 710 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUT(x, val) \ 711 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), val) 712 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUTM(x, mask, val) \ 713 do {\ 714 HWIO_INTLOCK(); \ 715 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x)); \ 716 HWIO_INTFREE();\ 717 } while (0) 718 719 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 720 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SPARE_CONTROL_SHFT 0xe 721 722 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 723 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 724 725 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 726 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 727 728 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 729 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 730 731 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 732 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_ENABLE_SHFT 0x6 733 734 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 735 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 736 737 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 738 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 739 740 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 741 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 742 743 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_BMSK 0x00000004 744 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_SHFT 0x2 745 746 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 747 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 748 749 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 750 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_SHFT 0x0 751 752 //// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB //// 753 754 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000050) 755 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000050) 756 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK 0xffffffff 757 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_SHFT 0 758 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x) \ 759 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK) 760 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_INM(x, mask) \ 761 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask) 762 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUT(x, val) \ 763 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), val) 764 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 765 do {\ 766 HWIO_INTLOCK(); \ 767 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x)); \ 768 HWIO_INTFREE();\ 769 } while (0) 770 771 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 772 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 773 774 //// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB //// 775 776 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000054) 777 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000054) 778 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK 0x000000ff 779 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_SHFT 0 780 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x) \ 781 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK) 782 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_INM(x, mask) \ 783 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask) 784 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUT(x, val) \ 785 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), val) 786 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 787 do {\ 788 HWIO_INTLOCK(); \ 789 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x)); \ 790 HWIO_INTFREE();\ 791 } while (0) 792 793 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 794 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 795 796 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0 //// 797 798 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000064) 799 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000064) 800 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 801 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 802 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 803 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK) 804 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 805 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 806 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 807 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 808 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 809 do {\ 810 HWIO_INTLOCK(); \ 811 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 812 HWIO_INTFREE();\ 813 } while (0) 814 815 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 816 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 817 818 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 819 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 820 821 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 822 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 823 824 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1 //// 825 826 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000068) 827 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000068) 828 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 829 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 830 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 831 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK) 832 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 833 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 834 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 835 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 836 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 837 do {\ 838 HWIO_INTLOCK(); \ 839 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 840 HWIO_INTFREE();\ 841 } while (0) 842 843 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 844 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 845 846 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS //// 847 848 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000006c) 849 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000006c) 850 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 851 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_SHFT 0 852 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x) \ 853 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK) 854 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 855 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 856 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 857 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), val) 858 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 859 do {\ 860 HWIO_INTLOCK(); \ 861 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x)); \ 862 HWIO_INTFREE();\ 863 } while (0) 864 865 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 866 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 867 868 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 869 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 870 871 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 872 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 873 874 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER //// 875 876 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000070) 877 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000070) 878 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 879 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 880 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 881 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK) 882 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 883 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 884 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 885 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 886 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 887 do {\ 888 HWIO_INTLOCK(); \ 889 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 890 HWIO_INTFREE();\ 891 } while (0) 892 893 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 894 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 895 896 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER //// 897 898 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000074) 899 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000074) 900 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 901 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 902 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 903 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK) 904 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 905 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 906 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 907 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 908 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 909 do {\ 910 HWIO_INTLOCK(); \ 911 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 912 HWIO_INTFREE();\ 913 } while (0) 914 915 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 916 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 917 918 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS //// 919 920 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000078) 921 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000078) 922 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 923 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 924 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 925 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK) 926 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 927 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 928 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 929 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 930 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 931 do {\ 932 HWIO_INTLOCK(); \ 933 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 934 HWIO_INTFREE();\ 935 } while (0) 936 937 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 938 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 939 940 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 941 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 942 943 //// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB //// 944 945 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000007c) 946 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000007c) 947 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK 0xffffffff 948 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_SHFT 0 949 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x) \ 950 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK) 951 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_INM(x, mask) \ 952 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask) 953 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUT(x, val) \ 954 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), val) 955 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 956 do {\ 957 HWIO_INTLOCK(); \ 958 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x)); \ 959 HWIO_INTFREE();\ 960 } while (0) 961 962 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 963 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 964 965 //// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB //// 966 967 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000080) 968 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000080) 969 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK 0x000001ff 970 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_SHFT 0 971 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x) \ 972 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK) 973 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_INM(x, mask) \ 974 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask) 975 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUT(x, val) \ 976 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), val) 977 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 978 do {\ 979 HWIO_INTLOCK(); \ 980 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x)); \ 981 HWIO_INTFREE();\ 982 } while (0) 983 984 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 985 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 986 987 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 988 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 989 990 //// Register REO_R0_RXDMA2REO0_RING_MSI1_DATA //// 991 992 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x) (x+0x00000084) 993 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_PHYS(x) (x+0x00000084) 994 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK 0xffffffff 995 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_SHFT 0 996 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x) \ 997 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK) 998 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_INM(x, mask) \ 999 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask) 1000 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUT(x, val) \ 1001 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), val) 1002 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUTM(x, mask, val) \ 1003 do {\ 1004 HWIO_INTLOCK(); \ 1005 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x)); \ 1006 HWIO_INTFREE();\ 1007 } while (0) 1008 1009 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1010 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_SHFT 0x0 1011 1012 //// Register REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET //// 1013 1014 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000088) 1015 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000088) 1016 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1017 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_SHFT 0 1018 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x) \ 1019 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK) 1020 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1021 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1022 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1023 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1024 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1025 do {\ 1026 HWIO_INTLOCK(); \ 1027 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x)); \ 1028 HWIO_INTFREE();\ 1029 } while (0) 1030 1031 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1032 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1033 1034 //// Register REO_R0_RXDMA2REO1_RING_BASE_LSB //// 1035 1036 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x) (x+0x0000008c) 1037 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_PHYS(x) (x+0x0000008c) 1038 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RMSK 0xffffffff 1039 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_SHFT 0 1040 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_IN(x) \ 1041 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RMSK) 1042 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_INM(x, mask) \ 1043 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), mask) 1044 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_OUT(x, val) \ 1045 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), val) 1046 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_OUTM(x, mask, val) \ 1047 do {\ 1048 HWIO_INTLOCK(); \ 1049 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_IN(x)); \ 1050 HWIO_INTFREE();\ 1051 } while (0) 1052 1053 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1054 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1055 1056 //// Register REO_R0_RXDMA2REO1_RING_BASE_MSB //// 1057 1058 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x) (x+0x00000090) 1059 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_PHYS(x) (x+0x00000090) 1060 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RMSK 0x00ffffff 1061 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_SHFT 0 1062 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_IN(x) \ 1063 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RMSK) 1064 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_INM(x, mask) \ 1065 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), mask) 1066 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_OUT(x, val) \ 1067 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), val) 1068 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_OUTM(x, mask, val) \ 1069 do {\ 1070 HWIO_INTLOCK(); \ 1071 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_IN(x)); \ 1072 HWIO_INTFREE();\ 1073 } while (0) 1074 1075 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1076 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1077 1078 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1079 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1080 1081 //// Register REO_R0_RXDMA2REO1_RING_ID //// 1082 1083 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x) (x+0x00000094) 1084 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_PHYS(x) (x+0x00000094) 1085 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_RMSK 0x000000ff 1086 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_SHFT 0 1087 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_IN(x) \ 1088 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_ID_RMSK) 1089 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_INM(x, mask) \ 1090 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), mask) 1091 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_OUT(x, val) \ 1092 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), val) 1093 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_OUTM(x, mask, val) \ 1094 do {\ 1095 HWIO_INTLOCK(); \ 1096 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_ID_IN(x)); \ 1097 HWIO_INTFREE();\ 1098 } while (0) 1099 1100 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1101 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_ENTRY_SIZE_SHFT 0x0 1102 1103 //// Register REO_R0_RXDMA2REO1_RING_STATUS //// 1104 1105 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x) (x+0x00000098) 1106 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_PHYS(x) (x+0x00000098) 1107 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_RMSK 0xffffffff 1108 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_SHFT 0 1109 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_IN(x) \ 1110 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_STATUS_RMSK) 1111 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_INM(x, mask) \ 1112 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), mask) 1113 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_OUT(x, val) \ 1114 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), val) 1115 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_OUTM(x, mask, val) \ 1116 do {\ 1117 HWIO_INTLOCK(); \ 1118 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_STATUS_IN(x)); \ 1119 HWIO_INTFREE();\ 1120 } while (0) 1121 1122 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1123 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1124 1125 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1126 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1127 1128 //// Register REO_R0_RXDMA2REO1_RING_MISC //// 1129 1130 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x) (x+0x0000009c) 1131 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_PHYS(x) (x+0x0000009c) 1132 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_RMSK 0x003fffff 1133 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SHFT 0 1134 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_IN(x) \ 1135 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MISC_RMSK) 1136 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_INM(x, mask) \ 1137 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), mask) 1138 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_OUT(x, val) \ 1139 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), val) 1140 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_OUTM(x, mask, val) \ 1141 do {\ 1142 HWIO_INTLOCK(); \ 1143 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MISC_IN(x)); \ 1144 HWIO_INTFREE();\ 1145 } while (0) 1146 1147 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1148 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SPARE_CONTROL_SHFT 0xe 1149 1150 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1151 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1152 1153 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1154 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1155 1156 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1157 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1158 1159 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1160 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SRNG_ENABLE_SHFT 0x6 1161 1162 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1163 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1164 1165 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1166 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1167 1168 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1169 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1170 1171 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1172 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SECURITY_BIT_SHFT 0x2 1173 1174 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1175 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1176 1177 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1178 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1179 1180 //// Register REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB //// 1181 1182 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x) (x+0x000000a8) 1183 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_PHYS(x) (x+0x000000a8) 1184 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_RMSK 0xffffffff 1185 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_SHFT 0 1186 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_IN(x) \ 1187 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_RMSK) 1188 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_INM(x, mask) \ 1189 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), mask) 1190 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_OUT(x, val) \ 1191 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), val) 1192 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1193 do {\ 1194 HWIO_INTLOCK(); \ 1195 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_IN(x)); \ 1196 HWIO_INTFREE();\ 1197 } while (0) 1198 1199 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1200 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1201 1202 //// Register REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB //// 1203 1204 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x) (x+0x000000ac) 1205 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_PHYS(x) (x+0x000000ac) 1206 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_RMSK 0x000000ff 1207 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_SHFT 0 1208 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_IN(x) \ 1209 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_RMSK) 1210 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_INM(x, mask) \ 1211 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), mask) 1212 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_OUT(x, val) \ 1213 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), val) 1214 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1215 do {\ 1216 HWIO_INTLOCK(); \ 1217 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_IN(x)); \ 1218 HWIO_INTFREE();\ 1219 } while (0) 1220 1221 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1222 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1223 1224 //// Register REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0 //// 1225 1226 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000000bc) 1227 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000000bc) 1228 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1229 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1230 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1231 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1232 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1233 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1234 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1235 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1236 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1237 do {\ 1238 HWIO_INTLOCK(); \ 1239 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1240 HWIO_INTFREE();\ 1241 } while (0) 1242 1243 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1244 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1245 1246 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1247 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1248 1249 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1250 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1251 1252 //// Register REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1 //// 1253 1254 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000000c0) 1255 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000000c0) 1256 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1257 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1258 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1259 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1260 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1261 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1262 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1263 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1264 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1265 do {\ 1266 HWIO_INTLOCK(); \ 1267 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1268 HWIO_INTFREE();\ 1269 } while (0) 1270 1271 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1272 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1273 1274 //// Register REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS //// 1275 1276 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000000c4) 1277 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000000c4) 1278 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1279 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_SHFT 0 1280 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_IN(x) \ 1281 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_RMSK) 1282 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1283 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1284 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1285 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1286 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1287 do {\ 1288 HWIO_INTLOCK(); \ 1289 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_IN(x)); \ 1290 HWIO_INTFREE();\ 1291 } while (0) 1292 1293 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1294 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1295 1296 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1297 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1298 1299 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1300 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1301 1302 //// Register REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER //// 1303 1304 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000000c8) 1305 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000000c8) 1306 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1307 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1308 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1309 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1310 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1311 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1312 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1313 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1314 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1315 do {\ 1316 HWIO_INTLOCK(); \ 1317 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1318 HWIO_INTFREE();\ 1319 } while (0) 1320 1321 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1322 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1323 1324 //// Register REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER //// 1325 1326 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000000cc) 1327 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000000cc) 1328 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1329 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1330 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1331 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1332 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1333 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1334 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1335 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1336 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1337 do {\ 1338 HWIO_INTLOCK(); \ 1339 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1340 HWIO_INTFREE();\ 1341 } while (0) 1342 1343 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1344 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1345 1346 //// Register REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS //// 1347 1348 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000000d0) 1349 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000000d0) 1350 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 1351 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1352 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1353 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1354 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1355 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1356 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1357 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1358 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1359 do {\ 1360 HWIO_INTLOCK(); \ 1361 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1362 HWIO_INTFREE();\ 1363 } while (0) 1364 1365 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 1366 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 1367 1368 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 1369 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1370 1371 //// Register REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB //// 1372 1373 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000000d4) 1374 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000000d4) 1375 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1376 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_SHFT 0 1377 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_IN(x) \ 1378 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_RMSK) 1379 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_INM(x, mask) \ 1380 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask) 1381 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_OUT(x, val) \ 1382 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), val) 1383 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1384 do {\ 1385 HWIO_INTLOCK(); \ 1386 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_IN(x)); \ 1387 HWIO_INTFREE();\ 1388 } while (0) 1389 1390 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1391 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1392 1393 //// Register REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB //// 1394 1395 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000000d8) 1396 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000000d8) 1397 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1398 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_SHFT 0 1399 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_IN(x) \ 1400 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_RMSK) 1401 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_INM(x, mask) \ 1402 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask) 1403 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_OUT(x, val) \ 1404 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), val) 1405 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1406 do {\ 1407 HWIO_INTLOCK(); \ 1408 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_IN(x)); \ 1409 HWIO_INTFREE();\ 1410 } while (0) 1411 1412 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1413 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1414 1415 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1416 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1417 1418 //// Register REO_R0_RXDMA2REO1_RING_MSI1_DATA //// 1419 1420 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x) (x+0x000000dc) 1421 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_PHYS(x) (x+0x000000dc) 1422 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_RMSK 0xffffffff 1423 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_SHFT 0 1424 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_IN(x) \ 1425 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_RMSK) 1426 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_INM(x, mask) \ 1427 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), mask) 1428 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_OUT(x, val) \ 1429 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), val) 1430 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_OUTM(x, mask, val) \ 1431 do {\ 1432 HWIO_INTLOCK(); \ 1433 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_IN(x)); \ 1434 HWIO_INTFREE();\ 1435 } while (0) 1436 1437 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1438 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_VALUE_SHFT 0x0 1439 1440 //// Register REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET //// 1441 1442 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000000e0) 1443 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000000e0) 1444 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1445 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_SHFT 0 1446 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_IN(x) \ 1447 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_RMSK) 1448 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1449 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1450 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1451 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1452 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1453 do {\ 1454 HWIO_INTLOCK(); \ 1455 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_IN(x)); \ 1456 HWIO_INTFREE();\ 1457 } while (0) 1458 1459 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1460 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1461 1462 //// Register REO_R0_RXDMA2REO2_RING_BASE_LSB //// 1463 1464 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x) (x+0x000000e4) 1465 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_PHYS(x) (x+0x000000e4) 1466 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RMSK 0xffffffff 1467 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_SHFT 0 1468 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_IN(x) \ 1469 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RMSK) 1470 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_INM(x, mask) \ 1471 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), mask) 1472 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_OUT(x, val) \ 1473 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), val) 1474 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_OUTM(x, mask, val) \ 1475 do {\ 1476 HWIO_INTLOCK(); \ 1477 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_IN(x)); \ 1478 HWIO_INTFREE();\ 1479 } while (0) 1480 1481 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1482 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1483 1484 //// Register REO_R0_RXDMA2REO2_RING_BASE_MSB //// 1485 1486 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x) (x+0x000000e8) 1487 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_PHYS(x) (x+0x000000e8) 1488 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RMSK 0x00ffffff 1489 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_SHFT 0 1490 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_IN(x) \ 1491 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RMSK) 1492 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_INM(x, mask) \ 1493 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), mask) 1494 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_OUT(x, val) \ 1495 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), val) 1496 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_OUTM(x, mask, val) \ 1497 do {\ 1498 HWIO_INTLOCK(); \ 1499 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_IN(x)); \ 1500 HWIO_INTFREE();\ 1501 } while (0) 1502 1503 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1504 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1505 1506 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1507 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1508 1509 //// Register REO_R0_RXDMA2REO2_RING_ID //// 1510 1511 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x) (x+0x000000ec) 1512 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_PHYS(x) (x+0x000000ec) 1513 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_RMSK 0x000000ff 1514 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_SHFT 0 1515 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_IN(x) \ 1516 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_ID_RMSK) 1517 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_INM(x, mask) \ 1518 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), mask) 1519 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_OUT(x, val) \ 1520 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), val) 1521 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_OUTM(x, mask, val) \ 1522 do {\ 1523 HWIO_INTLOCK(); \ 1524 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_ID_IN(x)); \ 1525 HWIO_INTFREE();\ 1526 } while (0) 1527 1528 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1529 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_ENTRY_SIZE_SHFT 0x0 1530 1531 //// Register REO_R0_RXDMA2REO2_RING_STATUS //// 1532 1533 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x) (x+0x000000f0) 1534 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_PHYS(x) (x+0x000000f0) 1535 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_RMSK 0xffffffff 1536 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_SHFT 0 1537 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_IN(x) \ 1538 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_STATUS_RMSK) 1539 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_INM(x, mask) \ 1540 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), mask) 1541 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_OUT(x, val) \ 1542 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), val) 1543 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_OUTM(x, mask, val) \ 1544 do {\ 1545 HWIO_INTLOCK(); \ 1546 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_STATUS_IN(x)); \ 1547 HWIO_INTFREE();\ 1548 } while (0) 1549 1550 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1551 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1552 1553 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1554 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1555 1556 //// Register REO_R0_RXDMA2REO2_RING_MISC //// 1557 1558 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x) (x+0x000000f4) 1559 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_PHYS(x) (x+0x000000f4) 1560 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_RMSK 0x003fffff 1561 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SHFT 0 1562 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_IN(x) \ 1563 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MISC_RMSK) 1564 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_INM(x, mask) \ 1565 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), mask) 1566 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_OUT(x, val) \ 1567 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), val) 1568 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_OUTM(x, mask, val) \ 1569 do {\ 1570 HWIO_INTLOCK(); \ 1571 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MISC_IN(x)); \ 1572 HWIO_INTFREE();\ 1573 } while (0) 1574 1575 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1576 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SPARE_CONTROL_SHFT 0xe 1577 1578 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1579 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1580 1581 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1582 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1583 1584 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1585 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1586 1587 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1588 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SRNG_ENABLE_SHFT 0x6 1589 1590 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1591 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1592 1593 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1594 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1595 1596 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1597 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1598 1599 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1600 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SECURITY_BIT_SHFT 0x2 1601 1602 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1603 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1604 1605 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1606 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1607 1608 //// Register REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB //// 1609 1610 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000100) 1611 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000100) 1612 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_RMSK 0xffffffff 1613 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_SHFT 0 1614 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_IN(x) \ 1615 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_RMSK) 1616 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_INM(x, mask) \ 1617 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), mask) 1618 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_OUT(x, val) \ 1619 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), val) 1620 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1621 do {\ 1622 HWIO_INTLOCK(); \ 1623 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_IN(x)); \ 1624 HWIO_INTFREE();\ 1625 } while (0) 1626 1627 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1628 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1629 1630 //// Register REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB //// 1631 1632 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000104) 1633 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000104) 1634 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_RMSK 0x000000ff 1635 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_SHFT 0 1636 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_IN(x) \ 1637 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_RMSK) 1638 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_INM(x, mask) \ 1639 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), mask) 1640 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_OUT(x, val) \ 1641 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), val) 1642 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1643 do {\ 1644 HWIO_INTLOCK(); \ 1645 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_IN(x)); \ 1646 HWIO_INTFREE();\ 1647 } while (0) 1648 1649 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1650 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1651 1652 //// Register REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0 //// 1653 1654 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000114) 1655 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000114) 1656 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1657 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1658 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1659 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1660 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1661 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1662 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1663 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1664 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1665 do {\ 1666 HWIO_INTLOCK(); \ 1667 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1668 HWIO_INTFREE();\ 1669 } while (0) 1670 1671 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1672 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1673 1674 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1675 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1676 1677 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1678 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1679 1680 //// Register REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1 //// 1681 1682 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000118) 1683 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000118) 1684 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1685 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1686 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1687 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1688 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1689 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1690 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1691 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1692 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1693 do {\ 1694 HWIO_INTLOCK(); \ 1695 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1696 HWIO_INTFREE();\ 1697 } while (0) 1698 1699 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1700 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1701 1702 //// Register REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS //// 1703 1704 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000011c) 1705 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000011c) 1706 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1707 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_SHFT 0 1708 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_IN(x) \ 1709 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_RMSK) 1710 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1711 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1712 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1713 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1714 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1715 do {\ 1716 HWIO_INTLOCK(); \ 1717 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_IN(x)); \ 1718 HWIO_INTFREE();\ 1719 } while (0) 1720 1721 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1722 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1723 1724 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1725 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1726 1727 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1728 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1729 1730 //// Register REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER //// 1731 1732 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000120) 1733 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000120) 1734 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1735 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1736 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1737 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1738 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1739 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1740 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1741 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1742 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1743 do {\ 1744 HWIO_INTLOCK(); \ 1745 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1746 HWIO_INTFREE();\ 1747 } while (0) 1748 1749 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1750 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1751 1752 //// Register REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER //// 1753 1754 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000124) 1755 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000124) 1756 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1757 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1758 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1759 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1760 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1761 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1762 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1763 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1764 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1765 do {\ 1766 HWIO_INTLOCK(); \ 1767 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1768 HWIO_INTFREE();\ 1769 } while (0) 1770 1771 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1772 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1773 1774 //// Register REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS //// 1775 1776 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000128) 1777 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000128) 1778 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 1779 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1780 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1781 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1782 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1783 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1784 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1785 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1786 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1787 do {\ 1788 HWIO_INTLOCK(); \ 1789 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1790 HWIO_INTFREE();\ 1791 } while (0) 1792 1793 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 1794 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 1795 1796 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 1797 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1798 1799 //// Register REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB //// 1800 1801 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000012c) 1802 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000012c) 1803 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1804 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_SHFT 0 1805 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_IN(x) \ 1806 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_RMSK) 1807 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_INM(x, mask) \ 1808 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), mask) 1809 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_OUT(x, val) \ 1810 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), val) 1811 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1812 do {\ 1813 HWIO_INTLOCK(); \ 1814 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_IN(x)); \ 1815 HWIO_INTFREE();\ 1816 } while (0) 1817 1818 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1819 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1820 1821 //// Register REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB //// 1822 1823 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000130) 1824 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000130) 1825 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1826 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_SHFT 0 1827 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_IN(x) \ 1828 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_RMSK) 1829 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_INM(x, mask) \ 1830 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), mask) 1831 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_OUT(x, val) \ 1832 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), val) 1833 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1834 do {\ 1835 HWIO_INTLOCK(); \ 1836 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_IN(x)); \ 1837 HWIO_INTFREE();\ 1838 } while (0) 1839 1840 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1841 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1842 1843 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1844 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1845 1846 //// Register REO_R0_RXDMA2REO2_RING_MSI1_DATA //// 1847 1848 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x) (x+0x00000134) 1849 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_PHYS(x) (x+0x00000134) 1850 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_RMSK 0xffffffff 1851 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_SHFT 0 1852 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_IN(x) \ 1853 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_RMSK) 1854 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_INM(x, mask) \ 1855 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), mask) 1856 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_OUT(x, val) \ 1857 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), val) 1858 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_OUTM(x, mask, val) \ 1859 do {\ 1860 HWIO_INTLOCK(); \ 1861 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_IN(x)); \ 1862 HWIO_INTFREE();\ 1863 } while (0) 1864 1865 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1866 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_VALUE_SHFT 0x0 1867 1868 //// Register REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET //// 1869 1870 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000138) 1871 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000138) 1872 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1873 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_SHFT 0 1874 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_IN(x) \ 1875 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_RMSK) 1876 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1877 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1878 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1879 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1880 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1881 do {\ 1882 HWIO_INTLOCK(); \ 1883 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_IN(x)); \ 1884 HWIO_INTFREE();\ 1885 } while (0) 1886 1887 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1888 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1889 1890 //// Register REO_R0_WBM2REO_LINK_RING_BASE_LSB //// 1891 1892 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x) (x+0x0000013c) 1893 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_PHYS(x) (x+0x0000013c) 1894 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK 0xffffffff 1895 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_SHFT 0 1896 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x) \ 1897 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK) 1898 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, mask) \ 1899 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask) 1900 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, val) \ 1901 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), val) 1902 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ 1903 do {\ 1904 HWIO_INTLOCK(); \ 1905 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)); \ 1906 HWIO_INTFREE();\ 1907 } while (0) 1908 1909 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1910 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1911 1912 //// Register REO_R0_WBM2REO_LINK_RING_BASE_MSB //// 1913 1914 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x) (x+0x00000140) 1915 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_PHYS(x) (x+0x00000140) 1916 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK 0x00ffffff 1917 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_SHFT 0 1918 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x) \ 1919 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK) 1920 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, mask) \ 1921 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask) 1922 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, val) \ 1923 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), val) 1924 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ 1925 do {\ 1926 HWIO_INTLOCK(); \ 1927 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)); \ 1928 HWIO_INTFREE();\ 1929 } while (0) 1930 1931 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1932 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1933 1934 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1935 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1936 1937 //// Register REO_R0_WBM2REO_LINK_RING_ID //// 1938 1939 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x) (x+0x00000144) 1940 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_PHYS(x) (x+0x00000144) 1941 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK 0x000000ff 1942 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_SHFT 0 1943 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x) \ 1944 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK) 1945 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_INM(x, mask) \ 1946 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask) 1947 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUT(x, val) \ 1948 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), val) 1949 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUTM(x, mask, val) \ 1950 do {\ 1951 HWIO_INTLOCK(); \ 1952 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x)); \ 1953 HWIO_INTFREE();\ 1954 } while (0) 1955 1956 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1957 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 1958 1959 //// Register REO_R0_WBM2REO_LINK_RING_STATUS //// 1960 1961 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x) (x+0x00000148) 1962 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_PHYS(x) (x+0x00000148) 1963 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK 0xffffffff 1964 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_SHFT 0 1965 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x) \ 1966 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK) 1967 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_INM(x, mask) \ 1968 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask) 1969 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUT(x, val) \ 1970 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), val) 1971 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUTM(x, mask, val) \ 1972 do {\ 1973 HWIO_INTLOCK(); \ 1974 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x)); \ 1975 HWIO_INTFREE();\ 1976 } while (0) 1977 1978 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1979 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1980 1981 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1982 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1983 1984 //// Register REO_R0_WBM2REO_LINK_RING_MISC //// 1985 1986 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x) (x+0x0000014c) 1987 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_PHYS(x) (x+0x0000014c) 1988 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK 0x003fffff 1989 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SHFT 0 1990 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x) \ 1991 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK) 1992 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_INM(x, mask) \ 1993 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask) 1994 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUT(x, val) \ 1995 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), val) 1996 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUTM(x, mask, val) \ 1997 do {\ 1998 HWIO_INTLOCK(); \ 1999 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x)); \ 2000 HWIO_INTFREE();\ 2001 } while (0) 2002 2003 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2004 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_SHFT 0xe 2005 2006 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2007 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2008 2009 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2010 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2011 2012 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2013 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2014 2015 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2016 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_SHFT 0x6 2017 2018 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2019 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2020 2021 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2022 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2023 2024 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2025 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2026 2027 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2028 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 2029 2030 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2031 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2032 2033 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2034 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2035 2036 //// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB //// 2037 2038 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000158) 2039 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000158) 2040 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK 0xffffffff 2041 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_SHFT 0 2042 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x) \ 2043 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK) 2044 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_INM(x, mask) \ 2045 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask) 2046 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUT(x, val) \ 2047 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), val) 2048 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2049 do {\ 2050 HWIO_INTLOCK(); \ 2051 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x)); \ 2052 HWIO_INTFREE();\ 2053 } while (0) 2054 2055 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2056 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2057 2058 //// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB //// 2059 2060 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000015c) 2061 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000015c) 2062 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK 0x000000ff 2063 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_SHFT 0 2064 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x) \ 2065 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK) 2066 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_INM(x, mask) \ 2067 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask) 2068 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUT(x, val) \ 2069 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), val) 2070 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2071 do {\ 2072 HWIO_INTLOCK(); \ 2073 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x)); \ 2074 HWIO_INTFREE();\ 2075 } while (0) 2076 2077 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2078 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2079 2080 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0 //// 2081 2082 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000016c) 2083 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000016c) 2084 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2085 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2086 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2087 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2088 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2089 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2090 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2091 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2092 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2093 do {\ 2094 HWIO_INTLOCK(); \ 2095 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2096 HWIO_INTFREE();\ 2097 } while (0) 2098 2099 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2100 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2101 2102 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2103 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2104 2105 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2106 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2107 2108 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1 //// 2109 2110 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000170) 2111 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000170) 2112 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2113 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2114 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2115 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2116 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2117 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2118 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2119 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2120 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2121 do {\ 2122 HWIO_INTLOCK(); \ 2123 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2124 HWIO_INTFREE();\ 2125 } while (0) 2126 2127 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2128 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2129 2130 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS //// 2131 2132 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000174) 2133 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000174) 2134 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2135 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_SHFT 0 2136 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x) \ 2137 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK) 2138 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2139 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2140 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2141 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2142 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2143 do {\ 2144 HWIO_INTLOCK(); \ 2145 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x)); \ 2146 HWIO_INTFREE();\ 2147 } while (0) 2148 2149 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2150 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2151 2152 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2153 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2154 2155 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2156 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2157 2158 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER //// 2159 2160 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000178) 2161 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000178) 2162 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2163 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2164 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2165 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2166 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2167 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2168 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2169 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2170 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2171 do {\ 2172 HWIO_INTLOCK(); \ 2173 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2174 HWIO_INTFREE();\ 2175 } while (0) 2176 2177 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2178 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2179 2180 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER //// 2181 2182 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000017c) 2183 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000017c) 2184 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2185 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2186 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2187 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2188 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2189 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2190 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2191 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2192 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2193 do {\ 2194 HWIO_INTLOCK(); \ 2195 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2196 HWIO_INTFREE();\ 2197 } while (0) 2198 2199 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2200 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2201 2202 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS //// 2203 2204 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000180) 2205 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000180) 2206 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2207 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2208 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2209 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2210 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2211 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2212 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2213 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2214 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2215 do {\ 2216 HWIO_INTLOCK(); \ 2217 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2218 HWIO_INTFREE();\ 2219 } while (0) 2220 2221 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 2222 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2223 2224 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 2225 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2226 2227 //// Register REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET //// 2228 2229 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000190) 2230 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000190) 2231 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2232 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 2233 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ 2234 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK) 2235 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2236 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2237 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2238 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2239 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2240 do {\ 2241 HWIO_INTLOCK(); \ 2242 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ 2243 HWIO_INTFREE();\ 2244 } while (0) 2245 2246 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2247 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2248 2249 //// Register REO_R0_REO_CMD_RING_BASE_LSB //// 2250 2251 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x) (x+0x00000194) 2252 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_PHYS(x) (x+0x00000194) 2253 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK 0xffffffff 2254 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_SHFT 0 2255 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x) \ 2256 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK) 2257 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_INM(x, mask) \ 2258 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask) 2259 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUT(x, val) \ 2260 out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), val) 2261 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUTM(x, mask, val) \ 2262 do {\ 2263 HWIO_INTLOCK(); \ 2264 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x)); \ 2265 HWIO_INTFREE();\ 2266 } while (0) 2267 2268 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2269 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2270 2271 //// Register REO_R0_REO_CMD_RING_BASE_MSB //// 2272 2273 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x) (x+0x00000198) 2274 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_PHYS(x) (x+0x00000198) 2275 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK 0x00ffffff 2276 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_SHFT 0 2277 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x) \ 2278 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK) 2279 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_INM(x, mask) \ 2280 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask) 2281 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUT(x, val) \ 2282 out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), val) 2283 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUTM(x, mask, val) \ 2284 do {\ 2285 HWIO_INTLOCK(); \ 2286 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x)); \ 2287 HWIO_INTFREE();\ 2288 } while (0) 2289 2290 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 2291 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2292 2293 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2294 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2295 2296 //// Register REO_R0_REO_CMD_RING_ID //// 2297 2298 #define HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x) (x+0x0000019c) 2299 #define HWIO_REO_R0_REO_CMD_RING_ID_PHYS(x) (x+0x0000019c) 2300 #define HWIO_REO_R0_REO_CMD_RING_ID_RMSK 0x000000ff 2301 #define HWIO_REO_R0_REO_CMD_RING_ID_SHFT 0 2302 #define HWIO_REO_R0_REO_CMD_RING_ID_IN(x) \ 2303 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), HWIO_REO_R0_REO_CMD_RING_ID_RMSK) 2304 #define HWIO_REO_R0_REO_CMD_RING_ID_INM(x, mask) \ 2305 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask) 2306 #define HWIO_REO_R0_REO_CMD_RING_ID_OUT(x, val) \ 2307 out_dword( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), val) 2308 #define HWIO_REO_R0_REO_CMD_RING_ID_OUTM(x, mask, val) \ 2309 do {\ 2310 HWIO_INTLOCK(); \ 2311 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_ID_IN(x)); \ 2312 HWIO_INTFREE();\ 2313 } while (0) 2314 2315 #define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2316 #define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_SHFT 0x0 2317 2318 //// Register REO_R0_REO_CMD_RING_STATUS //// 2319 2320 #define HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x) (x+0x000001a0) 2321 #define HWIO_REO_R0_REO_CMD_RING_STATUS_PHYS(x) (x+0x000001a0) 2322 #define HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK 0xffffffff 2323 #define HWIO_REO_R0_REO_CMD_RING_STATUS_SHFT 0 2324 #define HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x) \ 2325 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK) 2326 #define HWIO_REO_R0_REO_CMD_RING_STATUS_INM(x, mask) \ 2327 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask) 2328 #define HWIO_REO_R0_REO_CMD_RING_STATUS_OUT(x, val) \ 2329 out_dword( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), val) 2330 #define HWIO_REO_R0_REO_CMD_RING_STATUS_OUTM(x, mask, val) \ 2331 do {\ 2332 HWIO_INTLOCK(); \ 2333 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x)); \ 2334 HWIO_INTFREE();\ 2335 } while (0) 2336 2337 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2338 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2339 2340 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2341 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2342 2343 //// Register REO_R0_REO_CMD_RING_MISC //// 2344 2345 #define HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x) (x+0x000001a4) 2346 #define HWIO_REO_R0_REO_CMD_RING_MISC_PHYS(x) (x+0x000001a4) 2347 #define HWIO_REO_R0_REO_CMD_RING_MISC_RMSK 0x003fffff 2348 #define HWIO_REO_R0_REO_CMD_RING_MISC_SHFT 0 2349 #define HWIO_REO_R0_REO_CMD_RING_MISC_IN(x) \ 2350 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MISC_RMSK) 2351 #define HWIO_REO_R0_REO_CMD_RING_MISC_INM(x, mask) \ 2352 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask) 2353 #define HWIO_REO_R0_REO_CMD_RING_MISC_OUT(x, val) \ 2354 out_dword( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), val) 2355 #define HWIO_REO_R0_REO_CMD_RING_MISC_OUTM(x, mask, val) \ 2356 do {\ 2357 HWIO_INTLOCK(); \ 2358 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MISC_IN(x)); \ 2359 HWIO_INTFREE();\ 2360 } while (0) 2361 2362 #define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2363 #define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_SHFT 0xe 2364 2365 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2366 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2367 2368 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2369 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2370 2371 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2372 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2373 2374 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2375 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_SHFT 0x6 2376 2377 #define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2378 #define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2379 2380 #define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2381 #define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2382 2383 #define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2384 #define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2385 2386 #define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2387 #define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_SHFT 0x2 2388 2389 #define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2390 #define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2391 2392 #define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2393 #define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2394 2395 //// Register REO_R0_REO_CMD_RING_TP_ADDR_LSB //// 2396 2397 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x) (x+0x000001b0) 2398 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_PHYS(x) (x+0x000001b0) 2399 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff 2400 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_SHFT 0 2401 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x) \ 2402 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK) 2403 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_INM(x, mask) \ 2404 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) 2405 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUT(x, val) \ 2406 out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), val) 2407 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2408 do {\ 2409 HWIO_INTLOCK(); \ 2410 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x)); \ 2411 HWIO_INTFREE();\ 2412 } while (0) 2413 2414 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2415 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2416 2417 //// Register REO_R0_REO_CMD_RING_TP_ADDR_MSB //// 2418 2419 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x) (x+0x000001b4) 2420 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_PHYS(x) (x+0x000001b4) 2421 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK 0x000000ff 2422 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_SHFT 0 2423 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x) \ 2424 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK) 2425 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_INM(x, mask) \ 2426 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) 2427 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUT(x, val) \ 2428 out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), val) 2429 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2430 do {\ 2431 HWIO_INTLOCK(); \ 2432 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x)); \ 2433 HWIO_INTFREE();\ 2434 } while (0) 2435 2436 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2437 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2438 2439 //// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0 //// 2440 2441 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001c4) 2442 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001c4) 2443 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2444 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2445 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2446 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2447 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2448 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2449 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2450 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2451 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2452 do {\ 2453 HWIO_INTLOCK(); \ 2454 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2455 HWIO_INTFREE();\ 2456 } while (0) 2457 2458 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2459 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2460 2461 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2462 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2463 2464 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2465 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2466 2467 //// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1 //// 2468 2469 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000001c8) 2470 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000001c8) 2471 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2472 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2473 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2474 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2475 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2476 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2477 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2478 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2479 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2480 do {\ 2481 HWIO_INTLOCK(); \ 2482 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2483 HWIO_INTFREE();\ 2484 } while (0) 2485 2486 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2487 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2488 2489 //// Register REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS //// 2490 2491 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000001cc) 2492 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000001cc) 2493 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2494 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_SHFT 0 2495 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ 2496 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK) 2497 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2498 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2499 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2500 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2501 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2502 do {\ 2503 HWIO_INTLOCK(); \ 2504 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \ 2505 HWIO_INTFREE();\ 2506 } while (0) 2507 2508 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2509 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2510 2511 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2512 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2513 2514 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2515 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2516 2517 //// Register REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER //// 2518 2519 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001d0) 2520 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001d0) 2521 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2522 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2523 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2524 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2525 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2526 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2527 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2528 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2529 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2530 do {\ 2531 HWIO_INTLOCK(); \ 2532 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2533 HWIO_INTFREE();\ 2534 } while (0) 2535 2536 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2537 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2538 2539 //// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER //// 2540 2541 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000001d4) 2542 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000001d4) 2543 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2544 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2545 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2546 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2547 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2548 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2549 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2550 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2551 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2552 do {\ 2553 HWIO_INTLOCK(); \ 2554 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2555 HWIO_INTFREE();\ 2556 } while (0) 2557 2558 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2559 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2560 2561 //// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS //// 2562 2563 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000001d8) 2564 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000001d8) 2565 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2566 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2567 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2568 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2569 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2570 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2571 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2572 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2573 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2574 do {\ 2575 HWIO_INTLOCK(); \ 2576 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2577 HWIO_INTFREE();\ 2578 } while (0) 2579 2580 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 2581 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2582 2583 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 2584 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2585 2586 //// Register REO_R0_REO_CMD_RING_MSI1_BASE_LSB //// 2587 2588 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000001dc) 2589 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000001dc) 2590 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2591 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_SHFT 0 2592 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x) \ 2593 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK) 2594 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_INM(x, mask) \ 2595 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) 2596 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUT(x, val) \ 2597 out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), val) 2598 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2599 do {\ 2600 HWIO_INTLOCK(); \ 2601 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x)); \ 2602 HWIO_INTFREE();\ 2603 } while (0) 2604 2605 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2606 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2607 2608 //// Register REO_R0_REO_CMD_RING_MSI1_BASE_MSB //// 2609 2610 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000001e0) 2611 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000001e0) 2612 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2613 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_SHFT 0 2614 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x) \ 2615 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK) 2616 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_INM(x, mask) \ 2617 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) 2618 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUT(x, val) \ 2619 out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), val) 2620 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2621 do {\ 2622 HWIO_INTLOCK(); \ 2623 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x)); \ 2624 HWIO_INTFREE();\ 2625 } while (0) 2626 2627 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2628 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2629 2630 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2631 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2632 2633 //// Register REO_R0_REO_CMD_RING_MSI1_DATA //// 2634 2635 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x) (x+0x000001e4) 2636 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_PHYS(x) (x+0x000001e4) 2637 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK 0xffffffff 2638 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_SHFT 0 2639 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x) \ 2640 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK) 2641 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_INM(x, mask) \ 2642 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask) 2643 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUT(x, val) \ 2644 out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), val) 2645 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUTM(x, mask, val) \ 2646 do {\ 2647 HWIO_INTLOCK(); \ 2648 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x)); \ 2649 HWIO_INTFREE();\ 2650 } while (0) 2651 2652 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2653 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_SHFT 0x0 2654 2655 //// Register REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET //// 2656 2657 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001e8) 2658 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001e8) 2659 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2660 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_SHFT 0 2661 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ 2662 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK) 2663 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2664 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2665 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2666 out_dword( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2667 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2668 do {\ 2669 HWIO_INTLOCK(); \ 2670 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \ 2671 HWIO_INTFREE();\ 2672 } while (0) 2673 2674 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2675 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2676 2677 //// Register REO_R0_SW2REO_RING_BASE_LSB //// 2678 2679 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) (x+0x000001ec) 2680 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_PHYS(x) (x+0x000001ec) 2681 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK 0xffffffff 2682 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_SHFT 0 2683 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x) \ 2684 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK) 2685 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_INM(x, mask) \ 2686 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask) 2687 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUT(x, val) \ 2688 out_dword( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), val) 2689 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUTM(x, mask, val) \ 2690 do {\ 2691 HWIO_INTLOCK(); \ 2692 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x)); \ 2693 HWIO_INTFREE();\ 2694 } while (0) 2695 2696 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2697 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2698 2699 //// Register REO_R0_SW2REO_RING_BASE_MSB //// 2700 2701 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x) (x+0x000001f0) 2702 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_PHYS(x) (x+0x000001f0) 2703 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK 0x00ffffff 2704 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_SHFT 0 2705 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x) \ 2706 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK) 2707 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_INM(x, mask) \ 2708 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask) 2709 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUT(x, val) \ 2710 out_dword( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), val) 2711 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUTM(x, mask, val) \ 2712 do {\ 2713 HWIO_INTLOCK(); \ 2714 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x)); \ 2715 HWIO_INTFREE();\ 2716 } while (0) 2717 2718 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 2719 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2720 2721 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2722 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2723 2724 //// Register REO_R0_SW2REO_RING_ID //// 2725 2726 #define HWIO_REO_R0_SW2REO_RING_ID_ADDR(x) (x+0x000001f4) 2727 #define HWIO_REO_R0_SW2REO_RING_ID_PHYS(x) (x+0x000001f4) 2728 #define HWIO_REO_R0_SW2REO_RING_ID_RMSK 0x000000ff 2729 #define HWIO_REO_R0_SW2REO_RING_ID_SHFT 0 2730 #define HWIO_REO_R0_SW2REO_RING_ID_IN(x) \ 2731 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), HWIO_REO_R0_SW2REO_RING_ID_RMSK) 2732 #define HWIO_REO_R0_SW2REO_RING_ID_INM(x, mask) \ 2733 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask) 2734 #define HWIO_REO_R0_SW2REO_RING_ID_OUT(x, val) \ 2735 out_dword( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), val) 2736 #define HWIO_REO_R0_SW2REO_RING_ID_OUTM(x, mask, val) \ 2737 do {\ 2738 HWIO_INTLOCK(); \ 2739 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_ID_IN(x)); \ 2740 HWIO_INTFREE();\ 2741 } while (0) 2742 2743 #define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2744 #define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_SHFT 0x0 2745 2746 //// Register REO_R0_SW2REO_RING_STATUS //// 2747 2748 #define HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x) (x+0x000001f8) 2749 #define HWIO_REO_R0_SW2REO_RING_STATUS_PHYS(x) (x+0x000001f8) 2750 #define HWIO_REO_R0_SW2REO_RING_STATUS_RMSK 0xffffffff 2751 #define HWIO_REO_R0_SW2REO_RING_STATUS_SHFT 0 2752 #define HWIO_REO_R0_SW2REO_RING_STATUS_IN(x) \ 2753 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_STATUS_RMSK) 2754 #define HWIO_REO_R0_SW2REO_RING_STATUS_INM(x, mask) \ 2755 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask) 2756 #define HWIO_REO_R0_SW2REO_RING_STATUS_OUT(x, val) \ 2757 out_dword( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), val) 2758 #define HWIO_REO_R0_SW2REO_RING_STATUS_OUTM(x, mask, val) \ 2759 do {\ 2760 HWIO_INTLOCK(); \ 2761 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_STATUS_IN(x)); \ 2762 HWIO_INTFREE();\ 2763 } while (0) 2764 2765 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2766 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2767 2768 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2769 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2770 2771 //// Register REO_R0_SW2REO_RING_MISC //// 2772 2773 #define HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x) (x+0x000001fc) 2774 #define HWIO_REO_R0_SW2REO_RING_MISC_PHYS(x) (x+0x000001fc) 2775 #define HWIO_REO_R0_SW2REO_RING_MISC_RMSK 0x003fffff 2776 #define HWIO_REO_R0_SW2REO_RING_MISC_SHFT 0 2777 #define HWIO_REO_R0_SW2REO_RING_MISC_IN(x) \ 2778 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), HWIO_REO_R0_SW2REO_RING_MISC_RMSK) 2779 #define HWIO_REO_R0_SW2REO_RING_MISC_INM(x, mask) \ 2780 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask) 2781 #define HWIO_REO_R0_SW2REO_RING_MISC_OUT(x, val) \ 2782 out_dword( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), val) 2783 #define HWIO_REO_R0_SW2REO_RING_MISC_OUTM(x, mask, val) \ 2784 do {\ 2785 HWIO_INTLOCK(); \ 2786 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MISC_IN(x)); \ 2787 HWIO_INTFREE();\ 2788 } while (0) 2789 2790 #define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2791 #define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_SHFT 0xe 2792 2793 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2794 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2795 2796 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2797 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2798 2799 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2800 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2801 2802 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2803 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_SHFT 0x6 2804 2805 #define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2806 #define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2807 2808 #define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2809 #define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2810 2811 #define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2812 #define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2813 2814 #define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2815 #define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_SHFT 0x2 2816 2817 #define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2818 #define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2819 2820 #define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2821 #define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2822 2823 //// Register REO_R0_SW2REO_RING_TP_ADDR_LSB //// 2824 2825 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000208) 2826 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000208) 2827 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK 0xffffffff 2828 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_SHFT 0 2829 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x) \ 2830 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK) 2831 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_INM(x, mask) \ 2832 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask) 2833 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUT(x, val) \ 2834 out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), val) 2835 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2836 do {\ 2837 HWIO_INTLOCK(); \ 2838 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x)); \ 2839 HWIO_INTFREE();\ 2840 } while (0) 2841 2842 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2843 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2844 2845 //// Register REO_R0_SW2REO_RING_TP_ADDR_MSB //// 2846 2847 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000020c) 2848 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000020c) 2849 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK 0x000000ff 2850 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_SHFT 0 2851 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x) \ 2852 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK) 2853 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_INM(x, mask) \ 2854 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask) 2855 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUT(x, val) \ 2856 out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), val) 2857 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2858 do {\ 2859 HWIO_INTLOCK(); \ 2860 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x)); \ 2861 HWIO_INTFREE();\ 2862 } while (0) 2863 2864 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2865 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2866 2867 //// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0 //// 2868 2869 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000021c) 2870 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000021c) 2871 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2872 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2873 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2874 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2875 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2876 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2877 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2878 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2879 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2880 do {\ 2881 HWIO_INTLOCK(); \ 2882 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2883 HWIO_INTFREE();\ 2884 } while (0) 2885 2886 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2887 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2888 2889 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2890 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2891 2892 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2893 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2894 2895 //// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1 //// 2896 2897 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000220) 2898 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000220) 2899 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2900 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2901 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2902 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2903 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2904 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2905 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2906 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2907 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2908 do {\ 2909 HWIO_INTLOCK(); \ 2910 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2911 HWIO_INTFREE();\ 2912 } while (0) 2913 2914 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2915 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2916 2917 //// Register REO_R0_SW2REO_RING_CONSUMER_INT_STATUS //// 2918 2919 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000224) 2920 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000224) 2921 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2922 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_SHFT 0 2923 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x) \ 2924 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK) 2925 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2926 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2927 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2928 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2929 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2930 do {\ 2931 HWIO_INTLOCK(); \ 2932 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x)); \ 2933 HWIO_INTFREE();\ 2934 } while (0) 2935 2936 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2937 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2938 2939 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2940 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2941 2942 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2943 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2944 2945 //// Register REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER //// 2946 2947 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000228) 2948 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000228) 2949 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2950 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2951 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2952 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2953 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2954 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2955 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2956 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2957 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2958 do {\ 2959 HWIO_INTLOCK(); \ 2960 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2961 HWIO_INTFREE();\ 2962 } while (0) 2963 2964 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2965 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2966 2967 //// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER //// 2968 2969 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000022c) 2970 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000022c) 2971 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2972 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2973 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2974 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2975 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2976 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2977 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2978 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2979 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2980 do {\ 2981 HWIO_INTLOCK(); \ 2982 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2983 HWIO_INTFREE();\ 2984 } while (0) 2985 2986 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2987 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2988 2989 //// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS //// 2990 2991 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000230) 2992 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000230) 2993 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2994 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2995 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2996 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2997 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2998 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2999 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 3000 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 3001 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 3002 do {\ 3003 HWIO_INTLOCK(); \ 3004 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 3005 HWIO_INTFREE();\ 3006 } while (0) 3007 3008 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 3009 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 3010 3011 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 3012 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 3013 3014 //// Register REO_R0_SW2REO_RING_MSI1_BASE_LSB //// 3015 3016 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000234) 3017 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000234) 3018 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3019 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_SHFT 0 3020 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x) \ 3021 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK) 3022 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_INM(x, mask) \ 3023 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask) 3024 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUT(x, val) \ 3025 out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), val) 3026 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3027 do {\ 3028 HWIO_INTLOCK(); \ 3029 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x)); \ 3030 HWIO_INTFREE();\ 3031 } while (0) 3032 3033 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3034 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3035 3036 //// Register REO_R0_SW2REO_RING_MSI1_BASE_MSB //// 3037 3038 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000238) 3039 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000238) 3040 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3041 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_SHFT 0 3042 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x) \ 3043 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK) 3044 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_INM(x, mask) \ 3045 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask) 3046 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUT(x, val) \ 3047 out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), val) 3048 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3049 do {\ 3050 HWIO_INTLOCK(); \ 3051 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x)); \ 3052 HWIO_INTFREE();\ 3053 } while (0) 3054 3055 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3056 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3057 3058 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3059 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3060 3061 //// Register REO_R0_SW2REO_RING_MSI1_DATA //// 3062 3063 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x) (x+0x0000023c) 3064 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_PHYS(x) (x+0x0000023c) 3065 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK 0xffffffff 3066 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_SHFT 0 3067 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x) \ 3068 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK) 3069 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_INM(x, mask) \ 3070 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask) 3071 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUT(x, val) \ 3072 out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), val) 3073 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUTM(x, mask, val) \ 3074 do {\ 3075 HWIO_INTLOCK(); \ 3076 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x)); \ 3077 HWIO_INTFREE();\ 3078 } while (0) 3079 3080 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3081 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_SHFT 0x0 3082 3083 //// Register REO_R0_SW2REO_RING_HP_TP_SW_OFFSET //// 3084 3085 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000240) 3086 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000240) 3087 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3088 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_SHFT 0 3089 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x) \ 3090 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK) 3091 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3092 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3093 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3094 out_dword( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3095 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3096 do {\ 3097 HWIO_INTLOCK(); \ 3098 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x)); \ 3099 HWIO_INTFREE();\ 3100 } while (0) 3101 3102 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3103 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3104 3105 //// Register REO_R0_SW2REO1_RING_BASE_LSB //// 3106 3107 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x) (x+0x00000244) 3108 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_PHYS(x) (x+0x00000244) 3109 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RMSK 0xffffffff 3110 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_SHFT 0 3111 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_IN(x) \ 3112 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RMSK) 3113 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_INM(x, mask) \ 3114 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), mask) 3115 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OUT(x, val) \ 3116 out_dword( HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), val) 3117 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OUTM(x, mask, val) \ 3118 do {\ 3119 HWIO_INTLOCK(); \ 3120 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_BASE_LSB_IN(x)); \ 3121 HWIO_INTFREE();\ 3122 } while (0) 3123 3124 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3125 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3126 3127 //// Register REO_R0_SW2REO1_RING_BASE_MSB //// 3128 3129 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x) (x+0x00000248) 3130 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_PHYS(x) (x+0x00000248) 3131 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RMSK 0x00ffffff 3132 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_SHFT 0 3133 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_IN(x) \ 3134 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RMSK) 3135 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_INM(x, mask) \ 3136 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), mask) 3137 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OUT(x, val) \ 3138 out_dword( HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), val) 3139 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OUTM(x, mask, val) \ 3140 do {\ 3141 HWIO_INTLOCK(); \ 3142 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_BASE_MSB_IN(x)); \ 3143 HWIO_INTFREE();\ 3144 } while (0) 3145 3146 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3147 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3148 3149 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3150 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3151 3152 //// Register REO_R0_SW2REO1_RING_ID //// 3153 3154 #define HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x) (x+0x0000024c) 3155 #define HWIO_REO_R0_SW2REO1_RING_ID_PHYS(x) (x+0x0000024c) 3156 #define HWIO_REO_R0_SW2REO1_RING_ID_RMSK 0x000000ff 3157 #define HWIO_REO_R0_SW2REO1_RING_ID_SHFT 0 3158 #define HWIO_REO_R0_SW2REO1_RING_ID_IN(x) \ 3159 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), HWIO_REO_R0_SW2REO1_RING_ID_RMSK) 3160 #define HWIO_REO_R0_SW2REO1_RING_ID_INM(x, mask) \ 3161 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), mask) 3162 #define HWIO_REO_R0_SW2REO1_RING_ID_OUT(x, val) \ 3163 out_dword( HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), val) 3164 #define HWIO_REO_R0_SW2REO1_RING_ID_OUTM(x, mask, val) \ 3165 do {\ 3166 HWIO_INTLOCK(); \ 3167 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_ID_IN(x)); \ 3168 HWIO_INTFREE();\ 3169 } while (0) 3170 3171 #define HWIO_REO_R0_SW2REO1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3172 #define HWIO_REO_R0_SW2REO1_RING_ID_ENTRY_SIZE_SHFT 0x0 3173 3174 //// Register REO_R0_SW2REO1_RING_STATUS //// 3175 3176 #define HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x) (x+0x00000250) 3177 #define HWIO_REO_R0_SW2REO1_RING_STATUS_PHYS(x) (x+0x00000250) 3178 #define HWIO_REO_R0_SW2REO1_RING_STATUS_RMSK 0xffffffff 3179 #define HWIO_REO_R0_SW2REO1_RING_STATUS_SHFT 0 3180 #define HWIO_REO_R0_SW2REO1_RING_STATUS_IN(x) \ 3181 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), HWIO_REO_R0_SW2REO1_RING_STATUS_RMSK) 3182 #define HWIO_REO_R0_SW2REO1_RING_STATUS_INM(x, mask) \ 3183 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), mask) 3184 #define HWIO_REO_R0_SW2REO1_RING_STATUS_OUT(x, val) \ 3185 out_dword( HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), val) 3186 #define HWIO_REO_R0_SW2REO1_RING_STATUS_OUTM(x, mask, val) \ 3187 do {\ 3188 HWIO_INTLOCK(); \ 3189 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_STATUS_IN(x)); \ 3190 HWIO_INTFREE();\ 3191 } while (0) 3192 3193 #define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3194 #define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3195 3196 #define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3197 #define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3198 3199 //// Register REO_R0_SW2REO1_RING_MISC //// 3200 3201 #define HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x) (x+0x00000254) 3202 #define HWIO_REO_R0_SW2REO1_RING_MISC_PHYS(x) (x+0x00000254) 3203 #define HWIO_REO_R0_SW2REO1_RING_MISC_RMSK 0x003fffff 3204 #define HWIO_REO_R0_SW2REO1_RING_MISC_SHFT 0 3205 #define HWIO_REO_R0_SW2REO1_RING_MISC_IN(x) \ 3206 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MISC_RMSK) 3207 #define HWIO_REO_R0_SW2REO1_RING_MISC_INM(x, mask) \ 3208 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), mask) 3209 #define HWIO_REO_R0_SW2REO1_RING_MISC_OUT(x, val) \ 3210 out_dword( HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), val) 3211 #define HWIO_REO_R0_SW2REO1_RING_MISC_OUTM(x, mask, val) \ 3212 do {\ 3213 HWIO_INTLOCK(); \ 3214 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MISC_IN(x)); \ 3215 HWIO_INTFREE();\ 3216 } while (0) 3217 3218 #define HWIO_REO_R0_SW2REO1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3219 #define HWIO_REO_R0_SW2REO1_RING_MISC_SPARE_CONTROL_SHFT 0xe 3220 3221 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3222 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3223 3224 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3225 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3226 3227 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3228 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3229 3230 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3231 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_ENABLE_SHFT 0x6 3232 3233 #define HWIO_REO_R0_SW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3234 #define HWIO_REO_R0_SW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3235 3236 #define HWIO_REO_R0_SW2REO1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3237 #define HWIO_REO_R0_SW2REO1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3238 3239 #define HWIO_REO_R0_SW2REO1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3240 #define HWIO_REO_R0_SW2REO1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3241 3242 #define HWIO_REO_R0_SW2REO1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3243 #define HWIO_REO_R0_SW2REO1_RING_MISC_SECURITY_BIT_SHFT 0x2 3244 3245 #define HWIO_REO_R0_SW2REO1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3246 #define HWIO_REO_R0_SW2REO1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3247 3248 #define HWIO_REO_R0_SW2REO1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3249 #define HWIO_REO_R0_SW2REO1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3250 3251 //// Register REO_R0_SW2REO1_RING_TP_ADDR_LSB //// 3252 3253 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000260) 3254 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000260) 3255 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_RMSK 0xffffffff 3256 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_SHFT 0 3257 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_IN(x) \ 3258 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_RMSK) 3259 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_INM(x, mask) \ 3260 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), mask) 3261 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OUT(x, val) \ 3262 out_dword( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), val) 3263 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 3264 do {\ 3265 HWIO_INTLOCK(); \ 3266 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_IN(x)); \ 3267 HWIO_INTFREE();\ 3268 } while (0) 3269 3270 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 3271 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 3272 3273 //// Register REO_R0_SW2REO1_RING_TP_ADDR_MSB //// 3274 3275 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000264) 3276 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000264) 3277 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_RMSK 0x000000ff 3278 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_SHFT 0 3279 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_IN(x) \ 3280 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_RMSK) 3281 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_INM(x, mask) \ 3282 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), mask) 3283 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OUT(x, val) \ 3284 out_dword( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), val) 3285 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 3286 do {\ 3287 HWIO_INTLOCK(); \ 3288 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_IN(x)); \ 3289 HWIO_INTFREE();\ 3290 } while (0) 3291 3292 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 3293 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 3294 3295 //// Register REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0 //// 3296 3297 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000274) 3298 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000274) 3299 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 3300 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 3301 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 3302 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK) 3303 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 3304 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 3305 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 3306 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 3307 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 3308 do {\ 3309 HWIO_INTLOCK(); \ 3310 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 3311 HWIO_INTFREE();\ 3312 } while (0) 3313 3314 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3315 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3316 3317 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 3318 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 3319 3320 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3321 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3322 3323 //// Register REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1 //// 3324 3325 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000278) 3326 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000278) 3327 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 3328 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 3329 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 3330 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK) 3331 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 3332 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 3333 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 3334 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 3335 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 3336 do {\ 3337 HWIO_INTLOCK(); \ 3338 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 3339 HWIO_INTFREE();\ 3340 } while (0) 3341 3342 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 3343 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 3344 3345 //// Register REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS //// 3346 3347 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000027c) 3348 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000027c) 3349 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 3350 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_SHFT 0 3351 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_IN(x) \ 3352 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_RMSK) 3353 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 3354 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 3355 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 3356 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), val) 3357 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 3358 do {\ 3359 HWIO_INTLOCK(); \ 3360 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_IN(x)); \ 3361 HWIO_INTFREE();\ 3362 } while (0) 3363 3364 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3365 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3366 3367 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 3368 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 3369 3370 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3371 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3372 3373 //// Register REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER //// 3374 3375 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000280) 3376 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000280) 3377 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 3378 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 3379 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 3380 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK) 3381 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 3382 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 3383 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 3384 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 3385 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 3386 do {\ 3387 HWIO_INTLOCK(); \ 3388 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 3389 HWIO_INTFREE();\ 3390 } while (0) 3391 3392 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 3393 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 3394 3395 //// Register REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER //// 3396 3397 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000284) 3398 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000284) 3399 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 3400 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 3401 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 3402 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK) 3403 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 3404 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 3405 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 3406 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 3407 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 3408 do {\ 3409 HWIO_INTLOCK(); \ 3410 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 3411 HWIO_INTFREE();\ 3412 } while (0) 3413 3414 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 3415 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 3416 3417 //// Register REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS //// 3418 3419 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000288) 3420 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000288) 3421 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 3422 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 3423 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 3424 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK) 3425 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 3426 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 3427 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 3428 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 3429 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 3430 do {\ 3431 HWIO_INTLOCK(); \ 3432 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 3433 HWIO_INTFREE();\ 3434 } while (0) 3435 3436 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 3437 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 3438 3439 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 3440 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 3441 3442 //// Register REO_R0_SW2REO1_RING_MSI1_BASE_LSB //// 3443 3444 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000028c) 3445 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000028c) 3446 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3447 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_SHFT 0 3448 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_IN(x) \ 3449 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_RMSK) 3450 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_INM(x, mask) \ 3451 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask) 3452 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OUT(x, val) \ 3453 out_dword( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), val) 3454 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3455 do {\ 3456 HWIO_INTLOCK(); \ 3457 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_IN(x)); \ 3458 HWIO_INTFREE();\ 3459 } while (0) 3460 3461 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3462 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3463 3464 //// Register REO_R0_SW2REO1_RING_MSI1_BASE_MSB //// 3465 3466 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000290) 3467 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000290) 3468 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3469 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_SHFT 0 3470 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_IN(x) \ 3471 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_RMSK) 3472 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_INM(x, mask) \ 3473 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask) 3474 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OUT(x, val) \ 3475 out_dword( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), val) 3476 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3477 do {\ 3478 HWIO_INTLOCK(); \ 3479 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_IN(x)); \ 3480 HWIO_INTFREE();\ 3481 } while (0) 3482 3483 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3484 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3485 3486 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3487 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3488 3489 //// Register REO_R0_SW2REO1_RING_MSI1_DATA //// 3490 3491 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x) (x+0x00000294) 3492 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_PHYS(x) (x+0x00000294) 3493 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_RMSK 0xffffffff 3494 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_SHFT 0 3495 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_IN(x) \ 3496 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_RMSK) 3497 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_INM(x, mask) \ 3498 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), mask) 3499 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OUT(x, val) \ 3500 out_dword( HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), val) 3501 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OUTM(x, mask, val) \ 3502 do {\ 3503 HWIO_INTLOCK(); \ 3504 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_IN(x)); \ 3505 HWIO_INTFREE();\ 3506 } while (0) 3507 3508 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3509 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_VALUE_SHFT 0x0 3510 3511 //// Register REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET //// 3512 3513 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000298) 3514 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000298) 3515 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3516 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_SHFT 0 3517 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_IN(x) \ 3518 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_RMSK) 3519 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3520 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3521 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3522 out_dword( HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3523 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3524 do {\ 3525 HWIO_INTLOCK(); \ 3526 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_IN(x)); \ 3527 HWIO_INTFREE();\ 3528 } while (0) 3529 3530 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3531 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3532 3533 //// Register REO_R0_REO2SW1_RING_BASE_LSB //// 3534 3535 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) (x+0x0000029c) 3536 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_PHYS(x) (x+0x0000029c) 3537 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK 0xffffffff 3538 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_SHFT 0 3539 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x) \ 3540 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK) 3541 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_INM(x, mask) \ 3542 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask) 3543 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUT(x, val) \ 3544 out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), val) 3545 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUTM(x, mask, val) \ 3546 do {\ 3547 HWIO_INTLOCK(); \ 3548 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x)); \ 3549 HWIO_INTFREE();\ 3550 } while (0) 3551 3552 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3553 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3554 3555 //// Register REO_R0_REO2SW1_RING_BASE_MSB //// 3556 3557 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) (x+0x000002a0) 3558 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_PHYS(x) (x+0x000002a0) 3559 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK 0x0fffffff 3560 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_SHFT 0 3561 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x) \ 3562 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK) 3563 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_INM(x, mask) \ 3564 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask) 3565 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUT(x, val) \ 3566 out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), val) 3567 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUTM(x, mask, val) \ 3568 do {\ 3569 HWIO_INTLOCK(); \ 3570 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x)); \ 3571 HWIO_INTFREE();\ 3572 } while (0) 3573 3574 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 3575 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3576 3577 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3578 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3579 3580 //// Register REO_R0_REO2SW1_RING_ID //// 3581 3582 #define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) (x+0x000002a4) 3583 #define HWIO_REO_R0_REO2SW1_RING_ID_PHYS(x) (x+0x000002a4) 3584 #define HWIO_REO_R0_REO2SW1_RING_ID_RMSK 0x0000ffff 3585 #define HWIO_REO_R0_REO2SW1_RING_ID_SHFT 0 3586 #define HWIO_REO_R0_REO2SW1_RING_ID_IN(x) \ 3587 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW1_RING_ID_RMSK) 3588 #define HWIO_REO_R0_REO2SW1_RING_ID_INM(x, mask) \ 3589 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask) 3590 #define HWIO_REO_R0_REO2SW1_RING_ID_OUT(x, val) \ 3591 out_dword( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), val) 3592 #define HWIO_REO_R0_REO2SW1_RING_ID_OUTM(x, mask, val) \ 3593 do {\ 3594 HWIO_INTLOCK(); \ 3595 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_ID_IN(x)); \ 3596 HWIO_INTFREE();\ 3597 } while (0) 3598 3599 #define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_BMSK 0x0000ff00 3600 #define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_SHFT 0x8 3601 3602 #define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3603 #define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_SHFT 0x0 3604 3605 //// Register REO_R0_REO2SW1_RING_STATUS //// 3606 3607 #define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x) (x+0x000002a8) 3608 #define HWIO_REO_R0_REO2SW1_RING_STATUS_PHYS(x) (x+0x000002a8) 3609 #define HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK 0xffffffff 3610 #define HWIO_REO_R0_REO2SW1_RING_STATUS_SHFT 0 3611 #define HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x) \ 3612 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK) 3613 #define HWIO_REO_R0_REO2SW1_RING_STATUS_INM(x, mask) \ 3614 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask) 3615 #define HWIO_REO_R0_REO2SW1_RING_STATUS_OUT(x, val) \ 3616 out_dword( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), val) 3617 #define HWIO_REO_R0_REO2SW1_RING_STATUS_OUTM(x, mask, val) \ 3618 do {\ 3619 HWIO_INTLOCK(); \ 3620 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x)); \ 3621 HWIO_INTFREE();\ 3622 } while (0) 3623 3624 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3625 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3626 3627 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3628 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3629 3630 //// Register REO_R0_REO2SW1_RING_MISC //// 3631 3632 #define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) (x+0x000002ac) 3633 #define HWIO_REO_R0_REO2SW1_RING_MISC_PHYS(x) (x+0x000002ac) 3634 #define HWIO_REO_R0_REO2SW1_RING_MISC_RMSK 0x03ffffff 3635 #define HWIO_REO_R0_REO2SW1_RING_MISC_SHFT 0 3636 #define HWIO_REO_R0_REO2SW1_RING_MISC_IN(x) \ 3637 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MISC_RMSK) 3638 #define HWIO_REO_R0_REO2SW1_RING_MISC_INM(x, mask) \ 3639 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask) 3640 #define HWIO_REO_R0_REO2SW1_RING_MISC_OUT(x, val) \ 3641 out_dword( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), val) 3642 #define HWIO_REO_R0_REO2SW1_RING_MISC_OUTM(x, mask, val) \ 3643 do {\ 3644 HWIO_INTLOCK(); \ 3645 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MISC_IN(x)); \ 3646 HWIO_INTFREE();\ 3647 } while (0) 3648 3649 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3650 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_SHFT 0x16 3651 3652 #define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3653 #define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_SHFT 0xe 3654 3655 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3656 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3657 3658 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3659 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3660 3661 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3662 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3663 3664 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3665 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_SHFT 0x6 3666 3667 #define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3668 #define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3669 3670 #define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3671 #define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3672 3673 #define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3674 #define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3675 3676 #define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3677 #define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_SHFT 0x2 3678 3679 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3680 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3681 3682 #define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3683 #define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3684 3685 //// Register REO_R0_REO2SW1_RING_HP_ADDR_LSB //// 3686 3687 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) (x+0x000002b0) 3688 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_PHYS(x) (x+0x000002b0) 3689 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK 0xffffffff 3690 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_SHFT 0 3691 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x) \ 3692 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK) 3693 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_INM(x, mask) \ 3694 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask) 3695 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUT(x, val) \ 3696 out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), val) 3697 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3698 do {\ 3699 HWIO_INTLOCK(); \ 3700 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x)); \ 3701 HWIO_INTFREE();\ 3702 } while (0) 3703 3704 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3705 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3706 3707 //// Register REO_R0_REO2SW1_RING_HP_ADDR_MSB //// 3708 3709 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) (x+0x000002b4) 3710 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_PHYS(x) (x+0x000002b4) 3711 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK 0x000000ff 3712 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_SHFT 0 3713 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x) \ 3714 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK) 3715 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_INM(x, mask) \ 3716 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask) 3717 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUT(x, val) \ 3718 out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), val) 3719 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3720 do {\ 3721 HWIO_INTLOCK(); \ 3722 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x)); \ 3723 HWIO_INTFREE();\ 3724 } while (0) 3725 3726 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3727 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3728 3729 //// Register REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP //// 3730 3731 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000002c0) 3732 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000002c0) 3733 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3734 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SHFT 0 3735 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x) \ 3736 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK) 3737 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3738 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3739 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3740 out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3741 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3742 do {\ 3743 HWIO_INTLOCK(); \ 3744 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x)); \ 3745 HWIO_INTFREE();\ 3746 } while (0) 3747 3748 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3749 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3750 3751 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3752 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3753 3754 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3755 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3756 3757 //// Register REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS //// 3758 3759 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000002c4) 3760 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000002c4) 3761 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3762 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_SHFT 0 3763 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x) \ 3764 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK) 3765 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3766 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3767 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3768 out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3769 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3770 do {\ 3771 HWIO_INTLOCK(); \ 3772 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x)); \ 3773 HWIO_INTFREE();\ 3774 } while (0) 3775 3776 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3777 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3778 3779 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3780 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3781 3782 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3783 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3784 3785 //// Register REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER //// 3786 3787 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000002c8) 3788 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000002c8) 3789 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3790 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_SHFT 0 3791 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3792 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK) 3793 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3794 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3795 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3796 out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3797 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3798 do {\ 3799 HWIO_INTLOCK(); \ 3800 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3801 HWIO_INTFREE();\ 3802 } while (0) 3803 3804 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3805 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3806 3807 //// Register REO_R0_REO2SW1_RING_MSI1_BASE_LSB //// 3808 3809 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000002e4) 3810 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000002e4) 3811 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3812 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_SHFT 0 3813 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x) \ 3814 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK) 3815 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_INM(x, mask) \ 3816 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask) 3817 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUT(x, val) \ 3818 out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), val) 3819 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3820 do {\ 3821 HWIO_INTLOCK(); \ 3822 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x)); \ 3823 HWIO_INTFREE();\ 3824 } while (0) 3825 3826 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3827 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3828 3829 //// Register REO_R0_REO2SW1_RING_MSI1_BASE_MSB //// 3830 3831 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000002e8) 3832 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000002e8) 3833 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3834 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_SHFT 0 3835 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x) \ 3836 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK) 3837 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_INM(x, mask) \ 3838 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask) 3839 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUT(x, val) \ 3840 out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), val) 3841 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3842 do {\ 3843 HWIO_INTLOCK(); \ 3844 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x)); \ 3845 HWIO_INTFREE();\ 3846 } while (0) 3847 3848 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3849 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3850 3851 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3852 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3853 3854 //// Register REO_R0_REO2SW1_RING_MSI1_DATA //// 3855 3856 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) (x+0x000002ec) 3857 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_PHYS(x) (x+0x000002ec) 3858 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK 0xffffffff 3859 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_SHFT 0 3860 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x) \ 3861 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK) 3862 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_INM(x, mask) \ 3863 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask) 3864 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUT(x, val) \ 3865 out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), val) 3866 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUTM(x, mask, val) \ 3867 do {\ 3868 HWIO_INTLOCK(); \ 3869 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x)); \ 3870 HWIO_INTFREE();\ 3871 } while (0) 3872 3873 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3874 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_SHFT 0x0 3875 3876 //// Register REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET //// 3877 3878 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002f0) 3879 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002f0) 3880 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3881 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_SHFT 0 3882 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x) \ 3883 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK) 3884 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3885 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3886 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3887 out_dword( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3888 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3889 do {\ 3890 HWIO_INTLOCK(); \ 3891 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x)); \ 3892 HWIO_INTFREE();\ 3893 } while (0) 3894 3895 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3896 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3897 3898 //// Register REO_R0_REO2SW2_RING_BASE_LSB //// 3899 3900 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) (x+0x000002f4) 3901 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_PHYS(x) (x+0x000002f4) 3902 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK 0xffffffff 3903 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_SHFT 0 3904 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x) \ 3905 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK) 3906 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_INM(x, mask) \ 3907 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask) 3908 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUT(x, val) \ 3909 out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), val) 3910 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUTM(x, mask, val) \ 3911 do {\ 3912 HWIO_INTLOCK(); \ 3913 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x)); \ 3914 HWIO_INTFREE();\ 3915 } while (0) 3916 3917 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3918 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3919 3920 //// Register REO_R0_REO2SW2_RING_BASE_MSB //// 3921 3922 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x) (x+0x000002f8) 3923 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_PHYS(x) (x+0x000002f8) 3924 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK 0x0fffffff 3925 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_SHFT 0 3926 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x) \ 3927 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK) 3928 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_INM(x, mask) \ 3929 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask) 3930 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUT(x, val) \ 3931 out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), val) 3932 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUTM(x, mask, val) \ 3933 do {\ 3934 HWIO_INTLOCK(); \ 3935 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x)); \ 3936 HWIO_INTFREE();\ 3937 } while (0) 3938 3939 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 3940 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3941 3942 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3943 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3944 3945 //// Register REO_R0_REO2SW2_RING_ID //// 3946 3947 #define HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x) (x+0x000002fc) 3948 #define HWIO_REO_R0_REO2SW2_RING_ID_PHYS(x) (x+0x000002fc) 3949 #define HWIO_REO_R0_REO2SW2_RING_ID_RMSK 0x0000ffff 3950 #define HWIO_REO_R0_REO2SW2_RING_ID_SHFT 0 3951 #define HWIO_REO_R0_REO2SW2_RING_ID_IN(x) \ 3952 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW2_RING_ID_RMSK) 3953 #define HWIO_REO_R0_REO2SW2_RING_ID_INM(x, mask) \ 3954 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask) 3955 #define HWIO_REO_R0_REO2SW2_RING_ID_OUT(x, val) \ 3956 out_dword( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), val) 3957 #define HWIO_REO_R0_REO2SW2_RING_ID_OUTM(x, mask, val) \ 3958 do {\ 3959 HWIO_INTLOCK(); \ 3960 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_ID_IN(x)); \ 3961 HWIO_INTFREE();\ 3962 } while (0) 3963 3964 #define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_BMSK 0x0000ff00 3965 #define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_SHFT 0x8 3966 3967 #define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3968 #define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_SHFT 0x0 3969 3970 //// Register REO_R0_REO2SW2_RING_STATUS //// 3971 3972 #define HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x) (x+0x00000300) 3973 #define HWIO_REO_R0_REO2SW2_RING_STATUS_PHYS(x) (x+0x00000300) 3974 #define HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK 0xffffffff 3975 #define HWIO_REO_R0_REO2SW2_RING_STATUS_SHFT 0 3976 #define HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x) \ 3977 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK) 3978 #define HWIO_REO_R0_REO2SW2_RING_STATUS_INM(x, mask) \ 3979 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask) 3980 #define HWIO_REO_R0_REO2SW2_RING_STATUS_OUT(x, val) \ 3981 out_dword( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), val) 3982 #define HWIO_REO_R0_REO2SW2_RING_STATUS_OUTM(x, mask, val) \ 3983 do {\ 3984 HWIO_INTLOCK(); \ 3985 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x)); \ 3986 HWIO_INTFREE();\ 3987 } while (0) 3988 3989 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3990 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3991 3992 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3993 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3994 3995 //// Register REO_R0_REO2SW2_RING_MISC //// 3996 3997 #define HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x) (x+0x00000304) 3998 #define HWIO_REO_R0_REO2SW2_RING_MISC_PHYS(x) (x+0x00000304) 3999 #define HWIO_REO_R0_REO2SW2_RING_MISC_RMSK 0x03ffffff 4000 #define HWIO_REO_R0_REO2SW2_RING_MISC_SHFT 0 4001 #define HWIO_REO_R0_REO2SW2_RING_MISC_IN(x) \ 4002 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MISC_RMSK) 4003 #define HWIO_REO_R0_REO2SW2_RING_MISC_INM(x, mask) \ 4004 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask) 4005 #define HWIO_REO_R0_REO2SW2_RING_MISC_OUT(x, val) \ 4006 out_dword( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), val) 4007 #define HWIO_REO_R0_REO2SW2_RING_MISC_OUTM(x, mask, val) \ 4008 do {\ 4009 HWIO_INTLOCK(); \ 4010 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MISC_IN(x)); \ 4011 HWIO_INTFREE();\ 4012 } while (0) 4013 4014 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4015 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_SHFT 0x16 4016 4017 #define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4018 #define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_SHFT 0xe 4019 4020 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4021 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4022 4023 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4024 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4025 4026 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4027 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4028 4029 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 4030 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_SHFT 0x6 4031 4032 #define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4033 #define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4034 4035 #define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4036 #define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4037 4038 #define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4039 #define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4040 4041 #define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4042 #define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_SHFT 0x2 4043 4044 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4045 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4046 4047 #define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4048 #define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4049 4050 //// Register REO_R0_REO2SW2_RING_HP_ADDR_LSB //// 4051 4052 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000308) 4053 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000308) 4054 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK 0xffffffff 4055 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_SHFT 0 4056 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x) \ 4057 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK) 4058 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_INM(x, mask) \ 4059 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask) 4060 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUT(x, val) \ 4061 out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), val) 4062 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4063 do {\ 4064 HWIO_INTLOCK(); \ 4065 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x)); \ 4066 HWIO_INTFREE();\ 4067 } while (0) 4068 4069 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4070 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4071 4072 //// Register REO_R0_REO2SW2_RING_HP_ADDR_MSB //// 4073 4074 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000030c) 4075 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000030c) 4076 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK 0x000000ff 4077 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_SHFT 0 4078 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x) \ 4079 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK) 4080 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_INM(x, mask) \ 4081 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask) 4082 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUT(x, val) \ 4083 out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), val) 4084 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4085 do {\ 4086 HWIO_INTLOCK(); \ 4087 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x)); \ 4088 HWIO_INTFREE();\ 4089 } while (0) 4090 4091 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4092 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4093 4094 //// Register REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP //// 4095 4096 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000318) 4097 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000318) 4098 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4099 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SHFT 0 4100 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x) \ 4101 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK) 4102 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4103 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4104 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4105 out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4106 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4107 do {\ 4108 HWIO_INTLOCK(); \ 4109 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x)); \ 4110 HWIO_INTFREE();\ 4111 } while (0) 4112 4113 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4114 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4115 4116 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4117 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4118 4119 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4120 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4121 4122 //// Register REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS //// 4123 4124 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000031c) 4125 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000031c) 4126 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4127 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_SHFT 0 4128 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x) \ 4129 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK) 4130 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4131 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4132 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4133 out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4134 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4135 do {\ 4136 HWIO_INTLOCK(); \ 4137 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x)); \ 4138 HWIO_INTFREE();\ 4139 } while (0) 4140 4141 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4142 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4143 4144 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4145 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4146 4147 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4148 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4149 4150 //// Register REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER //// 4151 4152 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000320) 4153 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000320) 4154 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4155 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_SHFT 0 4156 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4157 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK) 4158 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4159 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4160 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4161 out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4162 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4163 do {\ 4164 HWIO_INTLOCK(); \ 4165 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4166 HWIO_INTFREE();\ 4167 } while (0) 4168 4169 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4170 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4171 4172 //// Register REO_R0_REO2SW2_RING_MSI1_BASE_LSB //// 4173 4174 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000033c) 4175 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000033c) 4176 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4177 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_SHFT 0 4178 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x) \ 4179 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK) 4180 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_INM(x, mask) \ 4181 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask) 4182 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUT(x, val) \ 4183 out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), val) 4184 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4185 do {\ 4186 HWIO_INTLOCK(); \ 4187 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x)); \ 4188 HWIO_INTFREE();\ 4189 } while (0) 4190 4191 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4192 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4193 4194 //// Register REO_R0_REO2SW2_RING_MSI1_BASE_MSB //// 4195 4196 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000340) 4197 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000340) 4198 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4199 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_SHFT 0 4200 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x) \ 4201 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK) 4202 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_INM(x, mask) \ 4203 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask) 4204 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUT(x, val) \ 4205 out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), val) 4206 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4207 do {\ 4208 HWIO_INTLOCK(); \ 4209 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x)); \ 4210 HWIO_INTFREE();\ 4211 } while (0) 4212 4213 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4214 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4215 4216 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4217 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4218 4219 //// Register REO_R0_REO2SW2_RING_MSI1_DATA //// 4220 4221 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x) (x+0x00000344) 4222 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_PHYS(x) (x+0x00000344) 4223 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK 0xffffffff 4224 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_SHFT 0 4225 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x) \ 4226 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK) 4227 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_INM(x, mask) \ 4228 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask) 4229 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUT(x, val) \ 4230 out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), val) 4231 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUTM(x, mask, val) \ 4232 do {\ 4233 HWIO_INTLOCK(); \ 4234 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x)); \ 4235 HWIO_INTFREE();\ 4236 } while (0) 4237 4238 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4239 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_SHFT 0x0 4240 4241 //// Register REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET //// 4242 4243 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000348) 4244 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000348) 4245 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4246 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_SHFT 0 4247 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x) \ 4248 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK) 4249 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4250 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4251 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4252 out_dword( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4253 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4254 do {\ 4255 HWIO_INTLOCK(); \ 4256 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x)); \ 4257 HWIO_INTFREE();\ 4258 } while (0) 4259 4260 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4261 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4262 4263 //// Register REO_R0_REO2SW3_RING_BASE_LSB //// 4264 4265 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x) (x+0x0000034c) 4266 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_PHYS(x) (x+0x0000034c) 4267 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK 0xffffffff 4268 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_SHFT 0 4269 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x) \ 4270 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK) 4271 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_INM(x, mask) \ 4272 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask) 4273 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUT(x, val) \ 4274 out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), val) 4275 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUTM(x, mask, val) \ 4276 do {\ 4277 HWIO_INTLOCK(); \ 4278 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x)); \ 4279 HWIO_INTFREE();\ 4280 } while (0) 4281 4282 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4283 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4284 4285 //// Register REO_R0_REO2SW3_RING_BASE_MSB //// 4286 4287 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x) (x+0x00000350) 4288 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_PHYS(x) (x+0x00000350) 4289 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK 0x0fffffff 4290 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_SHFT 0 4291 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x) \ 4292 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK) 4293 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_INM(x, mask) \ 4294 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask) 4295 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUT(x, val) \ 4296 out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), val) 4297 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUTM(x, mask, val) \ 4298 do {\ 4299 HWIO_INTLOCK(); \ 4300 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x)); \ 4301 HWIO_INTFREE();\ 4302 } while (0) 4303 4304 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 4305 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4306 4307 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4308 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4309 4310 //// Register REO_R0_REO2SW3_RING_ID //// 4311 4312 #define HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x) (x+0x00000354) 4313 #define HWIO_REO_R0_REO2SW3_RING_ID_PHYS(x) (x+0x00000354) 4314 #define HWIO_REO_R0_REO2SW3_RING_ID_RMSK 0x0000ffff 4315 #define HWIO_REO_R0_REO2SW3_RING_ID_SHFT 0 4316 #define HWIO_REO_R0_REO2SW3_RING_ID_IN(x) \ 4317 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW3_RING_ID_RMSK) 4318 #define HWIO_REO_R0_REO2SW3_RING_ID_INM(x, mask) \ 4319 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask) 4320 #define HWIO_REO_R0_REO2SW3_RING_ID_OUT(x, val) \ 4321 out_dword( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), val) 4322 #define HWIO_REO_R0_REO2SW3_RING_ID_OUTM(x, mask, val) \ 4323 do {\ 4324 HWIO_INTLOCK(); \ 4325 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_ID_IN(x)); \ 4326 HWIO_INTFREE();\ 4327 } while (0) 4328 4329 #define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_BMSK 0x0000ff00 4330 #define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_SHFT 0x8 4331 4332 #define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4333 #define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_SHFT 0x0 4334 4335 //// Register REO_R0_REO2SW3_RING_STATUS //// 4336 4337 #define HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x) (x+0x00000358) 4338 #define HWIO_REO_R0_REO2SW3_RING_STATUS_PHYS(x) (x+0x00000358) 4339 #define HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK 0xffffffff 4340 #define HWIO_REO_R0_REO2SW3_RING_STATUS_SHFT 0 4341 #define HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x) \ 4342 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK) 4343 #define HWIO_REO_R0_REO2SW3_RING_STATUS_INM(x, mask) \ 4344 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask) 4345 #define HWIO_REO_R0_REO2SW3_RING_STATUS_OUT(x, val) \ 4346 out_dword( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), val) 4347 #define HWIO_REO_R0_REO2SW3_RING_STATUS_OUTM(x, mask, val) \ 4348 do {\ 4349 HWIO_INTLOCK(); \ 4350 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x)); \ 4351 HWIO_INTFREE();\ 4352 } while (0) 4353 4354 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4355 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4356 4357 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4358 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4359 4360 //// Register REO_R0_REO2SW3_RING_MISC //// 4361 4362 #define HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x) (x+0x0000035c) 4363 #define HWIO_REO_R0_REO2SW3_RING_MISC_PHYS(x) (x+0x0000035c) 4364 #define HWIO_REO_R0_REO2SW3_RING_MISC_RMSK 0x03ffffff 4365 #define HWIO_REO_R0_REO2SW3_RING_MISC_SHFT 0 4366 #define HWIO_REO_R0_REO2SW3_RING_MISC_IN(x) \ 4367 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MISC_RMSK) 4368 #define HWIO_REO_R0_REO2SW3_RING_MISC_INM(x, mask) \ 4369 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask) 4370 #define HWIO_REO_R0_REO2SW3_RING_MISC_OUT(x, val) \ 4371 out_dword( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), val) 4372 #define HWIO_REO_R0_REO2SW3_RING_MISC_OUTM(x, mask, val) \ 4373 do {\ 4374 HWIO_INTLOCK(); \ 4375 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MISC_IN(x)); \ 4376 HWIO_INTFREE();\ 4377 } while (0) 4378 4379 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4380 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_SHFT 0x16 4381 4382 #define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4383 #define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_SHFT 0xe 4384 4385 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4386 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4387 4388 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4389 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4390 4391 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4392 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4393 4394 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 4395 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_SHFT 0x6 4396 4397 #define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4398 #define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4399 4400 #define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4401 #define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4402 4403 #define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4404 #define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4405 4406 #define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4407 #define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_SHFT 0x2 4408 4409 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4410 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4411 4412 #define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4413 #define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4414 4415 //// Register REO_R0_REO2SW3_RING_HP_ADDR_LSB //// 4416 4417 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000360) 4418 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000360) 4419 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK 0xffffffff 4420 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_SHFT 0 4421 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x) \ 4422 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK) 4423 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_INM(x, mask) \ 4424 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask) 4425 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUT(x, val) \ 4426 out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), val) 4427 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4428 do {\ 4429 HWIO_INTLOCK(); \ 4430 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x)); \ 4431 HWIO_INTFREE();\ 4432 } while (0) 4433 4434 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4435 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4436 4437 //// Register REO_R0_REO2SW3_RING_HP_ADDR_MSB //// 4438 4439 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000364) 4440 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000364) 4441 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK 0x000000ff 4442 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_SHFT 0 4443 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x) \ 4444 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK) 4445 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_INM(x, mask) \ 4446 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask) 4447 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUT(x, val) \ 4448 out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), val) 4449 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4450 do {\ 4451 HWIO_INTLOCK(); \ 4452 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x)); \ 4453 HWIO_INTFREE();\ 4454 } while (0) 4455 4456 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4457 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4458 4459 //// Register REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP //// 4460 4461 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000370) 4462 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000370) 4463 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4464 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SHFT 0 4465 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x) \ 4466 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK) 4467 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4468 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4469 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4470 out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4471 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4472 do {\ 4473 HWIO_INTLOCK(); \ 4474 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x)); \ 4475 HWIO_INTFREE();\ 4476 } while (0) 4477 4478 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4479 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4480 4481 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4482 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4483 4484 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4485 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4486 4487 //// Register REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS //// 4488 4489 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000374) 4490 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000374) 4491 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4492 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_SHFT 0 4493 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x) \ 4494 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK) 4495 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4496 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4497 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4498 out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4499 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4500 do {\ 4501 HWIO_INTLOCK(); \ 4502 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x)); \ 4503 HWIO_INTFREE();\ 4504 } while (0) 4505 4506 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4507 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4508 4509 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4510 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4511 4512 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4513 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4514 4515 //// Register REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER //// 4516 4517 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000378) 4518 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000378) 4519 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4520 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_SHFT 0 4521 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4522 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK) 4523 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4524 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4525 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4526 out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4527 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4528 do {\ 4529 HWIO_INTLOCK(); \ 4530 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4531 HWIO_INTFREE();\ 4532 } while (0) 4533 4534 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4535 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4536 4537 //// Register REO_R0_REO2SW3_RING_MSI1_BASE_LSB //// 4538 4539 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000394) 4540 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000394) 4541 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4542 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_SHFT 0 4543 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x) \ 4544 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK) 4545 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_INM(x, mask) \ 4546 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask) 4547 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUT(x, val) \ 4548 out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), val) 4549 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4550 do {\ 4551 HWIO_INTLOCK(); \ 4552 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x)); \ 4553 HWIO_INTFREE();\ 4554 } while (0) 4555 4556 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4557 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4558 4559 //// Register REO_R0_REO2SW3_RING_MSI1_BASE_MSB //// 4560 4561 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000398) 4562 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000398) 4563 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4564 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_SHFT 0 4565 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x) \ 4566 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK) 4567 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_INM(x, mask) \ 4568 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask) 4569 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUT(x, val) \ 4570 out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), val) 4571 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4572 do {\ 4573 HWIO_INTLOCK(); \ 4574 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x)); \ 4575 HWIO_INTFREE();\ 4576 } while (0) 4577 4578 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4579 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4580 4581 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4582 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4583 4584 //// Register REO_R0_REO2SW3_RING_MSI1_DATA //// 4585 4586 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x) (x+0x0000039c) 4587 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_PHYS(x) (x+0x0000039c) 4588 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK 0xffffffff 4589 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_SHFT 0 4590 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x) \ 4591 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK) 4592 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_INM(x, mask) \ 4593 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask) 4594 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUT(x, val) \ 4595 out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), val) 4596 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUTM(x, mask, val) \ 4597 do {\ 4598 HWIO_INTLOCK(); \ 4599 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x)); \ 4600 HWIO_INTFREE();\ 4601 } while (0) 4602 4603 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4604 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_SHFT 0x0 4605 4606 //// Register REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET //// 4607 4608 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003a0) 4609 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003a0) 4610 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4611 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_SHFT 0 4612 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x) \ 4613 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK) 4614 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4615 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4616 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4617 out_dword( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4618 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4619 do {\ 4620 HWIO_INTLOCK(); \ 4621 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x)); \ 4622 HWIO_INTFREE();\ 4623 } while (0) 4624 4625 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4626 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4627 4628 //// Register REO_R0_REO2SW4_RING_BASE_LSB //// 4629 4630 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x) (x+0x000003a4) 4631 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_PHYS(x) (x+0x000003a4) 4632 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK 0xffffffff 4633 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_SHFT 0 4634 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x) \ 4635 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK) 4636 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_INM(x, mask) \ 4637 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask) 4638 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUT(x, val) \ 4639 out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), val) 4640 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUTM(x, mask, val) \ 4641 do {\ 4642 HWIO_INTLOCK(); \ 4643 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x)); \ 4644 HWIO_INTFREE();\ 4645 } while (0) 4646 4647 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4648 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4649 4650 //// Register REO_R0_REO2SW4_RING_BASE_MSB //// 4651 4652 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x) (x+0x000003a8) 4653 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_PHYS(x) (x+0x000003a8) 4654 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK 0x0fffffff 4655 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_SHFT 0 4656 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x) \ 4657 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK) 4658 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_INM(x, mask) \ 4659 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask) 4660 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUT(x, val) \ 4661 out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), val) 4662 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUTM(x, mask, val) \ 4663 do {\ 4664 HWIO_INTLOCK(); \ 4665 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x)); \ 4666 HWIO_INTFREE();\ 4667 } while (0) 4668 4669 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 4670 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4671 4672 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4673 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4674 4675 //// Register REO_R0_REO2SW4_RING_ID //// 4676 4677 #define HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x) (x+0x000003ac) 4678 #define HWIO_REO_R0_REO2SW4_RING_ID_PHYS(x) (x+0x000003ac) 4679 #define HWIO_REO_R0_REO2SW4_RING_ID_RMSK 0x0000ffff 4680 #define HWIO_REO_R0_REO2SW4_RING_ID_SHFT 0 4681 #define HWIO_REO_R0_REO2SW4_RING_ID_IN(x) \ 4682 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW4_RING_ID_RMSK) 4683 #define HWIO_REO_R0_REO2SW4_RING_ID_INM(x, mask) \ 4684 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask) 4685 #define HWIO_REO_R0_REO2SW4_RING_ID_OUT(x, val) \ 4686 out_dword( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), val) 4687 #define HWIO_REO_R0_REO2SW4_RING_ID_OUTM(x, mask, val) \ 4688 do {\ 4689 HWIO_INTLOCK(); \ 4690 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_ID_IN(x)); \ 4691 HWIO_INTFREE();\ 4692 } while (0) 4693 4694 #define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_BMSK 0x0000ff00 4695 #define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_SHFT 0x8 4696 4697 #define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4698 #define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_SHFT 0x0 4699 4700 //// Register REO_R0_REO2SW4_RING_STATUS //// 4701 4702 #define HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x) (x+0x000003b0) 4703 #define HWIO_REO_R0_REO2SW4_RING_STATUS_PHYS(x) (x+0x000003b0) 4704 #define HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK 0xffffffff 4705 #define HWIO_REO_R0_REO2SW4_RING_STATUS_SHFT 0 4706 #define HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x) \ 4707 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK) 4708 #define HWIO_REO_R0_REO2SW4_RING_STATUS_INM(x, mask) \ 4709 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask) 4710 #define HWIO_REO_R0_REO2SW4_RING_STATUS_OUT(x, val) \ 4711 out_dword( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), val) 4712 #define HWIO_REO_R0_REO2SW4_RING_STATUS_OUTM(x, mask, val) \ 4713 do {\ 4714 HWIO_INTLOCK(); \ 4715 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x)); \ 4716 HWIO_INTFREE();\ 4717 } while (0) 4718 4719 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4720 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4721 4722 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4723 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4724 4725 //// Register REO_R0_REO2SW4_RING_MISC //// 4726 4727 #define HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x) (x+0x000003b4) 4728 #define HWIO_REO_R0_REO2SW4_RING_MISC_PHYS(x) (x+0x000003b4) 4729 #define HWIO_REO_R0_REO2SW4_RING_MISC_RMSK 0x03ffffff 4730 #define HWIO_REO_R0_REO2SW4_RING_MISC_SHFT 0 4731 #define HWIO_REO_R0_REO2SW4_RING_MISC_IN(x) \ 4732 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MISC_RMSK) 4733 #define HWIO_REO_R0_REO2SW4_RING_MISC_INM(x, mask) \ 4734 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask) 4735 #define HWIO_REO_R0_REO2SW4_RING_MISC_OUT(x, val) \ 4736 out_dword( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), val) 4737 #define HWIO_REO_R0_REO2SW4_RING_MISC_OUTM(x, mask, val) \ 4738 do {\ 4739 HWIO_INTLOCK(); \ 4740 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MISC_IN(x)); \ 4741 HWIO_INTFREE();\ 4742 } while (0) 4743 4744 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4745 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_SHFT 0x16 4746 4747 #define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4748 #define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_SHFT 0xe 4749 4750 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4751 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4752 4753 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4754 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4755 4756 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4757 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4758 4759 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 4760 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_SHFT 0x6 4761 4762 #define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4763 #define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4764 4765 #define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4766 #define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4767 4768 #define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4769 #define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4770 4771 #define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4772 #define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_SHFT 0x2 4773 4774 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4775 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4776 4777 #define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4778 #define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4779 4780 //// Register REO_R0_REO2SW4_RING_HP_ADDR_LSB //// 4781 4782 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x) (x+0x000003b8) 4783 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_PHYS(x) (x+0x000003b8) 4784 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK 0xffffffff 4785 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_SHFT 0 4786 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x) \ 4787 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK) 4788 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_INM(x, mask) \ 4789 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask) 4790 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUT(x, val) \ 4791 out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), val) 4792 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4793 do {\ 4794 HWIO_INTLOCK(); \ 4795 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x)); \ 4796 HWIO_INTFREE();\ 4797 } while (0) 4798 4799 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4800 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4801 4802 //// Register REO_R0_REO2SW4_RING_HP_ADDR_MSB //// 4803 4804 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x) (x+0x000003bc) 4805 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_PHYS(x) (x+0x000003bc) 4806 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK 0x000000ff 4807 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_SHFT 0 4808 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x) \ 4809 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK) 4810 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_INM(x, mask) \ 4811 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask) 4812 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUT(x, val) \ 4813 out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), val) 4814 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4815 do {\ 4816 HWIO_INTLOCK(); \ 4817 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x)); \ 4818 HWIO_INTFREE();\ 4819 } while (0) 4820 4821 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4822 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4823 4824 //// Register REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP //// 4825 4826 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000003c8) 4827 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000003c8) 4828 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4829 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SHFT 0 4830 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x) \ 4831 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK) 4832 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4833 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4834 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4835 out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4836 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4837 do {\ 4838 HWIO_INTLOCK(); \ 4839 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x)); \ 4840 HWIO_INTFREE();\ 4841 } while (0) 4842 4843 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4844 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4845 4846 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4847 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4848 4849 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4850 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4851 4852 //// Register REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS //// 4853 4854 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000003cc) 4855 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000003cc) 4856 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4857 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_SHFT 0 4858 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x) \ 4859 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK) 4860 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4861 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4862 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4863 out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4864 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4865 do {\ 4866 HWIO_INTLOCK(); \ 4867 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x)); \ 4868 HWIO_INTFREE();\ 4869 } while (0) 4870 4871 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4872 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4873 4874 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4875 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4876 4877 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4878 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4879 4880 //// Register REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER //// 4881 4882 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000003d0) 4883 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000003d0) 4884 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4885 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_SHFT 0 4886 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4887 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK) 4888 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4889 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4890 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4891 out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4892 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4893 do {\ 4894 HWIO_INTLOCK(); \ 4895 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4896 HWIO_INTFREE();\ 4897 } while (0) 4898 4899 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4900 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4901 4902 //// Register REO_R0_REO2SW4_RING_MSI1_BASE_LSB //// 4903 4904 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000003ec) 4905 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000003ec) 4906 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4907 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_SHFT 0 4908 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x) \ 4909 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK) 4910 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_INM(x, mask) \ 4911 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask) 4912 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUT(x, val) \ 4913 out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), val) 4914 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4915 do {\ 4916 HWIO_INTLOCK(); \ 4917 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x)); \ 4918 HWIO_INTFREE();\ 4919 } while (0) 4920 4921 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4922 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4923 4924 //// Register REO_R0_REO2SW4_RING_MSI1_BASE_MSB //// 4925 4926 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000003f0) 4927 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000003f0) 4928 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4929 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_SHFT 0 4930 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x) \ 4931 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK) 4932 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_INM(x, mask) \ 4933 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask) 4934 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUT(x, val) \ 4935 out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), val) 4936 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4937 do {\ 4938 HWIO_INTLOCK(); \ 4939 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x)); \ 4940 HWIO_INTFREE();\ 4941 } while (0) 4942 4943 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4944 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4945 4946 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4947 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4948 4949 //// Register REO_R0_REO2SW4_RING_MSI1_DATA //// 4950 4951 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x) (x+0x000003f4) 4952 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_PHYS(x) (x+0x000003f4) 4953 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK 0xffffffff 4954 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_SHFT 0 4955 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x) \ 4956 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK) 4957 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_INM(x, mask) \ 4958 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask) 4959 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUT(x, val) \ 4960 out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), val) 4961 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUTM(x, mask, val) \ 4962 do {\ 4963 HWIO_INTLOCK(); \ 4964 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x)); \ 4965 HWIO_INTFREE();\ 4966 } while (0) 4967 4968 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4969 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_SHFT 0x0 4970 4971 //// Register REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET //// 4972 4973 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003f8) 4974 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003f8) 4975 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4976 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_SHFT 0 4977 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x) \ 4978 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK) 4979 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4980 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4981 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4982 out_dword( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4983 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4984 do {\ 4985 HWIO_INTLOCK(); \ 4986 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x)); \ 4987 HWIO_INTFREE();\ 4988 } while (0) 4989 4990 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4991 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4992 4993 //// Register REO_R0_REO2TCL_RING_BASE_LSB //// 4994 4995 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x) (x+0x000003fc) 4996 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_PHYS(x) (x+0x000003fc) 4997 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK 0xffffffff 4998 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_SHFT 0 4999 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x) \ 5000 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK) 5001 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_INM(x, mask) \ 5002 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask) 5003 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUT(x, val) \ 5004 out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), val) 5005 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUTM(x, mask, val) \ 5006 do {\ 5007 HWIO_INTLOCK(); \ 5008 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x)); \ 5009 HWIO_INTFREE();\ 5010 } while (0) 5011 5012 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 5013 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 5014 5015 //// Register REO_R0_REO2TCL_RING_BASE_MSB //// 5016 5017 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x) (x+0x00000400) 5018 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_PHYS(x) (x+0x00000400) 5019 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK 0x0fffffff 5020 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_SHFT 0 5021 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x) \ 5022 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK) 5023 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_INM(x, mask) \ 5024 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask) 5025 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUT(x, val) \ 5026 out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), val) 5027 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUTM(x, mask, val) \ 5028 do {\ 5029 HWIO_INTLOCK(); \ 5030 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x)); \ 5031 HWIO_INTFREE();\ 5032 } while (0) 5033 5034 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 5035 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT 0x8 5036 5037 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 5038 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 5039 5040 //// Register REO_R0_REO2TCL_RING_ID //// 5041 5042 #define HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x) (x+0x00000404) 5043 #define HWIO_REO_R0_REO2TCL_RING_ID_PHYS(x) (x+0x00000404) 5044 #define HWIO_REO_R0_REO2TCL_RING_ID_RMSK 0x0000ffff 5045 #define HWIO_REO_R0_REO2TCL_RING_ID_SHFT 0 5046 #define HWIO_REO_R0_REO2TCL_RING_ID_IN(x) \ 5047 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), HWIO_REO_R0_REO2TCL_RING_ID_RMSK) 5048 #define HWIO_REO_R0_REO2TCL_RING_ID_INM(x, mask) \ 5049 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask) 5050 #define HWIO_REO_R0_REO2TCL_RING_ID_OUT(x, val) \ 5051 out_dword( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), val) 5052 #define HWIO_REO_R0_REO2TCL_RING_ID_OUTM(x, mask, val) \ 5053 do {\ 5054 HWIO_INTLOCK(); \ 5055 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_ID_IN(x)); \ 5056 HWIO_INTFREE();\ 5057 } while (0) 5058 5059 #define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_BMSK 0x0000ff00 5060 #define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_SHFT 0x8 5061 5062 #define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 5063 #define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_SHFT 0x0 5064 5065 //// Register REO_R0_REO2TCL_RING_STATUS //// 5066 5067 #define HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x) (x+0x00000408) 5068 #define HWIO_REO_R0_REO2TCL_RING_STATUS_PHYS(x) (x+0x00000408) 5069 #define HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK 0xffffffff 5070 #define HWIO_REO_R0_REO2TCL_RING_STATUS_SHFT 0 5071 #define HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x) \ 5072 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK) 5073 #define HWIO_REO_R0_REO2TCL_RING_STATUS_INM(x, mask) \ 5074 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask) 5075 #define HWIO_REO_R0_REO2TCL_RING_STATUS_OUT(x, val) \ 5076 out_dword( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), val) 5077 #define HWIO_REO_R0_REO2TCL_RING_STATUS_OUTM(x, mask, val) \ 5078 do {\ 5079 HWIO_INTLOCK(); \ 5080 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x)); \ 5081 HWIO_INTFREE();\ 5082 } while (0) 5083 5084 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 5085 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 5086 5087 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 5088 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 5089 5090 //// Register REO_R0_REO2TCL_RING_MISC //// 5091 5092 #define HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x) (x+0x0000040c) 5093 #define HWIO_REO_R0_REO2TCL_RING_MISC_PHYS(x) (x+0x0000040c) 5094 #define HWIO_REO_R0_REO2TCL_RING_MISC_RMSK 0x03ffffff 5095 #define HWIO_REO_R0_REO2TCL_RING_MISC_SHFT 0 5096 #define HWIO_REO_R0_REO2TCL_RING_MISC_IN(x) \ 5097 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MISC_RMSK) 5098 #define HWIO_REO_R0_REO2TCL_RING_MISC_INM(x, mask) \ 5099 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask) 5100 #define HWIO_REO_R0_REO2TCL_RING_MISC_OUT(x, val) \ 5101 out_dword( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), val) 5102 #define HWIO_REO_R0_REO2TCL_RING_MISC_OUTM(x, mask, val) \ 5103 do {\ 5104 HWIO_INTLOCK(); \ 5105 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MISC_IN(x)); \ 5106 HWIO_INTFREE();\ 5107 } while (0) 5108 5109 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOP_CNT_BMSK 0x03c00000 5110 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOP_CNT_SHFT 0x16 5111 5112 #define HWIO_REO_R0_REO2TCL_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 5113 #define HWIO_REO_R0_REO2TCL_RING_MISC_SPARE_CONTROL_SHFT 0xe 5114 5115 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 5116 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 5117 5118 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 5119 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 5120 5121 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 5122 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 5123 5124 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 5125 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_ENABLE_SHFT 0x6 5126 5127 #define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 5128 #define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 5129 5130 #define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 5131 #define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 5132 5133 #define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 5134 #define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 5135 5136 #define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_BMSK 0x00000004 5137 #define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_SHFT 0x2 5138 5139 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 5140 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 5141 5142 #define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 5143 #define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_SHFT 0x0 5144 5145 //// Register REO_R0_REO2TCL_RING_HP_ADDR_LSB //// 5146 5147 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000410) 5148 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000410) 5149 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK 0xffffffff 5150 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_SHFT 0 5151 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x) \ 5152 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK) 5153 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_INM(x, mask) \ 5154 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask) 5155 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUT(x, val) \ 5156 out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), val) 5157 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 5158 do {\ 5159 HWIO_INTLOCK(); \ 5160 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x)); \ 5161 HWIO_INTFREE();\ 5162 } while (0) 5163 5164 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 5165 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 5166 5167 //// Register REO_R0_REO2TCL_RING_HP_ADDR_MSB //// 5168 5169 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000414) 5170 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000414) 5171 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK 0x000000ff 5172 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_SHFT 0 5173 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x) \ 5174 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK) 5175 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_INM(x, mask) \ 5176 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask) 5177 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUT(x, val) \ 5178 out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), val) 5179 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 5180 do {\ 5181 HWIO_INTLOCK(); \ 5182 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x)); \ 5183 HWIO_INTFREE();\ 5184 } while (0) 5185 5186 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 5187 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 5188 5189 //// Register REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP //// 5190 5191 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000420) 5192 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000420) 5193 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 5194 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SHFT 0 5195 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x) \ 5196 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK) 5197 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 5198 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 5199 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 5200 out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), val) 5201 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 5202 do {\ 5203 HWIO_INTLOCK(); \ 5204 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x)); \ 5205 HWIO_INTFREE();\ 5206 } while (0) 5207 5208 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 5209 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 5210 5211 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 5212 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 5213 5214 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 5215 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 5216 5217 //// Register REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS //// 5218 5219 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000424) 5220 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000424) 5221 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 5222 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_SHFT 0 5223 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x) \ 5224 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK) 5225 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 5226 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 5227 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 5228 out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), val) 5229 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 5230 do {\ 5231 HWIO_INTLOCK(); \ 5232 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x)); \ 5233 HWIO_INTFREE();\ 5234 } while (0) 5235 5236 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 5237 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 5238 5239 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 5240 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 5241 5242 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 5243 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 5244 5245 //// Register REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER //// 5246 5247 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000428) 5248 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000428) 5249 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 5250 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_SHFT 0 5251 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x) \ 5252 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK) 5253 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 5254 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 5255 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 5256 out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 5257 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 5258 do {\ 5259 HWIO_INTLOCK(); \ 5260 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 5261 HWIO_INTFREE();\ 5262 } while (0) 5263 5264 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 5265 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 5266 5267 //// Register REO_R0_REO2TCL_RING_MSI1_BASE_LSB //// 5268 5269 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000444) 5270 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000444) 5271 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK 0xffffffff 5272 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_SHFT 0 5273 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x) \ 5274 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK) 5275 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_INM(x, mask) \ 5276 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask) 5277 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUT(x, val) \ 5278 out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), val) 5279 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 5280 do {\ 5281 HWIO_INTLOCK(); \ 5282 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x)); \ 5283 HWIO_INTFREE();\ 5284 } while (0) 5285 5286 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 5287 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 5288 5289 //// Register REO_R0_REO2TCL_RING_MSI1_BASE_MSB //// 5290 5291 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000448) 5292 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000448) 5293 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK 0x000001ff 5294 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_SHFT 0 5295 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x) \ 5296 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK) 5297 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_INM(x, mask) \ 5298 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask) 5299 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUT(x, val) \ 5300 out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), val) 5301 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 5302 do {\ 5303 HWIO_INTLOCK(); \ 5304 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x)); \ 5305 HWIO_INTFREE();\ 5306 } while (0) 5307 5308 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 5309 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 5310 5311 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 5312 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 5313 5314 //// Register REO_R0_REO2TCL_RING_MSI1_DATA //// 5315 5316 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x) (x+0x0000044c) 5317 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_PHYS(x) (x+0x0000044c) 5318 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK 0xffffffff 5319 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_SHFT 0 5320 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x) \ 5321 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK) 5322 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_INM(x, mask) \ 5323 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask) 5324 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUT(x, val) \ 5325 out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), val) 5326 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUTM(x, mask, val) \ 5327 do {\ 5328 HWIO_INTLOCK(); \ 5329 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x)); \ 5330 HWIO_INTFREE();\ 5331 } while (0) 5332 5333 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 5334 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_SHFT 0x0 5335 5336 //// Register REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET //// 5337 5338 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000450) 5339 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000450) 5340 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 5341 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_SHFT 0 5342 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x) \ 5343 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK) 5344 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 5345 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 5346 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 5347 out_dword( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), val) 5348 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 5349 do {\ 5350 HWIO_INTLOCK(); \ 5351 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x)); \ 5352 HWIO_INTFREE();\ 5353 } while (0) 5354 5355 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 5356 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 5357 5358 //// Register REO_R0_REO2FW_RING_BASE_LSB //// 5359 5360 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x) (x+0x00000454) 5361 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_PHYS(x) (x+0x00000454) 5362 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK 0xffffffff 5363 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_SHFT 0 5364 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x) \ 5365 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK) 5366 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_INM(x, mask) \ 5367 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask) 5368 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUT(x, val) \ 5369 out_dword( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), val) 5370 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUTM(x, mask, val) \ 5371 do {\ 5372 HWIO_INTLOCK(); \ 5373 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x)); \ 5374 HWIO_INTFREE();\ 5375 } while (0) 5376 5377 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 5378 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 5379 5380 //// Register REO_R0_REO2FW_RING_BASE_MSB //// 5381 5382 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x) (x+0x00000458) 5383 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_PHYS(x) (x+0x00000458) 5384 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK 0x0fffffff 5385 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_SHFT 0 5386 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x) \ 5387 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK) 5388 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_INM(x, mask) \ 5389 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask) 5390 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUT(x, val) \ 5391 out_dword( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), val) 5392 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUTM(x, mask, val) \ 5393 do {\ 5394 HWIO_INTLOCK(); \ 5395 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x)); \ 5396 HWIO_INTFREE();\ 5397 } while (0) 5398 5399 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 5400 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8 5401 5402 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 5403 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 5404 5405 //// Register REO_R0_REO2FW_RING_ID //// 5406 5407 #define HWIO_REO_R0_REO2FW_RING_ID_ADDR(x) (x+0x0000045c) 5408 #define HWIO_REO_R0_REO2FW_RING_ID_PHYS(x) (x+0x0000045c) 5409 #define HWIO_REO_R0_REO2FW_RING_ID_RMSK 0x0000ffff 5410 #define HWIO_REO_R0_REO2FW_RING_ID_SHFT 0 5411 #define HWIO_REO_R0_REO2FW_RING_ID_IN(x) \ 5412 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), HWIO_REO_R0_REO2FW_RING_ID_RMSK) 5413 #define HWIO_REO_R0_REO2FW_RING_ID_INM(x, mask) \ 5414 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask) 5415 #define HWIO_REO_R0_REO2FW_RING_ID_OUT(x, val) \ 5416 out_dword( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), val) 5417 #define HWIO_REO_R0_REO2FW_RING_ID_OUTM(x, mask, val) \ 5418 do {\ 5419 HWIO_INTLOCK(); \ 5420 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_ID_IN(x)); \ 5421 HWIO_INTFREE();\ 5422 } while (0) 5423 5424 #define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_BMSK 0x0000ff00 5425 #define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_SHFT 0x8 5426 5427 #define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 5428 #define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_SHFT 0x0 5429 5430 //// Register REO_R0_REO2FW_RING_STATUS //// 5431 5432 #define HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x) (x+0x00000460) 5433 #define HWIO_REO_R0_REO2FW_RING_STATUS_PHYS(x) (x+0x00000460) 5434 #define HWIO_REO_R0_REO2FW_RING_STATUS_RMSK 0xffffffff 5435 #define HWIO_REO_R0_REO2FW_RING_STATUS_SHFT 0 5436 #define HWIO_REO_R0_REO2FW_RING_STATUS_IN(x) \ 5437 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_STATUS_RMSK) 5438 #define HWIO_REO_R0_REO2FW_RING_STATUS_INM(x, mask) \ 5439 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask) 5440 #define HWIO_REO_R0_REO2FW_RING_STATUS_OUT(x, val) \ 5441 out_dword( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), val) 5442 #define HWIO_REO_R0_REO2FW_RING_STATUS_OUTM(x, mask, val) \ 5443 do {\ 5444 HWIO_INTLOCK(); \ 5445 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_STATUS_IN(x)); \ 5446 HWIO_INTFREE();\ 5447 } while (0) 5448 5449 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 5450 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 5451 5452 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 5453 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 5454 5455 //// Register REO_R0_REO2FW_RING_MISC //// 5456 5457 #define HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x) (x+0x00000464) 5458 #define HWIO_REO_R0_REO2FW_RING_MISC_PHYS(x) (x+0x00000464) 5459 #define HWIO_REO_R0_REO2FW_RING_MISC_RMSK 0x03ffffff 5460 #define HWIO_REO_R0_REO2FW_RING_MISC_SHFT 0 5461 #define HWIO_REO_R0_REO2FW_RING_MISC_IN(x) \ 5462 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), HWIO_REO_R0_REO2FW_RING_MISC_RMSK) 5463 #define HWIO_REO_R0_REO2FW_RING_MISC_INM(x, mask) \ 5464 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask) 5465 #define HWIO_REO_R0_REO2FW_RING_MISC_OUT(x, val) \ 5466 out_dword( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), val) 5467 #define HWIO_REO_R0_REO2FW_RING_MISC_OUTM(x, mask, val) \ 5468 do {\ 5469 HWIO_INTLOCK(); \ 5470 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MISC_IN(x)); \ 5471 HWIO_INTFREE();\ 5472 } while (0) 5473 5474 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOP_CNT_BMSK 0x03c00000 5475 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOP_CNT_SHFT 0x16 5476 5477 #define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 5478 #define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL_SHFT 0xe 5479 5480 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 5481 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 5482 5483 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 5484 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 5485 5486 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 5487 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 5488 5489 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 5490 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_ENABLE_SHFT 0x6 5491 5492 #define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 5493 #define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 5494 5495 #define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 5496 #define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 5497 5498 #define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 5499 #define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 5500 5501 #define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_BMSK 0x00000004 5502 #define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_SHFT 0x2 5503 5504 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 5505 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 5506 5507 #define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 5508 #define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_SHFT 0x0 5509 5510 //// Register REO_R0_REO2FW_RING_HP_ADDR_LSB //// 5511 5512 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000468) 5513 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000468) 5514 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff 5515 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_SHFT 0 5516 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x) \ 5517 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK) 5518 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_INM(x, mask) \ 5519 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask) 5520 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUT(x, val) \ 5521 out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), val) 5522 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 5523 do {\ 5524 HWIO_INTLOCK(); \ 5525 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x)); \ 5526 HWIO_INTFREE();\ 5527 } while (0) 5528 5529 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 5530 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 5531 5532 //// Register REO_R0_REO2FW_RING_HP_ADDR_MSB //// 5533 5534 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000046c) 5535 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000046c) 5536 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff 5537 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_SHFT 0 5538 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x) \ 5539 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK) 5540 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_INM(x, mask) \ 5541 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask) 5542 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUT(x, val) \ 5543 out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), val) 5544 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 5545 do {\ 5546 HWIO_INTLOCK(); \ 5547 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x)); \ 5548 HWIO_INTFREE();\ 5549 } while (0) 5550 5551 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 5552 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 5553 5554 //// Register REO_R0_REO2FW_RING_PRODUCER_INT_SETUP //// 5555 5556 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000478) 5557 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000478) 5558 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 5559 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SHFT 0 5560 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x) \ 5561 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK) 5562 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 5563 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 5564 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 5565 out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val) 5566 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 5567 do {\ 5568 HWIO_INTLOCK(); \ 5569 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x)); \ 5570 HWIO_INTFREE();\ 5571 } while (0) 5572 5573 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 5574 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 5575 5576 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 5577 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 5578 5579 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 5580 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 5581 5582 //// Register REO_R0_REO2FW_RING_PRODUCER_INT_STATUS //// 5583 5584 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000047c) 5585 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000047c) 5586 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 5587 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_SHFT 0 5588 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x) \ 5589 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK) 5590 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 5591 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 5592 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 5593 out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val) 5594 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 5595 do {\ 5596 HWIO_INTLOCK(); \ 5597 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x)); \ 5598 HWIO_INTFREE();\ 5599 } while (0) 5600 5601 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 5602 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 5603 5604 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 5605 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 5606 5607 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 5608 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 5609 5610 //// Register REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER //// 5611 5612 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000480) 5613 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000480) 5614 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 5615 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 5616 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ 5617 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK) 5618 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 5619 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 5620 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 5621 out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 5622 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 5623 do {\ 5624 HWIO_INTLOCK(); \ 5625 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 5626 HWIO_INTFREE();\ 5627 } while (0) 5628 5629 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 5630 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 5631 5632 //// Register REO_R0_REO2FW_RING_MSI1_BASE_LSB //// 5633 5634 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000049c) 5635 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000049c) 5636 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK 0xffffffff 5637 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_SHFT 0 5638 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x) \ 5639 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK) 5640 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_INM(x, mask) \ 5641 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask) 5642 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUT(x, val) \ 5643 out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), val) 5644 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 5645 do {\ 5646 HWIO_INTLOCK(); \ 5647 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x)); \ 5648 HWIO_INTFREE();\ 5649 } while (0) 5650 5651 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 5652 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 5653 5654 //// Register REO_R0_REO2FW_RING_MSI1_BASE_MSB //// 5655 5656 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000004a0) 5657 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000004a0) 5658 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK 0x000001ff 5659 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_SHFT 0 5660 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x) \ 5661 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK) 5662 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_INM(x, mask) \ 5663 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask) 5664 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUT(x, val) \ 5665 out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), val) 5666 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 5667 do {\ 5668 HWIO_INTLOCK(); \ 5669 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x)); \ 5670 HWIO_INTFREE();\ 5671 } while (0) 5672 5673 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 5674 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 5675 5676 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 5677 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 5678 5679 //// Register REO_R0_REO2FW_RING_MSI1_DATA //// 5680 5681 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x) (x+0x000004a4) 5682 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_PHYS(x) (x+0x000004a4) 5683 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK 0xffffffff 5684 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_SHFT 0 5685 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x) \ 5686 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK) 5687 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_INM(x, mask) \ 5688 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask) 5689 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUT(x, val) \ 5690 out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), val) 5691 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUTM(x, mask, val) \ 5692 do {\ 5693 HWIO_INTLOCK(); \ 5694 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x)); \ 5695 HWIO_INTFREE();\ 5696 } while (0) 5697 5698 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 5699 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_SHFT 0x0 5700 5701 //// Register REO_R0_REO2FW_RING_HP_TP_SW_OFFSET //// 5702 5703 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000004a8) 5704 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000004a8) 5705 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 5706 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_SHFT 0 5707 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x) \ 5708 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK) 5709 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 5710 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 5711 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 5712 out_dword( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val) 5713 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 5714 do {\ 5715 HWIO_INTLOCK(); \ 5716 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x)); \ 5717 HWIO_INTFREE();\ 5718 } while (0) 5719 5720 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 5721 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 5722 5723 //// Register REO_R0_REO_RELEASE_RING_BASE_LSB //// 5724 5725 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000004ac) 5726 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000004ac) 5727 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK 0xffffffff 5728 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_SHFT 0 5729 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x) \ 5730 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK) 5731 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_INM(x, mask) \ 5732 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask) 5733 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, val) \ 5734 out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), val) 5735 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ 5736 do {\ 5737 HWIO_INTLOCK(); \ 5738 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x)); \ 5739 HWIO_INTFREE();\ 5740 } while (0) 5741 5742 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 5743 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 5744 5745 //// Register REO_R0_REO_RELEASE_RING_BASE_MSB //// 5746 5747 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000004b0) 5748 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000004b0) 5749 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff 5750 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_SHFT 0 5751 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x) \ 5752 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK) 5753 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_INM(x, mask) \ 5754 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask) 5755 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, val) \ 5756 out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), val) 5757 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ 5758 do {\ 5759 HWIO_INTLOCK(); \ 5760 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x)); \ 5761 HWIO_INTFREE();\ 5762 } while (0) 5763 5764 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 5765 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 5766 5767 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 5768 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 5769 5770 //// Register REO_R0_REO_RELEASE_RING_ID //// 5771 5772 #define HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x) (x+0x000004b4) 5773 #define HWIO_REO_R0_REO_RELEASE_RING_ID_PHYS(x) (x+0x000004b4) 5774 #define HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK 0x0000ffff 5775 #define HWIO_REO_R0_REO_RELEASE_RING_ID_SHFT 0 5776 #define HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x) \ 5777 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK) 5778 #define HWIO_REO_R0_REO_RELEASE_RING_ID_INM(x, mask) \ 5779 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask) 5780 #define HWIO_REO_R0_REO_RELEASE_RING_ID_OUT(x, val) \ 5781 out_dword( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), val) 5782 #define HWIO_REO_R0_REO_RELEASE_RING_ID_OUTM(x, mask, val) \ 5783 do {\ 5784 HWIO_INTLOCK(); \ 5785 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x)); \ 5786 HWIO_INTFREE();\ 5787 } while (0) 5788 5789 #define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 5790 #define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_SHFT 0x8 5791 5792 #define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 5793 #define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 5794 5795 //// Register REO_R0_REO_RELEASE_RING_STATUS //// 5796 5797 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x) (x+0x000004b8) 5798 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_PHYS(x) (x+0x000004b8) 5799 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK 0xffffffff 5800 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_SHFT 0 5801 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x) \ 5802 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK) 5803 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_INM(x, mask) \ 5804 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask) 5805 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUT(x, val) \ 5806 out_dword( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), val) 5807 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUTM(x, mask, val) \ 5808 do {\ 5809 HWIO_INTLOCK(); \ 5810 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x)); \ 5811 HWIO_INTFREE();\ 5812 } while (0) 5813 5814 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 5815 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 5816 5817 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 5818 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 5819 5820 //// Register REO_R0_REO_RELEASE_RING_MISC //// 5821 5822 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x) (x+0x000004bc) 5823 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_PHYS(x) (x+0x000004bc) 5824 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK 0x03ffffff 5825 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SHFT 0 5826 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x) \ 5827 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK) 5828 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_INM(x, mask) \ 5829 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask) 5830 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUT(x, val) \ 5831 out_dword( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), val) 5832 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUTM(x, mask, val) \ 5833 do {\ 5834 HWIO_INTLOCK(); \ 5835 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x)); \ 5836 HWIO_INTFREE();\ 5837 } while (0) 5838 5839 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x03c00000 5840 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOP_CNT_SHFT 0x16 5841 5842 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 5843 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe 5844 5845 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 5846 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 5847 5848 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 5849 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 5850 5851 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 5852 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 5853 5854 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 5855 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6 5856 5857 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 5858 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 5859 5860 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 5861 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 5862 5863 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 5864 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 5865 5866 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 5867 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 5868 5869 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 5870 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 5871 5872 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 5873 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 5874 5875 //// Register REO_R0_REO_RELEASE_RING_HP_ADDR_LSB //// 5876 5877 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x000004c0) 5878 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x000004c0) 5879 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff 5880 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_SHFT 0 5881 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x) \ 5882 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK) 5883 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ 5884 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) 5885 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ 5886 out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) 5887 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 5888 do {\ 5889 HWIO_INTLOCK(); \ 5890 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ 5891 HWIO_INTFREE();\ 5892 } while (0) 5893 5894 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 5895 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 5896 5897 //// Register REO_R0_REO_RELEASE_RING_HP_ADDR_MSB //// 5898 5899 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x000004c4) 5900 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x000004c4) 5901 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff 5902 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_SHFT 0 5903 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x) \ 5904 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK) 5905 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ 5906 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) 5907 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ 5908 out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) 5909 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 5910 do {\ 5911 HWIO_INTLOCK(); \ 5912 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ 5913 HWIO_INTFREE();\ 5914 } while (0) 5915 5916 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 5917 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 5918 5919 //// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP //// 5920 5921 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000004d0) 5922 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000004d0) 5923 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 5924 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 5925 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ 5926 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) 5927 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 5928 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 5929 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 5930 out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) 5931 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 5932 do {\ 5933 HWIO_INTLOCK(); \ 5934 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ 5935 HWIO_INTFREE();\ 5936 } while (0) 5937 5938 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 5939 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 5940 5941 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 5942 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 5943 5944 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 5945 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 5946 5947 //// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS //// 5948 5949 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000004d4) 5950 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000004d4) 5951 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 5952 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 5953 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ 5954 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) 5955 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 5956 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 5957 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 5958 out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) 5959 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 5960 do {\ 5961 HWIO_INTLOCK(); \ 5962 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ 5963 HWIO_INTFREE();\ 5964 } while (0) 5965 5966 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 5967 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 5968 5969 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 5970 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 5971 5972 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 5973 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 5974 5975 //// Register REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER //// 5976 5977 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000004d8) 5978 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000004d8) 5979 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 5980 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 5981 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ 5982 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) 5983 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 5984 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 5985 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 5986 out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 5987 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 5988 do {\ 5989 HWIO_INTLOCK(); \ 5990 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 5991 HWIO_INTFREE();\ 5992 } while (0) 5993 5994 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 5995 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 5996 5997 //// Register REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET //// 5998 5999 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000500) 6000 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000500) 6001 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 6002 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 6003 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ 6004 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) 6005 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 6006 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 6007 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 6008 out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) 6009 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 6010 do {\ 6011 HWIO_INTLOCK(); \ 6012 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ 6013 HWIO_INTFREE();\ 6014 } while (0) 6015 6016 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 6017 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 6018 6019 //// Register REO_R0_REO_STATUS_RING_BASE_LSB //// 6020 6021 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x) (x+0x00000504) 6022 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_PHYS(x) (x+0x00000504) 6023 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK 0xffffffff 6024 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_SHFT 0 6025 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x) \ 6026 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK) 6027 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_INM(x, mask) \ 6028 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask) 6029 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUT(x, val) \ 6030 out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), val) 6031 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUTM(x, mask, val) \ 6032 do {\ 6033 HWIO_INTLOCK(); \ 6034 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x)); \ 6035 HWIO_INTFREE();\ 6036 } while (0) 6037 6038 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 6039 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 6040 6041 //// Register REO_R0_REO_STATUS_RING_BASE_MSB //// 6042 6043 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x) (x+0x00000508) 6044 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_PHYS(x) (x+0x00000508) 6045 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK 0x00ffffff 6046 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_SHFT 0 6047 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x) \ 6048 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK) 6049 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_INM(x, mask) \ 6050 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask) 6051 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUT(x, val) \ 6052 out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), val) 6053 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUTM(x, mask, val) \ 6054 do {\ 6055 HWIO_INTLOCK(); \ 6056 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x)); \ 6057 HWIO_INTFREE();\ 6058 } while (0) 6059 6060 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 6061 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 6062 6063 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 6064 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 6065 6066 //// Register REO_R0_REO_STATUS_RING_ID //// 6067 6068 #define HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x) (x+0x0000050c) 6069 #define HWIO_REO_R0_REO_STATUS_RING_ID_PHYS(x) (x+0x0000050c) 6070 #define HWIO_REO_R0_REO_STATUS_RING_ID_RMSK 0x0000ffff 6071 #define HWIO_REO_R0_REO_STATUS_RING_ID_SHFT 0 6072 #define HWIO_REO_R0_REO_STATUS_RING_ID_IN(x) \ 6073 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_ID_RMSK) 6074 #define HWIO_REO_R0_REO_STATUS_RING_ID_INM(x, mask) \ 6075 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask) 6076 #define HWIO_REO_R0_REO_STATUS_RING_ID_OUT(x, val) \ 6077 out_dword( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), val) 6078 #define HWIO_REO_R0_REO_STATUS_RING_ID_OUTM(x, mask, val) \ 6079 do {\ 6080 HWIO_INTLOCK(); \ 6081 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_ID_IN(x)); \ 6082 HWIO_INTFREE();\ 6083 } while (0) 6084 6085 #define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_BMSK 0x0000ff00 6086 #define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_SHFT 0x8 6087 6088 #define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 6089 #define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 6090 6091 //// Register REO_R0_REO_STATUS_RING_STATUS //// 6092 6093 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x) (x+0x00000510) 6094 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_PHYS(x) (x+0x00000510) 6095 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK 0xffffffff 6096 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_SHFT 0 6097 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x) \ 6098 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK) 6099 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_INM(x, mask) \ 6100 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask) 6101 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUT(x, val) \ 6102 out_dword( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), val) 6103 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUTM(x, mask, val) \ 6104 do {\ 6105 HWIO_INTLOCK(); \ 6106 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x)); \ 6107 HWIO_INTFREE();\ 6108 } while (0) 6109 6110 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 6111 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 6112 6113 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 6114 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 6115 6116 //// Register REO_R0_REO_STATUS_RING_MISC //// 6117 6118 #define HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x) (x+0x00000514) 6119 #define HWIO_REO_R0_REO_STATUS_RING_MISC_PHYS(x) (x+0x00000514) 6120 #define HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK 0x03ffffff 6121 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SHFT 0 6122 #define HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x) \ 6123 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK) 6124 #define HWIO_REO_R0_REO_STATUS_RING_MISC_INM(x, mask) \ 6125 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask) 6126 #define HWIO_REO_R0_REO_STATUS_RING_MISC_OUT(x, val) \ 6127 out_dword( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), val) 6128 #define HWIO_REO_R0_REO_STATUS_RING_MISC_OUTM(x, mask, val) \ 6129 do {\ 6130 HWIO_INTLOCK(); \ 6131 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x)); \ 6132 HWIO_INTFREE();\ 6133 } while (0) 6134 6135 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_BMSK 0x03c00000 6136 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 6137 6138 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 6139 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe 6140 6141 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 6142 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 6143 6144 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 6145 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 6146 6147 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 6148 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 6149 6150 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 6151 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 6152 6153 #define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 6154 #define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 6155 6156 #define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 6157 #define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 6158 6159 #define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 6160 #define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 6161 6162 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x00000004 6163 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 6164 6165 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 6166 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 6167 6168 #define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 6169 #define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 6170 6171 //// Register REO_R0_REO_STATUS_RING_HP_ADDR_LSB //// 6172 6173 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000518) 6174 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000518) 6175 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff 6176 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_SHFT 0 6177 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x) \ 6178 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK) 6179 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_INM(x, mask) \ 6180 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) 6181 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUT(x, val) \ 6182 out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), val) 6183 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 6184 do {\ 6185 HWIO_INTLOCK(); \ 6186 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x)); \ 6187 HWIO_INTFREE();\ 6188 } while (0) 6189 6190 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 6191 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 6192 6193 //// Register REO_R0_REO_STATUS_RING_HP_ADDR_MSB //// 6194 6195 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000051c) 6196 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000051c) 6197 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK 0x000000ff 6198 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_SHFT 0 6199 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x) \ 6200 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK) 6201 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_INM(x, mask) \ 6202 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) 6203 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUT(x, val) \ 6204 out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), val) 6205 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 6206 do {\ 6207 HWIO_INTLOCK(); \ 6208 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x)); \ 6209 HWIO_INTFREE();\ 6210 } while (0) 6211 6212 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 6213 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 6214 6215 //// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP //// 6216 6217 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000528) 6218 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000528) 6219 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 6220 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SHFT 0 6221 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ 6222 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK) 6223 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 6224 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 6225 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 6226 out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), val) 6227 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 6228 do {\ 6229 HWIO_INTLOCK(); \ 6230 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x)); \ 6231 HWIO_INTFREE();\ 6232 } while (0) 6233 6234 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 6235 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 6236 6237 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 6238 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 6239 6240 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 6241 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 6242 6243 //// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS //// 6244 6245 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000052c) 6246 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000052c) 6247 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 6248 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_SHFT 0 6249 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ 6250 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK) 6251 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 6252 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 6253 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 6254 out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), val) 6255 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 6256 do {\ 6257 HWIO_INTLOCK(); \ 6258 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x)); \ 6259 HWIO_INTFREE();\ 6260 } while (0) 6261 6262 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 6263 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 6264 6265 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 6266 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 6267 6268 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 6269 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 6270 6271 //// Register REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER //// 6272 6273 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000530) 6274 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000530) 6275 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 6276 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT 0 6277 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ 6278 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) 6279 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 6280 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 6281 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 6282 out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 6283 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 6284 do {\ 6285 HWIO_INTLOCK(); \ 6286 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 6287 HWIO_INTFREE();\ 6288 } while (0) 6289 6290 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 6291 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 6292 6293 //// Register REO_R0_REO_STATUS_RING_MSI1_BASE_LSB //// 6294 6295 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000054c) 6296 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000054c) 6297 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff 6298 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_SHFT 0 6299 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x) \ 6300 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK) 6301 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_INM(x, mask) \ 6302 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) 6303 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUT(x, val) \ 6304 out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), val) 6305 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 6306 do {\ 6307 HWIO_INTLOCK(); \ 6308 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x)); \ 6309 HWIO_INTFREE();\ 6310 } while (0) 6311 6312 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 6313 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 6314 6315 //// Register REO_R0_REO_STATUS_RING_MSI1_BASE_MSB //// 6316 6317 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000550) 6318 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000550) 6319 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK 0x000001ff 6320 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_SHFT 0 6321 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x) \ 6322 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK) 6323 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_INM(x, mask) \ 6324 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) 6325 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUT(x, val) \ 6326 out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), val) 6327 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 6328 do {\ 6329 HWIO_INTLOCK(); \ 6330 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x)); \ 6331 HWIO_INTFREE();\ 6332 } while (0) 6333 6334 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 6335 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 6336 6337 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 6338 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 6339 6340 //// Register REO_R0_REO_STATUS_RING_MSI1_DATA //// 6341 6342 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x) (x+0x00000554) 6343 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_PHYS(x) (x+0x00000554) 6344 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK 0xffffffff 6345 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_SHFT 0 6346 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x) \ 6347 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK) 6348 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_INM(x, mask) \ 6349 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask) 6350 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUT(x, val) \ 6351 out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), val) 6352 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUTM(x, mask, val) \ 6353 do {\ 6354 HWIO_INTLOCK(); \ 6355 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x)); \ 6356 HWIO_INTFREE();\ 6357 } while (0) 6358 6359 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 6360 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 6361 6362 //// Register REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET //// 6363 6364 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000558) 6365 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000558) 6366 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 6367 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_SHFT 0 6368 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ 6369 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK) 6370 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 6371 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 6372 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 6373 out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), val) 6374 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 6375 do {\ 6376 HWIO_INTLOCK(); \ 6377 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x)); \ 6378 HWIO_INTFREE();\ 6379 } while (0) 6380 6381 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 6382 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 6383 6384 //// Register REO_R0_WATCHDOG_TIMEOUT //// 6385 6386 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x) (x+0x0000055c) 6387 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_PHYS(x) (x+0x0000055c) 6388 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK 0x00000fff 6389 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SHFT 0 6390 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x) \ 6391 in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK) 6392 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_INM(x, mask) \ 6393 in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask) 6394 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUT(x, val) \ 6395 out_dword( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), val) 6396 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUTM(x, mask, val) \ 6397 do {\ 6398 HWIO_INTLOCK(); \ 6399 out_dword_masked_ns(HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask, val, HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x)); \ 6400 HWIO_INTFREE();\ 6401 } while (0) 6402 6403 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_BMSK 0x00000fff 6404 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_SHFT 0x0 6405 6406 //// Register REO_R0_INTERRUPT_DATA_CAPTURE_IX_0 //// 6407 6408 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x) (x+0x00000560) 6409 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_PHYS(x) (x+0x00000560) 6410 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK 0xffffffff 6411 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_SHFT 0 6412 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x) \ 6413 in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK) 6414 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_INM(x, mask) \ 6415 in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask) 6416 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUT(x, val) \ 6417 out_dword( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), val) 6418 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUTM(x, mask, val) \ 6419 do {\ 6420 HWIO_INTLOCK(); \ 6421 out_dword_masked_ns(HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x)); \ 6422 HWIO_INTFREE();\ 6423 } while (0) 6424 6425 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_BMSK 0xffffffff 6426 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_SHFT 0x0 6427 6428 //// Register REO_R0_AGING_THRESHOLD_IX_0 //// 6429 6430 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) (x+0x00000564) 6431 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_PHYS(x) (x+0x00000564) 6432 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK 0xffffffff 6433 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_SHFT 0 6434 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x) \ 6435 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK) 6436 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_INM(x, mask) \ 6437 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask) 6438 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUT(x, val) \ 6439 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), val) 6440 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUTM(x, mask, val) \ 6441 do {\ 6442 HWIO_INTLOCK(); \ 6443 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x)); \ 6444 HWIO_INTFREE();\ 6445 } while (0) 6446 6447 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_BMSK 0xffffffff 6448 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_SHFT 0x0 6449 6450 //// Register REO_R0_AGING_THRESHOLD_IX_1 //// 6451 6452 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) (x+0x00000568) 6453 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_PHYS(x) (x+0x00000568) 6454 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK 0xffffffff 6455 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_SHFT 0 6456 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x) \ 6457 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK) 6458 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_INM(x, mask) \ 6459 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask) 6460 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUT(x, val) \ 6461 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), val) 6462 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUTM(x, mask, val) \ 6463 do {\ 6464 HWIO_INTLOCK(); \ 6465 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x)); \ 6466 HWIO_INTFREE();\ 6467 } while (0) 6468 6469 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_BMSK 0xffffffff 6470 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_SHFT 0x0 6471 6472 //// Register REO_R0_AGING_THRESHOLD_IX_2 //// 6473 6474 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) (x+0x0000056c) 6475 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_PHYS(x) (x+0x0000056c) 6476 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK 0xffffffff 6477 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_SHFT 0 6478 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x) \ 6479 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK) 6480 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_INM(x, mask) \ 6481 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask) 6482 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUT(x, val) \ 6483 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), val) 6484 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUTM(x, mask, val) \ 6485 do {\ 6486 HWIO_INTLOCK(); \ 6487 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x)); \ 6488 HWIO_INTFREE();\ 6489 } while (0) 6490 6491 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_BMSK 0xffffffff 6492 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_SHFT 0x0 6493 6494 //// Register REO_R0_AGING_THRESHOLD_IX_3 //// 6495 6496 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) (x+0x00000570) 6497 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_PHYS(x) (x+0x00000570) 6498 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK 0xffffffff 6499 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_SHFT 0 6500 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x) \ 6501 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK) 6502 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_INM(x, mask) \ 6503 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask) 6504 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUT(x, val) \ 6505 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), val) 6506 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUTM(x, mask, val) \ 6507 do {\ 6508 HWIO_INTLOCK(); \ 6509 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x)); \ 6510 HWIO_INTFREE();\ 6511 } while (0) 6512 6513 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_BMSK 0xffffffff 6514 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_SHFT 0x0 6515 6516 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_0 //// 6517 6518 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x) (x+0x00000574) 6519 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_PHYS(x) (x+0x00000574) 6520 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK 0xffffffff 6521 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_SHFT 0 6522 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x) \ 6523 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK) 6524 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_INM(x, mask) \ 6525 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask) 6526 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUT(x, val) \ 6527 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), val) 6528 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUTM(x, mask, val) \ 6529 do {\ 6530 HWIO_INTLOCK(); \ 6531 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x)); \ 6532 HWIO_INTFREE();\ 6533 } while (0) 6534 6535 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 6536 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_SHFT 0x0 6537 6538 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_0 //// 6539 6540 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x) (x+0x00000578) 6541 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_PHYS(x) (x+0x00000578) 6542 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK 0x000000ff 6543 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_SHFT 0 6544 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x) \ 6545 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK) 6546 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_INM(x, mask) \ 6547 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask) 6548 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUT(x, val) \ 6549 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), val) 6550 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUTM(x, mask, val) \ 6551 do {\ 6552 HWIO_INTLOCK(); \ 6553 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x)); \ 6554 HWIO_INTFREE();\ 6555 } while (0) 6556 6557 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 6558 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_SHFT 0x0 6559 6560 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_0 //// 6561 6562 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x) (x+0x0000057c) 6563 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_PHYS(x) (x+0x0000057c) 6564 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK 0xffffffff 6565 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_SHFT 0 6566 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x) \ 6567 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK) 6568 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_INM(x, mask) \ 6569 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask) 6570 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUT(x, val) \ 6571 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), val) 6572 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUTM(x, mask, val) \ 6573 do {\ 6574 HWIO_INTLOCK(); \ 6575 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x)); \ 6576 HWIO_INTFREE();\ 6577 } while (0) 6578 6579 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 6580 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_SHFT 0x0 6581 6582 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_0 //// 6583 6584 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x) (x+0x00000580) 6585 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_PHYS(x) (x+0x00000580) 6586 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK 0x000000ff 6587 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_SHFT 0 6588 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x) \ 6589 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK) 6590 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_INM(x, mask) \ 6591 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask) 6592 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUT(x, val) \ 6593 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), val) 6594 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUTM(x, mask, val) \ 6595 do {\ 6596 HWIO_INTLOCK(); \ 6597 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x)); \ 6598 HWIO_INTFREE();\ 6599 } while (0) 6600 6601 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 6602 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_SHFT 0x0 6603 6604 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_1 //// 6605 6606 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x) (x+0x00000584) 6607 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_PHYS(x) (x+0x00000584) 6608 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK 0xffffffff 6609 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_SHFT 0 6610 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x) \ 6611 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK) 6612 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_INM(x, mask) \ 6613 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask) 6614 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUT(x, val) \ 6615 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), val) 6616 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUTM(x, mask, val) \ 6617 do {\ 6618 HWIO_INTLOCK(); \ 6619 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x)); \ 6620 HWIO_INTFREE();\ 6621 } while (0) 6622 6623 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 6624 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_SHFT 0x0 6625 6626 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_1 //// 6627 6628 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x) (x+0x00000588) 6629 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_PHYS(x) (x+0x00000588) 6630 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK 0x000000ff 6631 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_SHFT 0 6632 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x) \ 6633 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK) 6634 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_INM(x, mask) \ 6635 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask) 6636 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUT(x, val) \ 6637 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), val) 6638 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUTM(x, mask, val) \ 6639 do {\ 6640 HWIO_INTLOCK(); \ 6641 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x)); \ 6642 HWIO_INTFREE();\ 6643 } while (0) 6644 6645 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 6646 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_SHFT 0x0 6647 6648 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_1 //// 6649 6650 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x) (x+0x0000058c) 6651 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_PHYS(x) (x+0x0000058c) 6652 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK 0xffffffff 6653 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_SHFT 0 6654 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x) \ 6655 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK) 6656 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_INM(x, mask) \ 6657 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask) 6658 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUT(x, val) \ 6659 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), val) 6660 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUTM(x, mask, val) \ 6661 do {\ 6662 HWIO_INTLOCK(); \ 6663 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x)); \ 6664 HWIO_INTFREE();\ 6665 } while (0) 6666 6667 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 6668 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_SHFT 0x0 6669 6670 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_1 //// 6671 6672 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x) (x+0x00000590) 6673 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_PHYS(x) (x+0x00000590) 6674 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK 0x000000ff 6675 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_SHFT 0 6676 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x) \ 6677 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK) 6678 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_INM(x, mask) \ 6679 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask) 6680 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUT(x, val) \ 6681 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), val) 6682 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUTM(x, mask, val) \ 6683 do {\ 6684 HWIO_INTLOCK(); \ 6685 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x)); \ 6686 HWIO_INTFREE();\ 6687 } while (0) 6688 6689 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 6690 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_SHFT 0x0 6691 6692 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_2 //// 6693 6694 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x) (x+0x00000594) 6695 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_PHYS(x) (x+0x00000594) 6696 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK 0xffffffff 6697 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_SHFT 0 6698 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x) \ 6699 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK) 6700 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_INM(x, mask) \ 6701 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask) 6702 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUT(x, val) \ 6703 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), val) 6704 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUTM(x, mask, val) \ 6705 do {\ 6706 HWIO_INTLOCK(); \ 6707 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x)); \ 6708 HWIO_INTFREE();\ 6709 } while (0) 6710 6711 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 6712 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_SHFT 0x0 6713 6714 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_2 //// 6715 6716 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x) (x+0x00000598) 6717 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_PHYS(x) (x+0x00000598) 6718 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK 0x000000ff 6719 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_SHFT 0 6720 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x) \ 6721 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK) 6722 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_INM(x, mask) \ 6723 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask) 6724 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUT(x, val) \ 6725 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), val) 6726 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUTM(x, mask, val) \ 6727 do {\ 6728 HWIO_INTLOCK(); \ 6729 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x)); \ 6730 HWIO_INTFREE();\ 6731 } while (0) 6732 6733 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 6734 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_SHFT 0x0 6735 6736 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_2 //// 6737 6738 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x) (x+0x0000059c) 6739 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_PHYS(x) (x+0x0000059c) 6740 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK 0xffffffff 6741 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_SHFT 0 6742 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x) \ 6743 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK) 6744 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_INM(x, mask) \ 6745 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask) 6746 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUT(x, val) \ 6747 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), val) 6748 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUTM(x, mask, val) \ 6749 do {\ 6750 HWIO_INTLOCK(); \ 6751 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x)); \ 6752 HWIO_INTFREE();\ 6753 } while (0) 6754 6755 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 6756 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_SHFT 0x0 6757 6758 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_2 //// 6759 6760 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x) (x+0x000005a0) 6761 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_PHYS(x) (x+0x000005a0) 6762 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK 0x000000ff 6763 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_SHFT 0 6764 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x) \ 6765 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK) 6766 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_INM(x, mask) \ 6767 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask) 6768 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUT(x, val) \ 6769 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), val) 6770 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUTM(x, mask, val) \ 6771 do {\ 6772 HWIO_INTLOCK(); \ 6773 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x)); \ 6774 HWIO_INTFREE();\ 6775 } while (0) 6776 6777 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 6778 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_SHFT 0x0 6779 6780 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_3 //// 6781 6782 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x) (x+0x000005a4) 6783 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_PHYS(x) (x+0x000005a4) 6784 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK 0xffffffff 6785 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_SHFT 0 6786 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x) \ 6787 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK) 6788 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_INM(x, mask) \ 6789 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask) 6790 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUT(x, val) \ 6791 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), val) 6792 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUTM(x, mask, val) \ 6793 do {\ 6794 HWIO_INTLOCK(); \ 6795 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x)); \ 6796 HWIO_INTFREE();\ 6797 } while (0) 6798 6799 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 6800 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_SHFT 0x0 6801 6802 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_3 //// 6803 6804 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x) (x+0x000005a8) 6805 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_PHYS(x) (x+0x000005a8) 6806 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK 0x000000ff 6807 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_SHFT 0 6808 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x) \ 6809 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK) 6810 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_INM(x, mask) \ 6811 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask) 6812 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUT(x, val) \ 6813 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), val) 6814 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUTM(x, mask, val) \ 6815 do {\ 6816 HWIO_INTLOCK(); \ 6817 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x)); \ 6818 HWIO_INTFREE();\ 6819 } while (0) 6820 6821 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 6822 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_SHFT 0x0 6823 6824 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_3 //// 6825 6826 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x) (x+0x000005ac) 6827 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_PHYS(x) (x+0x000005ac) 6828 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK 0xffffffff 6829 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_SHFT 0 6830 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x) \ 6831 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK) 6832 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_INM(x, mask) \ 6833 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask) 6834 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUT(x, val) \ 6835 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), val) 6836 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUTM(x, mask, val) \ 6837 do {\ 6838 HWIO_INTLOCK(); \ 6839 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x)); \ 6840 HWIO_INTFREE();\ 6841 } while (0) 6842 6843 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 6844 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_SHFT 0x0 6845 6846 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_3 //// 6847 6848 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x) (x+0x000005b0) 6849 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_PHYS(x) (x+0x000005b0) 6850 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK 0x000000ff 6851 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_SHFT 0 6852 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x) \ 6853 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK) 6854 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_INM(x, mask) \ 6855 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask) 6856 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUT(x, val) \ 6857 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), val) 6858 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUTM(x, mask, val) \ 6859 do {\ 6860 HWIO_INTLOCK(); \ 6861 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x)); \ 6862 HWIO_INTFREE();\ 6863 } while (0) 6864 6865 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 6866 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_SHFT 0x0 6867 6868 //// Register REO_R0_AGING_NUM_QUEUES_IX_0 //// 6869 6870 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x) (x+0x000005b4) 6871 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_PHYS(x) (x+0x000005b4) 6872 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK 0x0000ffff 6873 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_SHFT 0 6874 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x) \ 6875 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK) 6876 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_INM(x, mask) \ 6877 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask) 6878 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUT(x, val) \ 6879 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), val) 6880 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUTM(x, mask, val) \ 6881 do {\ 6882 HWIO_INTLOCK(); \ 6883 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x)); \ 6884 HWIO_INTFREE();\ 6885 } while (0) 6886 6887 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_BMSK 0x0000ffff 6888 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_SHFT 0x0 6889 6890 //// Register REO_R0_AGING_NUM_QUEUES_IX_1 //// 6891 6892 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x) (x+0x000005b8) 6893 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_PHYS(x) (x+0x000005b8) 6894 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK 0x0000ffff 6895 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_SHFT 0 6896 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x) \ 6897 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK) 6898 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_INM(x, mask) \ 6899 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask) 6900 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUT(x, val) \ 6901 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), val) 6902 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUTM(x, mask, val) \ 6903 do {\ 6904 HWIO_INTLOCK(); \ 6905 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x)); \ 6906 HWIO_INTFREE();\ 6907 } while (0) 6908 6909 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_BMSK 0x0000ffff 6910 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_SHFT 0x0 6911 6912 //// Register REO_R0_AGING_NUM_QUEUES_IX_2 //// 6913 6914 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x) (x+0x000005bc) 6915 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_PHYS(x) (x+0x000005bc) 6916 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK 0x0000ffff 6917 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_SHFT 0 6918 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x) \ 6919 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK) 6920 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_INM(x, mask) \ 6921 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask) 6922 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUT(x, val) \ 6923 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), val) 6924 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUTM(x, mask, val) \ 6925 do {\ 6926 HWIO_INTLOCK(); \ 6927 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x)); \ 6928 HWIO_INTFREE();\ 6929 } while (0) 6930 6931 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_BMSK 0x0000ffff 6932 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_SHFT 0x0 6933 6934 //// Register REO_R0_AGING_NUM_QUEUES_IX_3 //// 6935 6936 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x) (x+0x000005c0) 6937 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_PHYS(x) (x+0x000005c0) 6938 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK 0x0000ffff 6939 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_SHFT 0 6940 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x) \ 6941 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK) 6942 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_INM(x, mask) \ 6943 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask) 6944 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUT(x, val) \ 6945 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), val) 6946 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUTM(x, mask, val) \ 6947 do {\ 6948 HWIO_INTLOCK(); \ 6949 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x)); \ 6950 HWIO_INTFREE();\ 6951 } while (0) 6952 6953 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_BMSK 0x0000ffff 6954 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_SHFT 0x0 6955 6956 //// Register REO_R0_AGING_TIMESTAMP_IX_0 //// 6957 6958 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x) (x+0x000005c4) 6959 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_PHYS(x) (x+0x000005c4) 6960 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK 0xffffffff 6961 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_SHFT 0 6962 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x) \ 6963 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK) 6964 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_INM(x, mask) \ 6965 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask) 6966 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUT(x, val) \ 6967 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), val) 6968 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUTM(x, mask, val) \ 6969 do {\ 6970 HWIO_INTLOCK(); \ 6971 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x)); \ 6972 HWIO_INTFREE();\ 6973 } while (0) 6974 6975 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_BMSK 0xffffffff 6976 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_SHFT 0x0 6977 6978 //// Register REO_R0_AGING_TIMESTAMP_IX_1 //// 6979 6980 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x) (x+0x000005c8) 6981 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_PHYS(x) (x+0x000005c8) 6982 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK 0xffffffff 6983 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_SHFT 0 6984 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x) \ 6985 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK) 6986 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_INM(x, mask) \ 6987 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask) 6988 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUT(x, val) \ 6989 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), val) 6990 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUTM(x, mask, val) \ 6991 do {\ 6992 HWIO_INTLOCK(); \ 6993 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x)); \ 6994 HWIO_INTFREE();\ 6995 } while (0) 6996 6997 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_BMSK 0xffffffff 6998 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_SHFT 0x0 6999 7000 //// Register REO_R0_AGING_TIMESTAMP_IX_2 //// 7001 7002 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x) (x+0x000005cc) 7003 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_PHYS(x) (x+0x000005cc) 7004 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK 0xffffffff 7005 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_SHFT 0 7006 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x) \ 7007 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK) 7008 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_INM(x, mask) \ 7009 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask) 7010 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUT(x, val) \ 7011 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), val) 7012 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUTM(x, mask, val) \ 7013 do {\ 7014 HWIO_INTLOCK(); \ 7015 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x)); \ 7016 HWIO_INTFREE();\ 7017 } while (0) 7018 7019 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_BMSK 0xffffffff 7020 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_SHFT 0x0 7021 7022 //// Register REO_R0_AGING_TIMESTAMP_IX_3 //// 7023 7024 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x) (x+0x000005d0) 7025 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_PHYS(x) (x+0x000005d0) 7026 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK 0xffffffff 7027 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_SHFT 0 7028 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x) \ 7029 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK) 7030 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_INM(x, mask) \ 7031 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask) 7032 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUT(x, val) \ 7033 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), val) 7034 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUTM(x, mask, val) \ 7035 do {\ 7036 HWIO_INTLOCK(); \ 7037 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x)); \ 7038 HWIO_INTFREE();\ 7039 } while (0) 7040 7041 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_BMSK 0xffffffff 7042 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_SHFT 0x0 7043 7044 //// Register REO_R0_AGING_CONTROL //// 7045 7046 #define HWIO_REO_R0_AGING_CONTROL_ADDR(x) (x+0x000005d4) 7047 #define HWIO_REO_R0_AGING_CONTROL_PHYS(x) (x+0x000005d4) 7048 #define HWIO_REO_R0_AGING_CONTROL_RMSK 0x0000001f 7049 #define HWIO_REO_R0_AGING_CONTROL_SHFT 0 7050 #define HWIO_REO_R0_AGING_CONTROL_IN(x) \ 7051 in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), HWIO_REO_R0_AGING_CONTROL_RMSK) 7052 #define HWIO_REO_R0_AGING_CONTROL_INM(x, mask) \ 7053 in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask) 7054 #define HWIO_REO_R0_AGING_CONTROL_OUT(x, val) \ 7055 out_dword( HWIO_REO_R0_AGING_CONTROL_ADDR(x), val) 7056 #define HWIO_REO_R0_AGING_CONTROL_OUTM(x, mask, val) \ 7057 do {\ 7058 HWIO_INTLOCK(); \ 7059 out_dword_masked_ns(HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_AGING_CONTROL_IN(x)); \ 7060 HWIO_INTFREE();\ 7061 } while (0) 7062 7063 #define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_BMSK 0x0000001f 7064 #define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_SHFT 0x0 7065 7066 //// Register REO_R0_MISC_CTL //// 7067 7068 #define HWIO_REO_R0_MISC_CTL_ADDR(x) (x+0x000005d8) 7069 #define HWIO_REO_R0_MISC_CTL_PHYS(x) (x+0x000005d8) 7070 #define HWIO_REO_R0_MISC_CTL_RMSK 0x0001ffff 7071 #define HWIO_REO_R0_MISC_CTL_SHFT 0 7072 #define HWIO_REO_R0_MISC_CTL_IN(x) \ 7073 in_dword_masked ( HWIO_REO_R0_MISC_CTL_ADDR(x), HWIO_REO_R0_MISC_CTL_RMSK) 7074 #define HWIO_REO_R0_MISC_CTL_INM(x, mask) \ 7075 in_dword_masked ( HWIO_REO_R0_MISC_CTL_ADDR(x), mask) 7076 #define HWIO_REO_R0_MISC_CTL_OUT(x, val) \ 7077 out_dword( HWIO_REO_R0_MISC_CTL_ADDR(x), val) 7078 #define HWIO_REO_R0_MISC_CTL_OUTM(x, mask, val) \ 7079 do {\ 7080 HWIO_INTLOCK(); \ 7081 out_dword_masked_ns(HWIO_REO_R0_MISC_CTL_ADDR(x), mask, val, HWIO_REO_R0_MISC_CTL_IN(x)); \ 7082 HWIO_INTFREE();\ 7083 } while (0) 7084 7085 #define HWIO_REO_R0_MISC_CTL_CACHE_FLUSH_Q_DESC_ONLY_BMSK 0x00010000 7086 #define HWIO_REO_R0_MISC_CTL_CACHE_FLUSH_Q_DESC_ONLY_SHFT 0x10 7087 7088 #define HWIO_REO_R0_MISC_CTL_SPARE_CONTROL_BMSK 0x0000ffff 7089 #define HWIO_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT 0x0 7090 7091 //// Register REO_R0_HIGH_MEMORY_THRESHOLD //// 7092 7093 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x) (x+0x000005dc) 7094 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_PHYS(x) (x+0x000005dc) 7095 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK 0xffffffff 7096 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_SHFT 0 7097 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x) \ 7098 in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK) 7099 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_INM(x, mask) \ 7100 in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask) 7101 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUT(x, val) \ 7102 out_dword( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), val) 7103 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUTM(x, mask, val) \ 7104 do {\ 7105 HWIO_INTLOCK(); \ 7106 out_dword_masked_ns(HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask, val, HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x)); \ 7107 HWIO_INTFREE();\ 7108 } while (0) 7109 7110 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_BMSK 0xffffffff 7111 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_SHFT 0x0 7112 7113 //// Register REO_R0_AC_BUFFERS_USED_IX_0 //// 7114 7115 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x) (x+0x000005e0) 7116 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_PHYS(x) (x+0x000005e0) 7117 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK 0xffffffff 7118 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_SHFT 0 7119 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x) \ 7120 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK) 7121 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_INM(x, mask) \ 7122 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask) 7123 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUT(x, val) \ 7124 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), val) 7125 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUTM(x, mask, val) \ 7126 do {\ 7127 HWIO_INTLOCK(); \ 7128 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x)); \ 7129 HWIO_INTFREE();\ 7130 } while (0) 7131 7132 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_BMSK 0xffffffff 7133 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_SHFT 0x0 7134 7135 //// Register REO_R0_AC_BUFFERS_USED_IX_1 //// 7136 7137 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x) (x+0x000005e4) 7138 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_PHYS(x) (x+0x000005e4) 7139 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK 0xffffffff 7140 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_SHFT 0 7141 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x) \ 7142 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK) 7143 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_INM(x, mask) \ 7144 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask) 7145 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUT(x, val) \ 7146 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), val) 7147 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUTM(x, mask, val) \ 7148 do {\ 7149 HWIO_INTLOCK(); \ 7150 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x)); \ 7151 HWIO_INTFREE();\ 7152 } while (0) 7153 7154 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_BMSK 0xffffffff 7155 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_SHFT 0x0 7156 7157 //// Register REO_R0_AC_BUFFERS_USED_IX_2 //// 7158 7159 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x) (x+0x000005e8) 7160 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_PHYS(x) (x+0x000005e8) 7161 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK 0xffffffff 7162 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_SHFT 0 7163 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x) \ 7164 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK) 7165 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_INM(x, mask) \ 7166 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask) 7167 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUT(x, val) \ 7168 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), val) 7169 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUTM(x, mask, val) \ 7170 do {\ 7171 HWIO_INTLOCK(); \ 7172 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x)); \ 7173 HWIO_INTFREE();\ 7174 } while (0) 7175 7176 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_BMSK 0xffffffff 7177 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_SHFT 0x0 7178 7179 //// Register REO_R0_AC_BUFFERS_USED_IX_3 //// 7180 7181 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x) (x+0x000005ec) 7182 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_PHYS(x) (x+0x000005ec) 7183 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK 0xffffffff 7184 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_SHFT 0 7185 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x) \ 7186 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK) 7187 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_INM(x, mask) \ 7188 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask) 7189 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUT(x, val) \ 7190 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), val) 7191 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUTM(x, mask, val) \ 7192 do {\ 7193 HWIO_INTLOCK(); \ 7194 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x)); \ 7195 HWIO_INTFREE();\ 7196 } while (0) 7197 7198 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_BMSK 0xffffffff 7199 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_SHFT 0x0 7200 7201 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0 //// 7202 7203 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x) (x+0x000005f0) 7204 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_PHYS(x) (x+0x000005f0) 7205 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK 0x00ffffff 7206 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_SHFT 0 7207 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x) \ 7208 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK) 7209 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_INM(x, mask) \ 7210 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask) 7211 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUT(x, val) \ 7212 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), val) 7213 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUTM(x, mask, val) \ 7214 do {\ 7215 HWIO_INTLOCK(); \ 7216 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x)); \ 7217 HWIO_INTFREE();\ 7218 } while (0) 7219 7220 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_BMSK 0x00ffffff 7221 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_SHFT 0x0 7222 7223 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1 //// 7224 7225 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x) (x+0x000005f4) 7226 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_PHYS(x) (x+0x000005f4) 7227 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK 0x00ffffff 7228 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_SHFT 0 7229 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x) \ 7230 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK) 7231 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_INM(x, mask) \ 7232 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask) 7233 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUT(x, val) \ 7234 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), val) 7235 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUTM(x, mask, val) \ 7236 do {\ 7237 HWIO_INTLOCK(); \ 7238 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x)); \ 7239 HWIO_INTFREE();\ 7240 } while (0) 7241 7242 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_BMSK 0x00ffffff 7243 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_SHFT 0x0 7244 7245 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2 //// 7246 7247 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x) (x+0x000005f8) 7248 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_PHYS(x) (x+0x000005f8) 7249 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK 0x00ffffff 7250 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_SHFT 0 7251 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x) \ 7252 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK) 7253 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_INM(x, mask) \ 7254 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask) 7255 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUT(x, val) \ 7256 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), val) 7257 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUTM(x, mask, val) \ 7258 do {\ 7259 HWIO_INTLOCK(); \ 7260 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x)); \ 7261 HWIO_INTFREE();\ 7262 } while (0) 7263 7264 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_BMSK 0x00ffffff 7265 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_SHFT 0x0 7266 7267 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL //// 7268 7269 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x) (x+0x000005fc) 7270 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_PHYS(x) (x+0x000005fc) 7271 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK 0x03ffffff 7272 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_SHFT 0 7273 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x) \ 7274 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK) 7275 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_INM(x, mask) \ 7276 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask) 7277 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUT(x, val) \ 7278 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), val) 7279 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUTM(x, mask, val) \ 7280 do {\ 7281 HWIO_INTLOCK(); \ 7282 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x)); \ 7283 HWIO_INTFREE();\ 7284 } while (0) 7285 7286 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_BMSK 0x03ffffff 7287 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_SHFT 0x0 7288 7289 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0 //// 7290 7291 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x) (x+0x00000600) 7292 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_PHYS(x) (x+0x00000600) 7293 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK 0x00ffffff 7294 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_SHFT 0 7295 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x) \ 7296 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK) 7297 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_INM(x, mask) \ 7298 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask) 7299 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUT(x, val) \ 7300 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), val) 7301 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUTM(x, mask, val) \ 7302 do {\ 7303 HWIO_INTLOCK(); \ 7304 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x)); \ 7305 HWIO_INTFREE();\ 7306 } while (0) 7307 7308 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_BMSK 0x00ffffff 7309 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_SHFT 0x0 7310 7311 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1 //// 7312 7313 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x) (x+0x00000604) 7314 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_PHYS(x) (x+0x00000604) 7315 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK 0x00ffffff 7316 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_SHFT 0 7317 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x) \ 7318 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK) 7319 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_INM(x, mask) \ 7320 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask) 7321 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUT(x, val) \ 7322 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), val) 7323 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUTM(x, mask, val) \ 7324 do {\ 7325 HWIO_INTLOCK(); \ 7326 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x)); \ 7327 HWIO_INTFREE();\ 7328 } while (0) 7329 7330 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_BMSK 0x00ffffff 7331 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_SHFT 0x0 7332 7333 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2 //// 7334 7335 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x) (x+0x00000608) 7336 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_PHYS(x) (x+0x00000608) 7337 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK 0x00ffffff 7338 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_SHFT 0 7339 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x) \ 7340 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK) 7341 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_INM(x, mask) \ 7342 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask) 7343 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUT(x, val) \ 7344 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), val) 7345 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUTM(x, mask, val) \ 7346 do {\ 7347 HWIO_INTLOCK(); \ 7348 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x)); \ 7349 HWIO_INTFREE();\ 7350 } while (0) 7351 7352 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_BMSK 0x00ffffff 7353 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_SHFT 0x0 7354 7355 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL //// 7356 7357 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x) (x+0x0000060c) 7358 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_PHYS(x) (x+0x0000060c) 7359 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK 0x00000001 7360 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_SHFT 0 7361 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x) \ 7362 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK) 7363 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_INM(x, mask) \ 7364 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask) 7365 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUT(x, val) \ 7366 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), val) 7367 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUTM(x, mask, val) \ 7368 do {\ 7369 HWIO_INTLOCK(); \ 7370 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x)); \ 7371 HWIO_INTFREE();\ 7372 } while (0) 7373 7374 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_BMSK 0x00000001 7375 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_SHFT 0x0 7376 7377 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0 //// 7378 7379 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x) (x+0x00000610) 7380 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_PHYS(x) (x+0x00000610) 7381 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK 0xffffffff 7382 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_SHFT 0 7383 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x) \ 7384 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK) 7385 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_INM(x, mask) \ 7386 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask) 7387 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUT(x, val) \ 7388 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), val) 7389 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUTM(x, mask, val) \ 7390 do {\ 7391 HWIO_INTLOCK(); \ 7392 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x)); \ 7393 HWIO_INTFREE();\ 7394 } while (0) 7395 7396 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_BMSK 0xffffffff 7397 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_SHFT 0x0 7398 7399 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0 //// 7400 7401 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x) (x+0x00000614) 7402 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_PHYS(x) (x+0x00000614) 7403 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK 0x000000ff 7404 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_SHFT 0 7405 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x) \ 7406 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK) 7407 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_INM(x, mask) \ 7408 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask) 7409 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUT(x, val) \ 7410 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), val) 7411 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUTM(x, mask, val) \ 7412 do {\ 7413 HWIO_INTLOCK(); \ 7414 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x)); \ 7415 HWIO_INTFREE();\ 7416 } while (0) 7417 7418 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_BMSK 0x000000ff 7419 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_SHFT 0x0 7420 7421 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1 //// 7422 7423 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x) (x+0x00000618) 7424 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_PHYS(x) (x+0x00000618) 7425 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK 0xffffffff 7426 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_SHFT 0 7427 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x) \ 7428 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK) 7429 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_INM(x, mask) \ 7430 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask) 7431 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUT(x, val) \ 7432 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), val) 7433 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUTM(x, mask, val) \ 7434 do {\ 7435 HWIO_INTLOCK(); \ 7436 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x)); \ 7437 HWIO_INTFREE();\ 7438 } while (0) 7439 7440 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_BMSK 0xffffffff 7441 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_SHFT 0x0 7442 7443 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1 //// 7444 7445 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x) (x+0x0000061c) 7446 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_PHYS(x) (x+0x0000061c) 7447 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK 0x000000ff 7448 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_SHFT 0 7449 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x) \ 7450 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK) 7451 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_INM(x, mask) \ 7452 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask) 7453 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUT(x, val) \ 7454 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), val) 7455 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUTM(x, mask, val) \ 7456 do {\ 7457 HWIO_INTLOCK(); \ 7458 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x)); \ 7459 HWIO_INTFREE();\ 7460 } while (0) 7461 7462 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_BMSK 0x000000ff 7463 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_SHFT 0x0 7464 7465 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2 //// 7466 7467 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x) (x+0x00000620) 7468 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_PHYS(x) (x+0x00000620) 7469 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK 0xffffffff 7470 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_SHFT 0 7471 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x) \ 7472 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK) 7473 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_INM(x, mask) \ 7474 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask) 7475 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUT(x, val) \ 7476 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), val) 7477 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUTM(x, mask, val) \ 7478 do {\ 7479 HWIO_INTLOCK(); \ 7480 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x)); \ 7481 HWIO_INTFREE();\ 7482 } while (0) 7483 7484 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_BMSK 0xffffffff 7485 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_SHFT 0x0 7486 7487 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2 //// 7488 7489 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x) (x+0x00000624) 7490 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_PHYS(x) (x+0x00000624) 7491 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK 0x000000ff 7492 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_SHFT 0 7493 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x) \ 7494 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK) 7495 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_INM(x, mask) \ 7496 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask) 7497 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUT(x, val) \ 7498 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), val) 7499 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUTM(x, mask, val) \ 7500 do {\ 7501 HWIO_INTLOCK(); \ 7502 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x)); \ 7503 HWIO_INTFREE();\ 7504 } while (0) 7505 7506 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_BMSK 0x000000ff 7507 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_SHFT 0x0 7508 7509 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3 //// 7510 7511 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x) (x+0x00000628) 7512 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_PHYS(x) (x+0x00000628) 7513 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK 0xffffffff 7514 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_SHFT 0 7515 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x) \ 7516 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK) 7517 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_INM(x, mask) \ 7518 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask) 7519 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUT(x, val) \ 7520 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), val) 7521 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUTM(x, mask, val) \ 7522 do {\ 7523 HWIO_INTLOCK(); \ 7524 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x)); \ 7525 HWIO_INTFREE();\ 7526 } while (0) 7527 7528 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_BMSK 0xffffffff 7529 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_SHFT 0x0 7530 7531 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3 //// 7532 7533 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x) (x+0x0000062c) 7534 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_PHYS(x) (x+0x0000062c) 7535 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK 0x000000ff 7536 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_SHFT 0 7537 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x) \ 7538 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK) 7539 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_INM(x, mask) \ 7540 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask) 7541 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUT(x, val) \ 7542 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), val) 7543 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUTM(x, mask, val) \ 7544 do {\ 7545 HWIO_INTLOCK(); \ 7546 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x)); \ 7547 HWIO_INTFREE();\ 7548 } while (0) 7549 7550 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_BMSK 0x000000ff 7551 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_SHFT 0x0 7552 7553 //// Register REO_R0_QUEUE_DESC_BLOCK_INFO //// 7554 7555 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x) (x+0x00000630) 7556 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_PHYS(x) (x+0x00000630) 7557 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK 0x0000001f 7558 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_SHFT 0 7559 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x) \ 7560 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK) 7561 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_INM(x, mask) \ 7562 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask) 7563 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUT(x, val) \ 7564 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), val) 7565 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUTM(x, mask, val) \ 7566 do {\ 7567 HWIO_INTLOCK(); \ 7568 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x)); \ 7569 HWIO_INTFREE();\ 7570 } while (0) 7571 7572 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_BMSK 0x00000010 7573 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_SHFT 0x4 7574 7575 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_BMSK 0x0000000f 7576 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_SHFT 0x0 7577 7578 //// Register REO_R0_GXI_TESTBUS_LOWER //// 7579 7580 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x00000634) 7581 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x00000634) 7582 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff 7583 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_SHFT 0 7584 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x) \ 7585 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK) 7586 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ 7587 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) 7588 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ 7589 out_dword( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), val) 7590 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ 7591 do {\ 7592 HWIO_INTLOCK(); \ 7593 out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x)); \ 7594 HWIO_INTFREE();\ 7595 } while (0) 7596 7597 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 7598 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 7599 7600 //// Register REO_R0_GXI_TESTBUS_UPPER //// 7601 7602 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x00000638) 7603 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x00000638) 7604 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff 7605 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_SHFT 0 7606 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x) \ 7607 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK) 7608 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ 7609 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) 7610 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ 7611 out_dword( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), val) 7612 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ 7613 do {\ 7614 HWIO_INTLOCK(); \ 7615 out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x)); \ 7616 HWIO_INTFREE();\ 7617 } while (0) 7618 7619 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff 7620 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 7621 7622 //// Register REO_R0_GXI_SM_STATES_IX_0 //// 7623 7624 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x0000063c) 7625 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x0000063c) 7626 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff 7627 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SHFT 0 7628 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x) \ 7629 in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK) 7630 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ 7631 in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) 7632 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ 7633 out_dword( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), val) 7634 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ 7635 do {\ 7636 HWIO_INTLOCK(); \ 7637 out_dword_masked_ns(HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x)); \ 7638 HWIO_INTFREE();\ 7639 } while (0) 7640 7641 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 7642 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 7643 7644 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 7645 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 7646 7647 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f 7648 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 7649 7650 //// Register REO_R0_GXI_END_OF_TEST_CHECK //// 7651 7652 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x00000640) 7653 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x00000640) 7654 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 7655 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_SHFT 0 7656 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x) \ 7657 in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK) 7658 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ 7659 in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) 7660 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ 7661 out_dword( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) 7662 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 7663 do {\ 7664 HWIO_INTLOCK(); \ 7665 out_dword_masked_ns(HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ 7666 HWIO_INTFREE();\ 7667 } while (0) 7668 7669 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 7670 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 7671 7672 //// Register REO_R0_GXI_CLOCK_GATE_DISABLE //// 7673 7674 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x00000644) 7675 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x00000644) 7676 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff 7677 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 7678 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ 7679 in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK) 7680 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ 7681 in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) 7682 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ 7683 out_dword( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) 7684 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ 7685 do {\ 7686 HWIO_INTLOCK(); \ 7687 out_dword_masked_ns(HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ 7688 HWIO_INTFREE();\ 7689 } while (0) 7690 7691 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 7692 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f 7693 7694 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SPARE_BMSK 0x00000800 7695 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb 7696 7697 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x00000400 7698 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa 7699 7700 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x00000200 7701 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9 7702 7703 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x00000100 7704 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8 7705 7706 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x00000080 7707 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7 7708 7709 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x00000040 7710 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6 7711 7712 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x00000020 7713 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5 7714 7715 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x00000010 7716 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4 7717 7718 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x00000008 7719 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3 7720 7721 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x00000004 7722 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2 7723 7724 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x00000002 7725 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1 7726 7727 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CORE_BMSK 0x00000001 7728 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CORE_SHFT 0x0 7729 7730 //// Register REO_R0_GXI_GXI_ERR_INTS //// 7731 7732 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x00000648) 7733 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x00000648) 7734 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 7735 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_SHFT 0 7736 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x) \ 7737 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK) 7738 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ 7739 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) 7740 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ 7741 out_dword( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), val) 7742 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ 7743 do {\ 7744 HWIO_INTLOCK(); \ 7745 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x)); \ 7746 HWIO_INTFREE();\ 7747 } while (0) 7748 7749 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 7750 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 7751 7752 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 7753 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 7754 7755 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 7756 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 7757 7758 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 7759 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 7760 7761 //// Register REO_R0_GXI_GXI_ERR_STATS //// 7762 7763 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x0000064c) 7764 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x0000064c) 7765 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f 7766 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_SHFT 0 7767 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x) \ 7768 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK) 7769 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ 7770 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) 7771 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ 7772 out_dword( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), val) 7773 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ 7774 do {\ 7775 HWIO_INTLOCK(); \ 7776 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x)); \ 7777 HWIO_INTFREE();\ 7778 } while (0) 7779 7780 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 7781 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 7782 7783 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 7784 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 7785 7786 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f 7787 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 7788 7789 //// Register REO_R0_GXI_GXI_DEFAULT_CONTROL //// 7790 7791 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x00000650) 7792 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x00000650) 7793 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f 7794 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 7795 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ 7796 in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) 7797 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ 7798 in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) 7799 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ 7800 out_dword( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) 7801 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ 7802 do {\ 7803 HWIO_INTLOCK(); \ 7804 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ 7805 HWIO_INTFREE();\ 7806 } while (0) 7807 7808 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 7809 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 7810 7811 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 7812 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 7813 7814 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 7815 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 7816 7817 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f 7818 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 7819 7820 //// Register REO_R0_GXI_GXI_REDUCED_CONTROL //// 7821 7822 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x00000654) 7823 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x00000654) 7824 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f 7825 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 7826 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ 7827 in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK) 7828 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ 7829 in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) 7830 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ 7831 out_dword( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) 7832 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ 7833 do {\ 7834 HWIO_INTLOCK(); \ 7835 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ 7836 HWIO_INTFREE();\ 7837 } while (0) 7838 7839 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 7840 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 7841 7842 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 7843 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 7844 7845 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 7846 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 7847 7848 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f 7849 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 7850 7851 //// Register REO_R0_GXI_GXI_MISC_CONTROL //// 7852 7853 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x00000658) 7854 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x00000658) 7855 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK 0x0fffffff 7856 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_SHFT 0 7857 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x) \ 7858 in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK) 7859 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ 7860 in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) 7861 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ 7862 out_dword( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) 7863 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ 7864 do {\ 7865 HWIO_INTLOCK(); \ 7866 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ 7867 HWIO_INTFREE();\ 7868 } while (0) 7869 7870 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x08000000 7871 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 0x1b 7872 7873 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x04000000 7874 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 0x1a 7875 7876 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x02000000 7877 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 0x19 7878 7879 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x01000000 7880 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 0x18 7881 7882 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x00800000 7883 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 0x17 7884 7885 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 7886 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 7887 7888 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 7889 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 7890 7891 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 7892 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 7893 7894 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe 7895 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 7896 7897 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 7898 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 7899 7900 //// Register REO_R0_GXI_GXI_WDOG_CONTROL //// 7901 7902 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x0000065c) 7903 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x0000065c) 7904 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 7905 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 7906 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ 7907 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK) 7908 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ 7909 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) 7910 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ 7911 out_dword( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) 7912 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ 7913 do {\ 7914 HWIO_INTLOCK(); \ 7915 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ 7916 HWIO_INTFREE();\ 7917 } while (0) 7918 7919 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 7920 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 7921 7922 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 7923 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 7924 7925 //// Register REO_R0_GXI_GXI_WDOG_STATUS //// 7926 7927 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x00000660) 7928 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x00000660) 7929 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff 7930 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_SHFT 0 7931 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x) \ 7932 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK) 7933 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ 7934 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) 7935 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ 7936 out_dword( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) 7937 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ 7938 do {\ 7939 HWIO_INTLOCK(); \ 7940 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ 7941 HWIO_INTFREE();\ 7942 } while (0) 7943 7944 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff 7945 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 7946 7947 //// Register REO_R0_GXI_GXI_IDLE_COUNTERS //// 7948 7949 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x00000664) 7950 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x00000664) 7951 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff 7952 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 7953 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ 7954 in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK) 7955 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ 7956 in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) 7957 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ 7958 out_dword( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) 7959 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ 7960 do {\ 7961 HWIO_INTLOCK(); \ 7962 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ 7963 HWIO_INTFREE();\ 7964 } while (0) 7965 7966 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 7967 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 7968 7969 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff 7970 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 7971 7972 //// Register REO_R0_GXI_GXI_RD_LATENCY_CTRL //// 7973 7974 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x) (x+0x00000668) 7975 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_PHYS(x) (x+0x00000668) 7976 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK 0x000fffff 7977 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_SHFT 0 7978 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x) \ 7979 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK) 7980 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_INM(x, mask) \ 7981 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask) 7982 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_OUT(x, val) \ 7983 out_dword( HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), val) 7984 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_OUTM(x, mask, val) \ 7985 do {\ 7986 HWIO_INTLOCK(); \ 7987 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x)); \ 7988 HWIO_INTFREE();\ 7989 } while (0) 7990 7991 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 7992 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 7993 7994 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 7995 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 7996 7997 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff 7998 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 7999 8000 //// Register REO_R0_GXI_GXI_WR_LATENCY_CTRL //// 8001 8002 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x) (x+0x0000066c) 8003 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_PHYS(x) (x+0x0000066c) 8004 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK 0x000fffff 8005 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_SHFT 0 8006 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x) \ 8007 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK) 8008 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_INM(x, mask) \ 8009 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask) 8010 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_OUT(x, val) \ 8011 out_dword( HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), val) 8012 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_OUTM(x, mask, val) \ 8013 do {\ 8014 HWIO_INTLOCK(); \ 8015 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x)); \ 8016 HWIO_INTFREE();\ 8017 } while (0) 8018 8019 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 8020 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 8021 8022 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 8023 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 8024 8025 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff 8026 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 8027 8028 //// Register REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 //// 8029 8030 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x00000670) 8031 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x00000670) 8032 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff 8033 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_SHFT 0 8034 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x) \ 8035 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK) 8036 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ 8037 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) 8038 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(x, val) \ 8039 out_dword( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), val) 8040 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ 8041 do {\ 8042 HWIO_INTLOCK(); \ 8043 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x)); \ 8044 HWIO_INTFREE();\ 8045 } while (0) 8046 8047 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff 8048 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 8049 8050 //// Register REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 //// 8051 8052 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x00000674) 8053 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x00000674) 8054 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff 8055 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_SHFT 0 8056 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x) \ 8057 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK) 8058 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ 8059 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) 8060 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(x, val) \ 8061 out_dword( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), val) 8062 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ 8063 do {\ 8064 HWIO_INTLOCK(); \ 8065 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x)); \ 8066 HWIO_INTFREE();\ 8067 } while (0) 8068 8069 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff 8070 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 8071 8072 //// Register REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 //// 8073 8074 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x00000678) 8075 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x00000678) 8076 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff 8077 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_SHFT 0 8078 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x) \ 8079 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK) 8080 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ 8081 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) 8082 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(x, val) \ 8083 out_dword( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), val) 8084 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ 8085 do {\ 8086 HWIO_INTLOCK(); \ 8087 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x)); \ 8088 HWIO_INTFREE();\ 8089 } while (0) 8090 8091 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff 8092 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 8093 8094 //// Register REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 //// 8095 8096 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x0000067c) 8097 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x0000067c) 8098 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff 8099 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_SHFT 0 8100 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x) \ 8101 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK) 8102 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ 8103 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) 8104 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(x, val) \ 8105 out_dword( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), val) 8106 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ 8107 do {\ 8108 HWIO_INTLOCK(); \ 8109 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x)); \ 8110 HWIO_INTFREE();\ 8111 } while (0) 8112 8113 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff 8114 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 8115 8116 //// Register REO_R0_GXI_GXI_AXI_OUTSANDING_CTL //// 8117 8118 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x) (x+0x00000680) 8119 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x) (x+0x00000680) 8120 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK 0x00009f9f 8121 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_SHFT 0 8122 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x) \ 8123 in_dword_masked ( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK) 8124 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_INM(x, mask) \ 8125 in_dword_masked ( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask) 8126 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUT(x, val) \ 8127 out_dword( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), val) 8128 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUTM(x, mask, val) \ 8129 do {\ 8130 HWIO_INTLOCK(); \ 8131 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x)); \ 8132 HWIO_INTFREE();\ 8133 } while (0) 8134 8135 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_BMSK 0x00008000 8136 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_SHFT 0xf 8137 8138 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_BMSK 0x00001f00 8139 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_SHFT 0x8 8140 8141 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_BMSK 0x00000080 8142 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_SHFT 0x7 8143 8144 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_BMSK 0x0000001f 8145 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_SHFT 0x0 8146 8147 //// Register REO_R0_CACHE_CTL_CONFIG //// 8148 8149 #define HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x) (x+0x00000684) 8150 #define HWIO_REO_R0_CACHE_CTL_CONFIG_PHYS(x) (x+0x00000684) 8151 #define HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK 0xffffffff 8152 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SHFT 0 8153 #define HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x) \ 8154 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK) 8155 #define HWIO_REO_R0_CACHE_CTL_CONFIG_INM(x, mask) \ 8156 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask) 8157 #define HWIO_REO_R0_CACHE_CTL_CONFIG_OUT(x, val) \ 8158 out_dword( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), val) 8159 #define HWIO_REO_R0_CACHE_CTL_CONFIG_OUTM(x, mask, val) \ 8160 do {\ 8161 HWIO_INTLOCK(); \ 8162 out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x)); \ 8163 HWIO_INTFREE();\ 8164 } while (0) 8165 8166 #define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_BMSK 0xff000000 8167 #define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_SHFT 0x18 8168 8169 #define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_BMSK 0x00800000 8170 #define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_SHFT 0x17 8171 8172 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_BMSK 0x00400000 8173 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_SHFT 0x16 8174 8175 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_BMSK 0x00200000 8176 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_SHFT 0x15 8177 8178 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_BMSK 0x00100000 8179 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_SHFT 0x14 8180 8181 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_BMSK 0x00080000 8182 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_SHFT 0x13 8183 8184 #define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_BMSK 0x00040000 8185 #define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_SHFT 0x12 8186 8187 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_BMSK 0x00020000 8188 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_SHFT 0x11 8189 8190 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_BMSK 0x0001fe00 8191 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_SHFT 0x9 8192 8193 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_BMSK 0x000001ff 8194 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_SHFT 0x0 8195 8196 //// Register REO_R0_CACHE_CTL_CONTROL //// 8197 8198 #define HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x) (x+0x00000688) 8199 #define HWIO_REO_R0_CACHE_CTL_CONTROL_PHYS(x) (x+0x00000688) 8200 #define HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK 0x00000003 8201 #define HWIO_REO_R0_CACHE_CTL_CONTROL_SHFT 0 8202 #define HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x) \ 8203 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK) 8204 #define HWIO_REO_R0_CACHE_CTL_CONTROL_INM(x, mask) \ 8205 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask) 8206 #define HWIO_REO_R0_CACHE_CTL_CONTROL_OUT(x, val) \ 8207 out_dword( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), val) 8208 #define HWIO_REO_R0_CACHE_CTL_CONTROL_OUTM(x, mask, val) \ 8209 do {\ 8210 HWIO_INTLOCK(); \ 8211 out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x)); \ 8212 HWIO_INTFREE();\ 8213 } while (0) 8214 8215 #define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_BMSK 0x00000002 8216 #define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_SHFT 0x1 8217 8218 #define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_BMSK 0x00000001 8219 #define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_SHFT 0x0 8220 8221 //// Register REO_R0_CACHE_CTL_CONFIG_SET //// 8222 8223 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x) (x+0x0000068c) 8224 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_PHYS(x) (x+0x0000068c) 8225 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_RMSK 0x01ffffff 8226 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_SHFT 0 8227 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_IN(x) \ 8228 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONFIG_SET_RMSK) 8229 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_INM(x, mask) \ 8230 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), mask) 8231 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OUT(x, val) \ 8232 out_dword( HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), val) 8233 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OUTM(x, mask, val) \ 8234 do {\ 8235 HWIO_INTLOCK(); \ 8236 out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONFIG_SET_IN(x)); \ 8237 HWIO_INTFREE();\ 8238 } while (0) 8239 8240 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_DESC_TYPE_BITMAP_BMSK 0x01fe0000 8241 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_DESC_TYPE_BITMAP_SHFT 0x11 8242 8243 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CACHE_EMPTY_THRESHOLD_SET2_BMSK 0x0001fe00 8244 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CACHE_EMPTY_THRESHOLD_SET2_SHFT 0x9 8245 8246 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CACHE_LINE_USE_NUM_SET2_BMSK 0x000001ff 8247 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CACHE_LINE_USE_NUM_SET2_SHFT 0x0 8248 8249 //// Register REO_R0_CACHE_CTL_SET_SIZE //// 8250 8251 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x) (x+0x00000690) 8252 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_PHYS(x) (x+0x00000690) 8253 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_RMSK 0x000001ff 8254 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SHFT 0 8255 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_IN(x) \ 8256 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), HWIO_REO_R0_CACHE_CTL_SET_SIZE_RMSK) 8257 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_INM(x, mask) \ 8258 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), mask) 8259 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OUT(x, val) \ 8260 out_dword( HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), val) 8261 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OUTM(x, mask, val) \ 8262 do {\ 8263 HWIO_INTLOCK(); \ 8264 out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_SET_SIZE_IN(x)); \ 8265 HWIO_INTFREE();\ 8266 } while (0) 8267 8268 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_BMSK 0x000001ff 8269 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_SHFT 0x0 8270 8271 //// Register REO_R0_CLK_GATE_CTRL //// 8272 8273 #define HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x) (x+0x00000694) 8274 #define HWIO_REO_R0_CLK_GATE_CTRL_PHYS(x) (x+0x00000694) 8275 #define HWIO_REO_R0_CLK_GATE_CTRL_RMSK 0x0007ffff 8276 #define HWIO_REO_R0_CLK_GATE_CTRL_SHFT 0 8277 #define HWIO_REO_R0_CLK_GATE_CTRL_IN(x) \ 8278 in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), HWIO_REO_R0_CLK_GATE_CTRL_RMSK) 8279 #define HWIO_REO_R0_CLK_GATE_CTRL_INM(x, mask) \ 8280 in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask) 8281 #define HWIO_REO_R0_CLK_GATE_CTRL_OUT(x, val) \ 8282 out_dword( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), val) 8283 #define HWIO_REO_R0_CLK_GATE_CTRL_OUTM(x, mask, val) \ 8284 do {\ 8285 HWIO_INTLOCK(); \ 8286 out_dword_masked_ns(HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask, val, HWIO_REO_R0_CLK_GATE_CTRL_IN(x)); \ 8287 HWIO_INTFREE();\ 8288 } while (0) 8289 8290 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_BMSK 0x00040000 8291 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_SHFT 0x12 8292 8293 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_BMSK 0x00020000 8294 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_SHFT 0x11 8295 8296 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_BMSK 0x00010000 8297 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_SHFT 0x10 8298 8299 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_BMSK 0x00008000 8300 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_SHFT 0xf 8301 8302 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_BMSK 0x00004000 8303 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_SHFT 0xe 8304 8305 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_BMSK 0x00002000 8306 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_SHFT 0xd 8307 8308 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_1_BMSK 0x00001000 8309 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_1_SHFT 0xc 8310 8311 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_0_BMSK 0x00000800 8312 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_0_SHFT 0xb 8313 8314 #define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_BMSK 0x00000400 8315 #define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_SHFT 0xa 8316 8317 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_BMSK 0x000003ff 8318 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SHFT 0x0 8319 8320 //// Register REO_R0_EVENTMASK_IX_0 //// 8321 8322 #define HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x) (x+0x00000698) 8323 #define HWIO_REO_R0_EVENTMASK_IX_0_PHYS(x) (x+0x00000698) 8324 #define HWIO_REO_R0_EVENTMASK_IX_0_RMSK 0xffffffff 8325 #define HWIO_REO_R0_EVENTMASK_IX_0_SHFT 0 8326 #define HWIO_REO_R0_EVENTMASK_IX_0_IN(x) \ 8327 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_0_RMSK) 8328 #define HWIO_REO_R0_EVENTMASK_IX_0_INM(x, mask) \ 8329 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask) 8330 #define HWIO_REO_R0_EVENTMASK_IX_0_OUT(x, val) \ 8331 out_dword( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), val) 8332 #define HWIO_REO_R0_EVENTMASK_IX_0_OUTM(x, mask, val) \ 8333 do {\ 8334 HWIO_INTLOCK(); \ 8335 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_0_IN(x)); \ 8336 HWIO_INTFREE();\ 8337 } while (0) 8338 8339 #define HWIO_REO_R0_EVENTMASK_IX_0_MASK_BMSK 0xffffffff 8340 #define HWIO_REO_R0_EVENTMASK_IX_0_MASK_SHFT 0x0 8341 8342 //// Register REO_R0_EVENTMASK_IX_1 //// 8343 8344 #define HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x) (x+0x0000069c) 8345 #define HWIO_REO_R0_EVENTMASK_IX_1_PHYS(x) (x+0x0000069c) 8346 #define HWIO_REO_R0_EVENTMASK_IX_1_RMSK 0xffffffff 8347 #define HWIO_REO_R0_EVENTMASK_IX_1_SHFT 0 8348 #define HWIO_REO_R0_EVENTMASK_IX_1_IN(x) \ 8349 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_1_RMSK) 8350 #define HWIO_REO_R0_EVENTMASK_IX_1_INM(x, mask) \ 8351 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask) 8352 #define HWIO_REO_R0_EVENTMASK_IX_1_OUT(x, val) \ 8353 out_dword( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), val) 8354 #define HWIO_REO_R0_EVENTMASK_IX_1_OUTM(x, mask, val) \ 8355 do {\ 8356 HWIO_INTLOCK(); \ 8357 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_1_IN(x)); \ 8358 HWIO_INTFREE();\ 8359 } while (0) 8360 8361 #define HWIO_REO_R0_EVENTMASK_IX_1_MASK_BMSK 0xffffffff 8362 #define HWIO_REO_R0_EVENTMASK_IX_1_MASK_SHFT 0x0 8363 8364 //// Register REO_R0_EVENTMASK_IX_2 //// 8365 8366 #define HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x) (x+0x000006a0) 8367 #define HWIO_REO_R0_EVENTMASK_IX_2_PHYS(x) (x+0x000006a0) 8368 #define HWIO_REO_R0_EVENTMASK_IX_2_RMSK 0xffffffff 8369 #define HWIO_REO_R0_EVENTMASK_IX_2_SHFT 0 8370 #define HWIO_REO_R0_EVENTMASK_IX_2_IN(x) \ 8371 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_2_RMSK) 8372 #define HWIO_REO_R0_EVENTMASK_IX_2_INM(x, mask) \ 8373 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask) 8374 #define HWIO_REO_R0_EVENTMASK_IX_2_OUT(x, val) \ 8375 out_dword( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), val) 8376 #define HWIO_REO_R0_EVENTMASK_IX_2_OUTM(x, mask, val) \ 8377 do {\ 8378 HWIO_INTLOCK(); \ 8379 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_2_IN(x)); \ 8380 HWIO_INTFREE();\ 8381 } while (0) 8382 8383 #define HWIO_REO_R0_EVENTMASK_IX_2_MASK_BMSK 0xffffffff 8384 #define HWIO_REO_R0_EVENTMASK_IX_2_MASK_SHFT 0x0 8385 8386 //// Register REO_R0_EVENTMASK_IX_3 //// 8387 8388 #define HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x) (x+0x000006a4) 8389 #define HWIO_REO_R0_EVENTMASK_IX_3_PHYS(x) (x+0x000006a4) 8390 #define HWIO_REO_R0_EVENTMASK_IX_3_RMSK 0xffffffff 8391 #define HWIO_REO_R0_EVENTMASK_IX_3_SHFT 0 8392 #define HWIO_REO_R0_EVENTMASK_IX_3_IN(x) \ 8393 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_3_RMSK) 8394 #define HWIO_REO_R0_EVENTMASK_IX_3_INM(x, mask) \ 8395 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask) 8396 #define HWIO_REO_R0_EVENTMASK_IX_3_OUT(x, val) \ 8397 out_dword( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), val) 8398 #define HWIO_REO_R0_EVENTMASK_IX_3_OUTM(x, mask, val) \ 8399 do {\ 8400 HWIO_INTLOCK(); \ 8401 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_3_IN(x)); \ 8402 HWIO_INTFREE();\ 8403 } while (0) 8404 8405 #define HWIO_REO_R0_EVENTMASK_IX_3_MASK_BMSK 0xffffffff 8406 #define HWIO_REO_R0_EVENTMASK_IX_3_MASK_SHFT 0x0 8407 8408 //// Register REO_R1_MISC_DEBUG_CTRL //// 8409 8410 #define HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x) (x+0x00002000) 8411 #define HWIO_REO_R1_MISC_DEBUG_CTRL_PHYS(x) (x+0x00002000) 8412 #define HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK 0x7fffffff 8413 #define HWIO_REO_R1_MISC_DEBUG_CTRL_SHFT 0 8414 #define HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x) \ 8415 in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK) 8416 #define HWIO_REO_R1_MISC_DEBUG_CTRL_INM(x, mask) \ 8417 in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask) 8418 #define HWIO_REO_R1_MISC_DEBUG_CTRL_OUT(x, val) \ 8419 out_dword( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), val) 8420 #define HWIO_REO_R1_MISC_DEBUG_CTRL_OUTM(x, mask, val) \ 8421 do {\ 8422 HWIO_INTLOCK(); \ 8423 out_dword_masked_ns(HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x)); \ 8424 HWIO_INTFREE();\ 8425 } while (0) 8426 8427 #define HWIO_REO_R1_MISC_DEBUG_CTRL_IDLE_REQ_BMSK 0x40000000 8428 #define HWIO_REO_R1_MISC_DEBUG_CTRL_IDLE_REQ_SHFT 0x1e 8429 8430 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_BMSK 0x3ff00000 8431 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_SHFT 0x14 8432 8433 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_BMSK 0x000ffc00 8434 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_SHFT 0xa 8435 8436 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_BMSK 0x000003ff 8437 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_SHFT 0x0 8438 8439 //// Register REO_R1_MISC_PERF_DEBUG_CTRL //// 8440 8441 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x) (x+0x00002004) 8442 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PHYS(x) (x+0x00002004) 8443 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK 0x00ffffff 8444 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_SHFT 0 8445 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x) \ 8446 in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK) 8447 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_INM(x, mask) \ 8448 in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask) 8449 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUT(x, val) \ 8450 out_dword( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), val) 8451 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUTM(x, mask, val) \ 8452 do {\ 8453 HWIO_INTLOCK(); \ 8454 out_dword_masked_ns(HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x)); \ 8455 HWIO_INTFREE();\ 8456 } while (0) 8457 8458 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_BMSK 0x00fff000 8459 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_SHFT 0xc 8460 8461 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_BMSK 0x00000fff 8462 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_SHFT 0x0 8463 8464 //// Register REO_R1_CACHE_CTL_DEBUG_CONTROL //// 8465 8466 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x) (x+0x00002008) 8467 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_PHYS(x) (x+0x00002008) 8468 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK 0x00000fff 8469 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_SHFT 0 8470 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x) \ 8471 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK) 8472 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_INM(x, mask) \ 8473 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask) 8474 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUT(x, val) \ 8475 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), val) 8476 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUTM(x, mask, val) \ 8477 do {\ 8478 HWIO_INTLOCK(); \ 8479 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x)); \ 8480 HWIO_INTFREE();\ 8481 } while (0) 8482 8483 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_BMSK 0x00000800 8484 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_SHFT 0xb 8485 8486 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_BMSK 0x00000400 8487 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_SHFT 0xa 8488 8489 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_BMSK 0x00000200 8490 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_SHFT 0x9 8491 8492 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_BMSK 0x000001ff 8493 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_SHFT 0x0 8494 8495 //// Register REO_R1_CACHE_CTL_DEBUG_HIT_COUNT //// 8496 8497 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x) (x+0x0000200c) 8498 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_PHYS(x) (x+0x0000200c) 8499 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK 0xffffffff 8500 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_SHFT 0 8501 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x) \ 8502 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK) 8503 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_INM(x, mask) \ 8504 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask) 8505 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUT(x, val) \ 8506 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), val) 8507 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUTM(x, mask, val) \ 8508 do {\ 8509 HWIO_INTLOCK(); \ 8510 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x)); \ 8511 HWIO_INTFREE();\ 8512 } while (0) 8513 8514 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_BMSK 0xffffffff 8515 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_SHFT 0x0 8516 8517 //// Register REO_R1_CACHE_CTL_DEBUG_MISS_COUNT //// 8518 8519 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x) (x+0x00002010) 8520 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_PHYS(x) (x+0x00002010) 8521 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK 0x00ffffff 8522 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_SHFT 0 8523 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x) \ 8524 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK) 8525 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_INM(x, mask) \ 8526 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask) 8527 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUT(x, val) \ 8528 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), val) 8529 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUTM(x, mask, val) \ 8530 do {\ 8531 HWIO_INTLOCK(); \ 8532 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x)); \ 8533 HWIO_INTFREE();\ 8534 } while (0) 8535 8536 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_BMSK 0x00ffffff 8537 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_SHFT 0x0 8538 8539 //// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW //// 8540 8541 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x) (x+0x00002014) 8542 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_PHYS(x) (x+0x00002014) 8543 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK 0xffffffff 8544 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_SHFT 0 8545 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x) \ 8546 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK) 8547 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_INM(x, mask) \ 8548 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask) 8549 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUT(x, val) \ 8550 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), val) 8551 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUTM(x, mask, val) \ 8552 do {\ 8553 HWIO_INTLOCK(); \ 8554 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x)); \ 8555 HWIO_INTFREE();\ 8556 } while (0) 8557 8558 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_BMSK 0xffffffff 8559 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_SHFT 0x0 8560 8561 //// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH //// 8562 8563 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x) (x+0x00002018) 8564 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_PHYS(x) (x+0x00002018) 8565 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK 0xffffffff 8566 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_SHFT 0 8567 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x) \ 8568 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK) 8569 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_INM(x, mask) \ 8570 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask) 8571 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUT(x, val) \ 8572 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), val) 8573 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUTM(x, mask, val) \ 8574 do {\ 8575 HWIO_INTLOCK(); \ 8576 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x)); \ 8577 HWIO_INTFREE();\ 8578 } while (0) 8579 8580 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_BMSK 0xffffffff 8581 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_SHFT 0x0 8582 8583 //// Register REO_R1_CACHE_CTL_DEBUG_STM //// 8584 8585 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x) (x+0x0000201c) 8586 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_PHYS(x) (x+0x0000201c) 8587 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK 0x01ffffff 8588 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_SHFT 0 8589 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x) \ 8590 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK) 8591 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_INM(x, mask) \ 8592 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask) 8593 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUT(x, val) \ 8594 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), val) 8595 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUTM(x, mask, val) \ 8596 do {\ 8597 HWIO_INTLOCK(); \ 8598 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x)); \ 8599 HWIO_INTFREE();\ 8600 } while (0) 8601 8602 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_BMSK 0x01ffffff 8603 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_SHFT 0x0 8604 8605 //// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST //// 8606 8607 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x) (x+0x00002020) 8608 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_PHYS(x) (x+0x00002020) 8609 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK 0x0007ffff 8610 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_SHFT 0 8611 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x) \ 8612 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK) 8613 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_INM(x, mask) \ 8614 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask) 8615 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUT(x, val) \ 8616 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), val) 8617 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUTM(x, mask, val) \ 8618 do {\ 8619 HWIO_INTLOCK(); \ 8620 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x)); \ 8621 HWIO_INTFREE();\ 8622 } while (0) 8623 8624 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_BMSK 0x0007fc00 8625 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_SHFT 0xa 8626 8627 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_BMSK 0x000003ff 8628 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_SHFT 0x0 8629 8630 //// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST1 //// 8631 8632 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x) (x+0x00002024) 8633 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_PHYS(x) (x+0x00002024) 8634 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_RMSK 0x0007ffff 8635 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_SHFT 0 8636 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_IN(x) \ 8637 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_RMSK) 8638 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_INM(x, mask) \ 8639 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), mask) 8640 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_OUT(x, val) \ 8641 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), val) 8642 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_OUTM(x, mask, val) \ 8643 do {\ 8644 HWIO_INTLOCK(); \ 8645 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_IN(x)); \ 8646 HWIO_INTFREE();\ 8647 } while (0) 8648 8649 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_BMSK 0x0007fc00 8650 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_SHFT 0xa 8651 8652 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_BMSK 0x000003ff 8653 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_SHFT 0x0 8654 8655 //// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST2 //// 8656 8657 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x) (x+0x00002028) 8658 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_PHYS(x) (x+0x00002028) 8659 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_RMSK 0x0007ffff 8660 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_SHFT 0 8661 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_IN(x) \ 8662 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_RMSK) 8663 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_INM(x, mask) \ 8664 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), mask) 8665 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_OUT(x, val) \ 8666 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), val) 8667 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_OUTM(x, mask, val) \ 8668 do {\ 8669 HWIO_INTLOCK(); \ 8670 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_IN(x)); \ 8671 HWIO_INTFREE();\ 8672 } while (0) 8673 8674 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_BMSK 0x0007fc00 8675 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_SHFT 0xa 8676 8677 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_BMSK 0x000003ff 8678 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_SHFT 0x0 8679 8680 //// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST3 //// 8681 8682 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x) (x+0x0000202c) 8683 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_PHYS(x) (x+0x0000202c) 8684 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_RMSK 0x0007ffff 8685 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_SHFT 0 8686 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_IN(x) \ 8687 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_RMSK) 8688 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_INM(x, mask) \ 8689 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), mask) 8690 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_OUT(x, val) \ 8691 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), val) 8692 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_OUTM(x, mask, val) \ 8693 do {\ 8694 HWIO_INTLOCK(); \ 8695 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_IN(x)); \ 8696 HWIO_INTFREE();\ 8697 } while (0) 8698 8699 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_BMSK 0x0007fc00 8700 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_SHFT 0xa 8701 8702 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_BMSK 0x000003ff 8703 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_SHFT 0x0 8704 8705 //// Register REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW //// 8706 8707 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x) (x+0x00002030) 8708 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_PHYS(x) (x+0x00002030) 8709 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_RMSK 0xffffffff 8710 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_SHFT 0 8711 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_IN(x) \ 8712 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_RMSK) 8713 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_INM(x, mask) \ 8714 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), mask) 8715 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_OUT(x, val) \ 8716 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), val) 8717 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_OUTM(x, mask, val) \ 8718 do {\ 8719 HWIO_INTLOCK(); \ 8720 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_IN(x)); \ 8721 HWIO_INTFREE();\ 8722 } while (0) 8723 8724 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_BMSK 0xffffffff 8725 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_SHFT 0x0 8726 8727 //// Register REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH //// 8728 8729 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x) (x+0x00002034) 8730 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_PHYS(x) (x+0x00002034) 8731 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_RMSK 0xffffffff 8732 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_SHFT 0 8733 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_IN(x) \ 8734 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_RMSK) 8735 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_INM(x, mask) \ 8736 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), mask) 8737 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_OUT(x, val) \ 8738 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), val) 8739 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_OUTM(x, mask, val) \ 8740 do {\ 8741 HWIO_INTLOCK(); \ 8742 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_IN(x)); \ 8743 HWIO_INTFREE();\ 8744 } while (0) 8745 8746 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_BMSK 0xffffffff 8747 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_SHFT 0x0 8748 8749 //// Register REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER //// 8750 8751 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x) (x+0x00002038) 8752 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_PHYS(x) (x+0x00002038) 8753 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_RMSK 0x000fffff 8754 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SHFT 0 8755 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_IN(x) \ 8756 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_RMSK) 8757 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_INM(x, mask) \ 8758 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), mask) 8759 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_OUT(x, val) \ 8760 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), val) 8761 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_OUTM(x, mask, val) \ 8762 do {\ 8763 HWIO_INTLOCK(); \ 8764 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_IN(x)); \ 8765 HWIO_INTFREE();\ 8766 } while (0) 8767 8768 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_BMSK 0x000ffc00 8769 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_SHFT 0xa 8770 8771 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_BMSK 0x000003ff 8772 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_SHFT 0x0 8773 8774 //// Register REO_R1_CACHE_CTL_END_OF_TEST_CHECK //// 8775 8776 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x) (x+0x0000203c) 8777 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_PHYS(x) (x+0x0000203c) 8778 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK 0x00000001 8779 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_SHFT 0 8780 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x) \ 8781 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK) 8782 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_INM(x, mask) \ 8783 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask) 8784 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUT(x, val) \ 8785 out_dword( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), val) 8786 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 8787 do {\ 8788 HWIO_INTLOCK(); \ 8789 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x)); \ 8790 HWIO_INTFREE();\ 8791 } while (0) 8792 8793 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 8794 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 8795 8796 //// Register REO_R1_END_OF_TEST_CHECK //// 8797 8798 #define HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00002040) 8799 #define HWIO_REO_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00002040) 8800 #define HWIO_REO_R1_END_OF_TEST_CHECK_RMSK 0x00000001 8801 #define HWIO_REO_R1_END_OF_TEST_CHECK_SHFT 0 8802 #define HWIO_REO_R1_END_OF_TEST_CHECK_IN(x) \ 8803 in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_END_OF_TEST_CHECK_RMSK) 8804 #define HWIO_REO_R1_END_OF_TEST_CHECK_INM(x, mask) \ 8805 in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask) 8806 #define HWIO_REO_R1_END_OF_TEST_CHECK_OUT(x, val) \ 8807 out_dword( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), val) 8808 #define HWIO_REO_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 8809 do {\ 8810 HWIO_INTLOCK(); \ 8811 out_dword_masked_ns(HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_END_OF_TEST_CHECK_IN(x)); \ 8812 HWIO_INTFREE();\ 8813 } while (0) 8814 8815 #define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 8816 #define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 8817 8818 //// Register REO_R1_SM_ALL_IDLE //// 8819 8820 #define HWIO_REO_R1_SM_ALL_IDLE_ADDR(x) (x+0x00002044) 8821 #define HWIO_REO_R1_SM_ALL_IDLE_PHYS(x) (x+0x00002044) 8822 #define HWIO_REO_R1_SM_ALL_IDLE_RMSK 0x00000007 8823 #define HWIO_REO_R1_SM_ALL_IDLE_SHFT 0 8824 #define HWIO_REO_R1_SM_ALL_IDLE_IN(x) \ 8825 in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), HWIO_REO_R1_SM_ALL_IDLE_RMSK) 8826 #define HWIO_REO_R1_SM_ALL_IDLE_INM(x, mask) \ 8827 in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask) 8828 #define HWIO_REO_R1_SM_ALL_IDLE_OUT(x, val) \ 8829 out_dword( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), val) 8830 #define HWIO_REO_R1_SM_ALL_IDLE_OUTM(x, mask, val) \ 8831 do {\ 8832 HWIO_INTLOCK(); \ 8833 out_dword_masked_ns(HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask, val, HWIO_REO_R1_SM_ALL_IDLE_IN(x)); \ 8834 HWIO_INTFREE();\ 8835 } while (0) 8836 8837 #define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_BMSK 0x00000004 8838 #define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_SHFT 0x2 8839 8840 #define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_BMSK 0x00000002 8841 #define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_SHFT 0x1 8842 8843 #define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_BMSK 0x00000001 8844 #define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_SHFT 0x0 8845 8846 //// Register REO_R1_TESTBUS_CTRL //// 8847 8848 #define HWIO_REO_R1_TESTBUS_CTRL_ADDR(x) (x+0x00002048) 8849 #define HWIO_REO_R1_TESTBUS_CTRL_PHYS(x) (x+0x00002048) 8850 #define HWIO_REO_R1_TESTBUS_CTRL_RMSK 0x0000007f 8851 #define HWIO_REO_R1_TESTBUS_CTRL_SHFT 0 8852 #define HWIO_REO_R1_TESTBUS_CTRL_IN(x) \ 8853 in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), HWIO_REO_R1_TESTBUS_CTRL_RMSK) 8854 #define HWIO_REO_R1_TESTBUS_CTRL_INM(x, mask) \ 8855 in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask) 8856 #define HWIO_REO_R1_TESTBUS_CTRL_OUT(x, val) \ 8857 out_dword( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), val) 8858 #define HWIO_REO_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ 8859 do {\ 8860 HWIO_INTLOCK(); \ 8861 out_dword_masked_ns(HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_CTRL_IN(x)); \ 8862 HWIO_INTFREE();\ 8863 } while (0) 8864 8865 #define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_BMSK 0x0000007f 8866 #define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_SHFT 0x0 8867 8868 //// Register REO_R1_TESTBUS_LOWER //// 8869 8870 #define HWIO_REO_R1_TESTBUS_LOWER_ADDR(x) (x+0x0000204c) 8871 #define HWIO_REO_R1_TESTBUS_LOWER_PHYS(x) (x+0x0000204c) 8872 #define HWIO_REO_R1_TESTBUS_LOWER_RMSK 0xffffffff 8873 #define HWIO_REO_R1_TESTBUS_LOWER_SHFT 0 8874 #define HWIO_REO_R1_TESTBUS_LOWER_IN(x) \ 8875 in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), HWIO_REO_R1_TESTBUS_LOWER_RMSK) 8876 #define HWIO_REO_R1_TESTBUS_LOWER_INM(x, mask) \ 8877 in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask) 8878 #define HWIO_REO_R1_TESTBUS_LOWER_OUT(x, val) \ 8879 out_dword( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), val) 8880 #define HWIO_REO_R1_TESTBUS_LOWER_OUTM(x, mask, val) \ 8881 do {\ 8882 HWIO_INTLOCK(); \ 8883 out_dword_masked_ns(HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_LOWER_IN(x)); \ 8884 HWIO_INTFREE();\ 8885 } while (0) 8886 8887 #define HWIO_REO_R1_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 8888 #define HWIO_REO_R1_TESTBUS_LOWER_VALUE_SHFT 0x0 8889 8890 //// Register REO_R1_TESTBUS_HIGHER //// 8891 8892 #define HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x) (x+0x00002050) 8893 #define HWIO_REO_R1_TESTBUS_HIGHER_PHYS(x) (x+0x00002050) 8894 #define HWIO_REO_R1_TESTBUS_HIGHER_RMSK 0x000000ff 8895 #define HWIO_REO_R1_TESTBUS_HIGHER_SHFT 0 8896 #define HWIO_REO_R1_TESTBUS_HIGHER_IN(x) \ 8897 in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), HWIO_REO_R1_TESTBUS_HIGHER_RMSK) 8898 #define HWIO_REO_R1_TESTBUS_HIGHER_INM(x, mask) \ 8899 in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask) 8900 #define HWIO_REO_R1_TESTBUS_HIGHER_OUT(x, val) \ 8901 out_dword( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), val) 8902 #define HWIO_REO_R1_TESTBUS_HIGHER_OUTM(x, mask, val) \ 8903 do {\ 8904 HWIO_INTLOCK(); \ 8905 out_dword_masked_ns(HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_HIGHER_IN(x)); \ 8906 HWIO_INTFREE();\ 8907 } while (0) 8908 8909 #define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_BMSK 0x000000ff 8910 #define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_SHFT 0x0 8911 8912 //// Register REO_R1_SM_STATES_IX_0 //// 8913 8914 #define HWIO_REO_R1_SM_STATES_IX_0_ADDR(x) (x+0x00002054) 8915 #define HWIO_REO_R1_SM_STATES_IX_0_PHYS(x) (x+0x00002054) 8916 #define HWIO_REO_R1_SM_STATES_IX_0_RMSK 0xffffffff 8917 #define HWIO_REO_R1_SM_STATES_IX_0_SHFT 0 8918 #define HWIO_REO_R1_SM_STATES_IX_0_IN(x) \ 8919 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), HWIO_REO_R1_SM_STATES_IX_0_RMSK) 8920 #define HWIO_REO_R1_SM_STATES_IX_0_INM(x, mask) \ 8921 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask) 8922 #define HWIO_REO_R1_SM_STATES_IX_0_OUT(x, val) \ 8923 out_dword( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), val) 8924 #define HWIO_REO_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ 8925 do {\ 8926 HWIO_INTLOCK(); \ 8927 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_0_IN(x)); \ 8928 HWIO_INTFREE();\ 8929 } while (0) 8930 8931 #define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_BMSK 0xffffffff 8932 #define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_SHFT 0x0 8933 8934 //// Register REO_R1_SM_STATES_IX_1 //// 8935 8936 #define HWIO_REO_R1_SM_STATES_IX_1_ADDR(x) (x+0x00002058) 8937 #define HWIO_REO_R1_SM_STATES_IX_1_PHYS(x) (x+0x00002058) 8938 #define HWIO_REO_R1_SM_STATES_IX_1_RMSK 0xffffffff 8939 #define HWIO_REO_R1_SM_STATES_IX_1_SHFT 0 8940 #define HWIO_REO_R1_SM_STATES_IX_1_IN(x) \ 8941 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), HWIO_REO_R1_SM_STATES_IX_1_RMSK) 8942 #define HWIO_REO_R1_SM_STATES_IX_1_INM(x, mask) \ 8943 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask) 8944 #define HWIO_REO_R1_SM_STATES_IX_1_OUT(x, val) \ 8945 out_dword( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), val) 8946 #define HWIO_REO_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ 8947 do {\ 8948 HWIO_INTLOCK(); \ 8949 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_1_IN(x)); \ 8950 HWIO_INTFREE();\ 8951 } while (0) 8952 8953 #define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_BMSK 0xffffffff 8954 #define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_SHFT 0x0 8955 8956 //// Register REO_R1_SM_STATES_IX_2 //// 8957 8958 #define HWIO_REO_R1_SM_STATES_IX_2_ADDR(x) (x+0x0000205c) 8959 #define HWIO_REO_R1_SM_STATES_IX_2_PHYS(x) (x+0x0000205c) 8960 #define HWIO_REO_R1_SM_STATES_IX_2_RMSK 0xffffffff 8961 #define HWIO_REO_R1_SM_STATES_IX_2_SHFT 0 8962 #define HWIO_REO_R1_SM_STATES_IX_2_IN(x) \ 8963 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), HWIO_REO_R1_SM_STATES_IX_2_RMSK) 8964 #define HWIO_REO_R1_SM_STATES_IX_2_INM(x, mask) \ 8965 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask) 8966 #define HWIO_REO_R1_SM_STATES_IX_2_OUT(x, val) \ 8967 out_dword( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), val) 8968 #define HWIO_REO_R1_SM_STATES_IX_2_OUTM(x, mask, val) \ 8969 do {\ 8970 HWIO_INTLOCK(); \ 8971 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_2_IN(x)); \ 8972 HWIO_INTFREE();\ 8973 } while (0) 8974 8975 #define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_BMSK 0xffffffff 8976 #define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_SHFT 0x0 8977 8978 //// Register REO_R1_SM_STATES_IX_3 //// 8979 8980 #define HWIO_REO_R1_SM_STATES_IX_3_ADDR(x) (x+0x00002060) 8981 #define HWIO_REO_R1_SM_STATES_IX_3_PHYS(x) (x+0x00002060) 8982 #define HWIO_REO_R1_SM_STATES_IX_3_RMSK 0xffffffff 8983 #define HWIO_REO_R1_SM_STATES_IX_3_SHFT 0 8984 #define HWIO_REO_R1_SM_STATES_IX_3_IN(x) \ 8985 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), HWIO_REO_R1_SM_STATES_IX_3_RMSK) 8986 #define HWIO_REO_R1_SM_STATES_IX_3_INM(x, mask) \ 8987 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask) 8988 #define HWIO_REO_R1_SM_STATES_IX_3_OUT(x, val) \ 8989 out_dword( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), val) 8990 #define HWIO_REO_R1_SM_STATES_IX_3_OUTM(x, mask, val) \ 8991 do {\ 8992 HWIO_INTLOCK(); \ 8993 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_3_IN(x)); \ 8994 HWIO_INTFREE();\ 8995 } while (0) 8996 8997 #define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_BMSK 0xffffffff 8998 #define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_SHFT 0x0 8999 9000 //// Register REO_R1_SM_STATES_IX_4 //// 9001 9002 #define HWIO_REO_R1_SM_STATES_IX_4_ADDR(x) (x+0x00002064) 9003 #define HWIO_REO_R1_SM_STATES_IX_4_PHYS(x) (x+0x00002064) 9004 #define HWIO_REO_R1_SM_STATES_IX_4_RMSK 0xffffffff 9005 #define HWIO_REO_R1_SM_STATES_IX_4_SHFT 0 9006 #define HWIO_REO_R1_SM_STATES_IX_4_IN(x) \ 9007 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), HWIO_REO_R1_SM_STATES_IX_4_RMSK) 9008 #define HWIO_REO_R1_SM_STATES_IX_4_INM(x, mask) \ 9009 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask) 9010 #define HWIO_REO_R1_SM_STATES_IX_4_OUT(x, val) \ 9011 out_dword( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), val) 9012 #define HWIO_REO_R1_SM_STATES_IX_4_OUTM(x, mask, val) \ 9013 do {\ 9014 HWIO_INTLOCK(); \ 9015 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_4_IN(x)); \ 9016 HWIO_INTFREE();\ 9017 } while (0) 9018 9019 #define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_BMSK 0xffffffff 9020 #define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_SHFT 0x0 9021 9022 //// Register REO_R1_SM_STATES_IX_5 //// 9023 9024 #define HWIO_REO_R1_SM_STATES_IX_5_ADDR(x) (x+0x00002068) 9025 #define HWIO_REO_R1_SM_STATES_IX_5_PHYS(x) (x+0x00002068) 9026 #define HWIO_REO_R1_SM_STATES_IX_5_RMSK 0xffffffff 9027 #define HWIO_REO_R1_SM_STATES_IX_5_SHFT 0 9028 #define HWIO_REO_R1_SM_STATES_IX_5_IN(x) \ 9029 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), HWIO_REO_R1_SM_STATES_IX_5_RMSK) 9030 #define HWIO_REO_R1_SM_STATES_IX_5_INM(x, mask) \ 9031 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask) 9032 #define HWIO_REO_R1_SM_STATES_IX_5_OUT(x, val) \ 9033 out_dword( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), val) 9034 #define HWIO_REO_R1_SM_STATES_IX_5_OUTM(x, mask, val) \ 9035 do {\ 9036 HWIO_INTLOCK(); \ 9037 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_5_IN(x)); \ 9038 HWIO_INTFREE();\ 9039 } while (0) 9040 9041 #define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_BMSK 0xffffffff 9042 #define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_SHFT 0x0 9043 9044 //// Register REO_R1_SM_STATES_IX_6 //// 9045 9046 #define HWIO_REO_R1_SM_STATES_IX_6_ADDR(x) (x+0x0000206c) 9047 #define HWIO_REO_R1_SM_STATES_IX_6_PHYS(x) (x+0x0000206c) 9048 #define HWIO_REO_R1_SM_STATES_IX_6_RMSK 0xffffffff 9049 #define HWIO_REO_R1_SM_STATES_IX_6_SHFT 0 9050 #define HWIO_REO_R1_SM_STATES_IX_6_IN(x) \ 9051 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), HWIO_REO_R1_SM_STATES_IX_6_RMSK) 9052 #define HWIO_REO_R1_SM_STATES_IX_6_INM(x, mask) \ 9053 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask) 9054 #define HWIO_REO_R1_SM_STATES_IX_6_OUT(x, val) \ 9055 out_dword( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), val) 9056 #define HWIO_REO_R1_SM_STATES_IX_6_OUTM(x, mask, val) \ 9057 do {\ 9058 HWIO_INTLOCK(); \ 9059 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_6_IN(x)); \ 9060 HWIO_INTFREE();\ 9061 } while (0) 9062 9063 #define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_BMSK 0xffffffff 9064 #define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_SHFT 0x0 9065 9066 //// Register REO_R1_IDLE_STATES_IX_0 //// 9067 9068 #define HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x) (x+0x00002070) 9069 #define HWIO_REO_R1_IDLE_STATES_IX_0_PHYS(x) (x+0x00002070) 9070 #define HWIO_REO_R1_IDLE_STATES_IX_0_RMSK 0xffffffff 9071 #define HWIO_REO_R1_IDLE_STATES_IX_0_SHFT 0 9072 #define HWIO_REO_R1_IDLE_STATES_IX_0_IN(x) \ 9073 in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), HWIO_REO_R1_IDLE_STATES_IX_0_RMSK) 9074 #define HWIO_REO_R1_IDLE_STATES_IX_0_INM(x, mask) \ 9075 in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask) 9076 #define HWIO_REO_R1_IDLE_STATES_IX_0_OUT(x, val) \ 9077 out_dword( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), val) 9078 #define HWIO_REO_R1_IDLE_STATES_IX_0_OUTM(x, mask, val) \ 9079 do {\ 9080 HWIO_INTLOCK(); \ 9081 out_dword_masked_ns(HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_IDLE_STATES_IX_0_IN(x)); \ 9082 HWIO_INTFREE();\ 9083 } while (0) 9084 9085 #define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_BMSK 0xffffffff 9086 #define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_SHFT 0x0 9087 9088 //// Register REO_R1_INVALID_APB_ACCESS //// 9089 9090 #define HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x) (x+0x00002074) 9091 #define HWIO_REO_R1_INVALID_APB_ACCESS_PHYS(x) (x+0x00002074) 9092 #define HWIO_REO_R1_INVALID_APB_ACCESS_RMSK 0x0007ffff 9093 #define HWIO_REO_R1_INVALID_APB_ACCESS_SHFT 0 9094 #define HWIO_REO_R1_INVALID_APB_ACCESS_IN(x) \ 9095 in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), HWIO_REO_R1_INVALID_APB_ACCESS_RMSK) 9096 #define HWIO_REO_R1_INVALID_APB_ACCESS_INM(x, mask) \ 9097 in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask) 9098 #define HWIO_REO_R1_INVALID_APB_ACCESS_OUT(x, val) \ 9099 out_dword( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), val) 9100 #define HWIO_REO_R1_INVALID_APB_ACCESS_OUTM(x, mask, val) \ 9101 do {\ 9102 HWIO_INTLOCK(); \ 9103 out_dword_masked_ns(HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask, val, HWIO_REO_R1_INVALID_APB_ACCESS_IN(x)); \ 9104 HWIO_INTFREE();\ 9105 } while (0) 9106 9107 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_BMSK 0x00060000 9108 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_SHFT 0x11 9109 9110 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_BMSK 0x0001ffff 9111 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_SHFT 0x0 9112 9113 //// Register REO_R2_RXDMA2REO0_RING_HP //// 9114 9115 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x) (x+0x00003000) 9116 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_PHYS(x) (x+0x00003000) 9117 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK 0x0000ffff 9118 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_SHFT 0 9119 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x) \ 9120 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK) 9121 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_INM(x, mask) \ 9122 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask) 9123 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUT(x, val) \ 9124 out_dword( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), val) 9125 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUTM(x, mask, val) \ 9126 do {\ 9127 HWIO_INTLOCK(); \ 9128 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x)); \ 9129 HWIO_INTFREE();\ 9130 } while (0) 9131 9132 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_BMSK 0x0000ffff 9133 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_SHFT 0x0 9134 9135 //// Register REO_R2_RXDMA2REO0_RING_TP //// 9136 9137 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x) (x+0x00003004) 9138 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_PHYS(x) (x+0x00003004) 9139 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK 0x0000ffff 9140 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_SHFT 0 9141 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x) \ 9142 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK) 9143 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_INM(x, mask) \ 9144 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask) 9145 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUT(x, val) \ 9146 out_dword( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), val) 9147 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUTM(x, mask, val) \ 9148 do {\ 9149 HWIO_INTLOCK(); \ 9150 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x)); \ 9151 HWIO_INTFREE();\ 9152 } while (0) 9153 9154 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_BMSK 0x0000ffff 9155 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_SHFT 0x0 9156 9157 //// Register REO_R2_RXDMA2REO1_RING_HP //// 9158 9159 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x) (x+0x00003008) 9160 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_PHYS(x) (x+0x00003008) 9161 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_RMSK 0x0000ffff 9162 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_SHFT 0 9163 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_IN(x) \ 9164 in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO1_RING_HP_RMSK) 9165 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_INM(x, mask) \ 9166 in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), mask) 9167 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_OUT(x, val) \ 9168 out_dword( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), val) 9169 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_OUTM(x, mask, val) \ 9170 do {\ 9171 HWIO_INTLOCK(); \ 9172 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO1_RING_HP_IN(x)); \ 9173 HWIO_INTFREE();\ 9174 } while (0) 9175 9176 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 9177 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_HEAD_PTR_SHFT 0x0 9178 9179 //// Register REO_R2_RXDMA2REO1_RING_TP //// 9180 9181 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x) (x+0x0000300c) 9182 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_PHYS(x) (x+0x0000300c) 9183 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_RMSK 0x0000ffff 9184 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_SHFT 0 9185 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_IN(x) \ 9186 in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO1_RING_TP_RMSK) 9187 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_INM(x, mask) \ 9188 in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), mask) 9189 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_OUT(x, val) \ 9190 out_dword( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), val) 9191 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_OUTM(x, mask, val) \ 9192 do {\ 9193 HWIO_INTLOCK(); \ 9194 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO1_RING_TP_IN(x)); \ 9195 HWIO_INTFREE();\ 9196 } while (0) 9197 9198 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 9199 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_TAIL_PTR_SHFT 0x0 9200 9201 //// Register REO_R2_RXDMA2REO2_RING_HP //// 9202 9203 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x) (x+0x00003010) 9204 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_PHYS(x) (x+0x00003010) 9205 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_RMSK 0x0000ffff 9206 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_SHFT 0 9207 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_IN(x) \ 9208 in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO2_RING_HP_RMSK) 9209 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_INM(x, mask) \ 9210 in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), mask) 9211 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_OUT(x, val) \ 9212 out_dword( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), val) 9213 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_OUTM(x, mask, val) \ 9214 do {\ 9215 HWIO_INTLOCK(); \ 9216 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO2_RING_HP_IN(x)); \ 9217 HWIO_INTFREE();\ 9218 } while (0) 9219 9220 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_HEAD_PTR_BMSK 0x0000ffff 9221 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_HEAD_PTR_SHFT 0x0 9222 9223 //// Register REO_R2_RXDMA2REO2_RING_TP //// 9224 9225 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x) (x+0x00003014) 9226 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_PHYS(x) (x+0x00003014) 9227 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_RMSK 0x0000ffff 9228 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_SHFT 0 9229 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_IN(x) \ 9230 in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO2_RING_TP_RMSK) 9231 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_INM(x, mask) \ 9232 in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), mask) 9233 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_OUT(x, val) \ 9234 out_dword( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), val) 9235 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_OUTM(x, mask, val) \ 9236 do {\ 9237 HWIO_INTLOCK(); \ 9238 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO2_RING_TP_IN(x)); \ 9239 HWIO_INTFREE();\ 9240 } while (0) 9241 9242 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_TAIL_PTR_BMSK 0x0000ffff 9243 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_TAIL_PTR_SHFT 0x0 9244 9245 //// Register REO_R2_WBM2REO_LINK_RING_HP //// 9246 9247 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x) (x+0x00003018) 9248 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_PHYS(x) (x+0x00003018) 9249 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK 0x0000ffff 9250 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_SHFT 0 9251 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x) \ 9252 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK) 9253 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_INM(x, mask) \ 9254 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask) 9255 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUT(x, val) \ 9256 out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), val) 9257 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUTM(x, mask, val) \ 9258 do {\ 9259 HWIO_INTLOCK(); \ 9260 out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x)); \ 9261 HWIO_INTFREE();\ 9262 } while (0) 9263 9264 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff 9265 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT 0x0 9266 9267 //// Register REO_R2_WBM2REO_LINK_RING_TP //// 9268 9269 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x) (x+0x0000301c) 9270 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_PHYS(x) (x+0x0000301c) 9271 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK 0x0000ffff 9272 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_SHFT 0 9273 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x) \ 9274 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK) 9275 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_INM(x, mask) \ 9276 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask) 9277 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUT(x, val) \ 9278 out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), val) 9279 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUTM(x, mask, val) \ 9280 do {\ 9281 HWIO_INTLOCK(); \ 9282 out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x)); \ 9283 HWIO_INTFREE();\ 9284 } while (0) 9285 9286 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff 9287 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT 0x0 9288 9289 //// Register REO_R2_REO_CMD_RING_HP //// 9290 9291 #define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x) (x+0x00003020) 9292 #define HWIO_REO_R2_REO_CMD_RING_HP_PHYS(x) (x+0x00003020) 9293 #define HWIO_REO_R2_REO_CMD_RING_HP_RMSK 0x0000ffff 9294 #define HWIO_REO_R2_REO_CMD_RING_HP_SHFT 0 9295 #define HWIO_REO_R2_REO_CMD_RING_HP_IN(x) \ 9296 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_HP_RMSK) 9297 #define HWIO_REO_R2_REO_CMD_RING_HP_INM(x, mask) \ 9298 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask) 9299 #define HWIO_REO_R2_REO_CMD_RING_HP_OUT(x, val) \ 9300 out_dword( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), val) 9301 #define HWIO_REO_R2_REO_CMD_RING_HP_OUTM(x, mask, val) \ 9302 do {\ 9303 HWIO_INTLOCK(); \ 9304 out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_HP_IN(x)); \ 9305 HWIO_INTFREE();\ 9306 } while (0) 9307 9308 #define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_BMSK 0x0000ffff 9309 #define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_SHFT 0x0 9310 9311 //// Register REO_R2_REO_CMD_RING_TP //// 9312 9313 #define HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x) (x+0x00003024) 9314 #define HWIO_REO_R2_REO_CMD_RING_TP_PHYS(x) (x+0x00003024) 9315 #define HWIO_REO_R2_REO_CMD_RING_TP_RMSK 0x0000ffff 9316 #define HWIO_REO_R2_REO_CMD_RING_TP_SHFT 0 9317 #define HWIO_REO_R2_REO_CMD_RING_TP_IN(x) \ 9318 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_TP_RMSK) 9319 #define HWIO_REO_R2_REO_CMD_RING_TP_INM(x, mask) \ 9320 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask) 9321 #define HWIO_REO_R2_REO_CMD_RING_TP_OUT(x, val) \ 9322 out_dword( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), val) 9323 #define HWIO_REO_R2_REO_CMD_RING_TP_OUTM(x, mask, val) \ 9324 do {\ 9325 HWIO_INTLOCK(); \ 9326 out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_TP_IN(x)); \ 9327 HWIO_INTFREE();\ 9328 } while (0) 9329 9330 #define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_BMSK 0x0000ffff 9331 #define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_SHFT 0x0 9332 9333 //// Register REO_R2_SW2REO_RING_HP //// 9334 9335 #define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) (x+0x00003028) 9336 #define HWIO_REO_R2_SW2REO_RING_HP_PHYS(x) (x+0x00003028) 9337 #define HWIO_REO_R2_SW2REO_RING_HP_RMSK 0x0000ffff 9338 #define HWIO_REO_R2_SW2REO_RING_HP_SHFT 0 9339 #define HWIO_REO_R2_SW2REO_RING_HP_IN(x) \ 9340 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), HWIO_REO_R2_SW2REO_RING_HP_RMSK) 9341 #define HWIO_REO_R2_SW2REO_RING_HP_INM(x, mask) \ 9342 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask) 9343 #define HWIO_REO_R2_SW2REO_RING_HP_OUT(x, val) \ 9344 out_dword( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), val) 9345 #define HWIO_REO_R2_SW2REO_RING_HP_OUTM(x, mask, val) \ 9346 do {\ 9347 HWIO_INTLOCK(); \ 9348 out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_HP_IN(x)); \ 9349 HWIO_INTFREE();\ 9350 } while (0) 9351 9352 #define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_BMSK 0x0000ffff 9353 #define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_SHFT 0x0 9354 9355 //// Register REO_R2_SW2REO_RING_TP //// 9356 9357 #define HWIO_REO_R2_SW2REO_RING_TP_ADDR(x) (x+0x0000302c) 9358 #define HWIO_REO_R2_SW2REO_RING_TP_PHYS(x) (x+0x0000302c) 9359 #define HWIO_REO_R2_SW2REO_RING_TP_RMSK 0x0000ffff 9360 #define HWIO_REO_R2_SW2REO_RING_TP_SHFT 0 9361 #define HWIO_REO_R2_SW2REO_RING_TP_IN(x) \ 9362 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), HWIO_REO_R2_SW2REO_RING_TP_RMSK) 9363 #define HWIO_REO_R2_SW2REO_RING_TP_INM(x, mask) \ 9364 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask) 9365 #define HWIO_REO_R2_SW2REO_RING_TP_OUT(x, val) \ 9366 out_dword( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), val) 9367 #define HWIO_REO_R2_SW2REO_RING_TP_OUTM(x, mask, val) \ 9368 do {\ 9369 HWIO_INTLOCK(); \ 9370 out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_TP_IN(x)); \ 9371 HWIO_INTFREE();\ 9372 } while (0) 9373 9374 #define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_BMSK 0x0000ffff 9375 #define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_SHFT 0x0 9376 9377 //// Register REO_R2_SW2REO1_RING_HP //// 9378 9379 #define HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x) (x+0x00003030) 9380 #define HWIO_REO_R2_SW2REO1_RING_HP_PHYS(x) (x+0x00003030) 9381 #define HWIO_REO_R2_SW2REO1_RING_HP_RMSK 0x0000ffff 9382 #define HWIO_REO_R2_SW2REO1_RING_HP_SHFT 0 9383 #define HWIO_REO_R2_SW2REO1_RING_HP_IN(x) \ 9384 in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), HWIO_REO_R2_SW2REO1_RING_HP_RMSK) 9385 #define HWIO_REO_R2_SW2REO1_RING_HP_INM(x, mask) \ 9386 in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), mask) 9387 #define HWIO_REO_R2_SW2REO1_RING_HP_OUT(x, val) \ 9388 out_dword( HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), val) 9389 #define HWIO_REO_R2_SW2REO1_RING_HP_OUTM(x, mask, val) \ 9390 do {\ 9391 HWIO_INTLOCK(); \ 9392 out_dword_masked_ns(HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO1_RING_HP_IN(x)); \ 9393 HWIO_INTFREE();\ 9394 } while (0) 9395 9396 #define HWIO_REO_R2_SW2REO1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 9397 #define HWIO_REO_R2_SW2REO1_RING_HP_HEAD_PTR_SHFT 0x0 9398 9399 //// Register REO_R2_SW2REO1_RING_TP //// 9400 9401 #define HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x) (x+0x00003034) 9402 #define HWIO_REO_R2_SW2REO1_RING_TP_PHYS(x) (x+0x00003034) 9403 #define HWIO_REO_R2_SW2REO1_RING_TP_RMSK 0x0000ffff 9404 #define HWIO_REO_R2_SW2REO1_RING_TP_SHFT 0 9405 #define HWIO_REO_R2_SW2REO1_RING_TP_IN(x) \ 9406 in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), HWIO_REO_R2_SW2REO1_RING_TP_RMSK) 9407 #define HWIO_REO_R2_SW2REO1_RING_TP_INM(x, mask) \ 9408 in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), mask) 9409 #define HWIO_REO_R2_SW2REO1_RING_TP_OUT(x, val) \ 9410 out_dword( HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), val) 9411 #define HWIO_REO_R2_SW2REO1_RING_TP_OUTM(x, mask, val) \ 9412 do {\ 9413 HWIO_INTLOCK(); \ 9414 out_dword_masked_ns(HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO1_RING_TP_IN(x)); \ 9415 HWIO_INTFREE();\ 9416 } while (0) 9417 9418 #define HWIO_REO_R2_SW2REO1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 9419 #define HWIO_REO_R2_SW2REO1_RING_TP_TAIL_PTR_SHFT 0x0 9420 9421 //// Register REO_R2_REO2SW1_RING_HP //// 9422 9423 #define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) (x+0x00003038) 9424 #define HWIO_REO_R2_REO2SW1_RING_HP_PHYS(x) (x+0x00003038) 9425 #define HWIO_REO_R2_REO2SW1_RING_HP_RMSK 0x000fffff 9426 #define HWIO_REO_R2_REO2SW1_RING_HP_SHFT 0 9427 #define HWIO_REO_R2_REO2SW1_RING_HP_IN(x) \ 9428 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_HP_RMSK) 9429 #define HWIO_REO_R2_REO2SW1_RING_HP_INM(x, mask) \ 9430 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask) 9431 #define HWIO_REO_R2_REO2SW1_RING_HP_OUT(x, val) \ 9432 out_dword( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), val) 9433 #define HWIO_REO_R2_REO2SW1_RING_HP_OUTM(x, mask, val) \ 9434 do {\ 9435 HWIO_INTLOCK(); \ 9436 out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_HP_IN(x)); \ 9437 HWIO_INTFREE();\ 9438 } while (0) 9439 9440 #define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_BMSK 0x000fffff 9441 #define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_SHFT 0x0 9442 9443 //// Register REO_R2_REO2SW1_RING_TP //// 9444 9445 #define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) (x+0x0000303c) 9446 #define HWIO_REO_R2_REO2SW1_RING_TP_PHYS(x) (x+0x0000303c) 9447 #define HWIO_REO_R2_REO2SW1_RING_TP_RMSK 0x000fffff 9448 #define HWIO_REO_R2_REO2SW1_RING_TP_SHFT 0 9449 #define HWIO_REO_R2_REO2SW1_RING_TP_IN(x) \ 9450 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_TP_RMSK) 9451 #define HWIO_REO_R2_REO2SW1_RING_TP_INM(x, mask) \ 9452 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask) 9453 #define HWIO_REO_R2_REO2SW1_RING_TP_OUT(x, val) \ 9454 out_dword( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), val) 9455 #define HWIO_REO_R2_REO2SW1_RING_TP_OUTM(x, mask, val) \ 9456 do {\ 9457 HWIO_INTLOCK(); \ 9458 out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_TP_IN(x)); \ 9459 HWIO_INTFREE();\ 9460 } while (0) 9461 9462 #define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_BMSK 0x000fffff 9463 #define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_SHFT 0x0 9464 9465 //// Register REO_R2_REO2SW2_RING_HP //// 9466 9467 #define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) (x+0x00003040) 9468 #define HWIO_REO_R2_REO2SW2_RING_HP_PHYS(x) (x+0x00003040) 9469 #define HWIO_REO_R2_REO2SW2_RING_HP_RMSK 0x000fffff 9470 #define HWIO_REO_R2_REO2SW2_RING_HP_SHFT 0 9471 #define HWIO_REO_R2_REO2SW2_RING_HP_IN(x) \ 9472 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_HP_RMSK) 9473 #define HWIO_REO_R2_REO2SW2_RING_HP_INM(x, mask) \ 9474 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask) 9475 #define HWIO_REO_R2_REO2SW2_RING_HP_OUT(x, val) \ 9476 out_dword( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), val) 9477 #define HWIO_REO_R2_REO2SW2_RING_HP_OUTM(x, mask, val) \ 9478 do {\ 9479 HWIO_INTLOCK(); \ 9480 out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_HP_IN(x)); \ 9481 HWIO_INTFREE();\ 9482 } while (0) 9483 9484 #define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_BMSK 0x000fffff 9485 #define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_SHFT 0x0 9486 9487 //// Register REO_R2_REO2SW2_RING_TP //// 9488 9489 #define HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x) (x+0x00003044) 9490 #define HWIO_REO_R2_REO2SW2_RING_TP_PHYS(x) (x+0x00003044) 9491 #define HWIO_REO_R2_REO2SW2_RING_TP_RMSK 0x000fffff 9492 #define HWIO_REO_R2_REO2SW2_RING_TP_SHFT 0 9493 #define HWIO_REO_R2_REO2SW2_RING_TP_IN(x) \ 9494 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_TP_RMSK) 9495 #define HWIO_REO_R2_REO2SW2_RING_TP_INM(x, mask) \ 9496 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask) 9497 #define HWIO_REO_R2_REO2SW2_RING_TP_OUT(x, val) \ 9498 out_dword( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), val) 9499 #define HWIO_REO_R2_REO2SW2_RING_TP_OUTM(x, mask, val) \ 9500 do {\ 9501 HWIO_INTLOCK(); \ 9502 out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_TP_IN(x)); \ 9503 HWIO_INTFREE();\ 9504 } while (0) 9505 9506 #define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_BMSK 0x000fffff 9507 #define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_SHFT 0x0 9508 9509 //// Register REO_R2_REO2SW3_RING_HP //// 9510 9511 #define HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x) (x+0x00003048) 9512 #define HWIO_REO_R2_REO2SW3_RING_HP_PHYS(x) (x+0x00003048) 9513 #define HWIO_REO_R2_REO2SW3_RING_HP_RMSK 0x000fffff 9514 #define HWIO_REO_R2_REO2SW3_RING_HP_SHFT 0 9515 #define HWIO_REO_R2_REO2SW3_RING_HP_IN(x) \ 9516 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_HP_RMSK) 9517 #define HWIO_REO_R2_REO2SW3_RING_HP_INM(x, mask) \ 9518 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask) 9519 #define HWIO_REO_R2_REO2SW3_RING_HP_OUT(x, val) \ 9520 out_dword( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), val) 9521 #define HWIO_REO_R2_REO2SW3_RING_HP_OUTM(x, mask, val) \ 9522 do {\ 9523 HWIO_INTLOCK(); \ 9524 out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_HP_IN(x)); \ 9525 HWIO_INTFREE();\ 9526 } while (0) 9527 9528 #define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_BMSK 0x000fffff 9529 #define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_SHFT 0x0 9530 9531 //// Register REO_R2_REO2SW3_RING_TP //// 9532 9533 #define HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x) (x+0x0000304c) 9534 #define HWIO_REO_R2_REO2SW3_RING_TP_PHYS(x) (x+0x0000304c) 9535 #define HWIO_REO_R2_REO2SW3_RING_TP_RMSK 0x000fffff 9536 #define HWIO_REO_R2_REO2SW3_RING_TP_SHFT 0 9537 #define HWIO_REO_R2_REO2SW3_RING_TP_IN(x) \ 9538 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_TP_RMSK) 9539 #define HWIO_REO_R2_REO2SW3_RING_TP_INM(x, mask) \ 9540 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask) 9541 #define HWIO_REO_R2_REO2SW3_RING_TP_OUT(x, val) \ 9542 out_dword( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), val) 9543 #define HWIO_REO_R2_REO2SW3_RING_TP_OUTM(x, mask, val) \ 9544 do {\ 9545 HWIO_INTLOCK(); \ 9546 out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_TP_IN(x)); \ 9547 HWIO_INTFREE();\ 9548 } while (0) 9549 9550 #define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_BMSK 0x000fffff 9551 #define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_SHFT 0x0 9552 9553 //// Register REO_R2_REO2SW4_RING_HP //// 9554 9555 #define HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x) (x+0x00003050) 9556 #define HWIO_REO_R2_REO2SW4_RING_HP_PHYS(x) (x+0x00003050) 9557 #define HWIO_REO_R2_REO2SW4_RING_HP_RMSK 0x000fffff 9558 #define HWIO_REO_R2_REO2SW4_RING_HP_SHFT 0 9559 #define HWIO_REO_R2_REO2SW4_RING_HP_IN(x) \ 9560 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_HP_RMSK) 9561 #define HWIO_REO_R2_REO2SW4_RING_HP_INM(x, mask) \ 9562 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask) 9563 #define HWIO_REO_R2_REO2SW4_RING_HP_OUT(x, val) \ 9564 out_dword( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), val) 9565 #define HWIO_REO_R2_REO2SW4_RING_HP_OUTM(x, mask, val) \ 9566 do {\ 9567 HWIO_INTLOCK(); \ 9568 out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_HP_IN(x)); \ 9569 HWIO_INTFREE();\ 9570 } while (0) 9571 9572 #define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_BMSK 0x000fffff 9573 #define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_SHFT 0x0 9574 9575 //// Register REO_R2_REO2SW4_RING_TP //// 9576 9577 #define HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x) (x+0x00003054) 9578 #define HWIO_REO_R2_REO2SW4_RING_TP_PHYS(x) (x+0x00003054) 9579 #define HWIO_REO_R2_REO2SW4_RING_TP_RMSK 0x000fffff 9580 #define HWIO_REO_R2_REO2SW4_RING_TP_SHFT 0 9581 #define HWIO_REO_R2_REO2SW4_RING_TP_IN(x) \ 9582 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_TP_RMSK) 9583 #define HWIO_REO_R2_REO2SW4_RING_TP_INM(x, mask) \ 9584 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask) 9585 #define HWIO_REO_R2_REO2SW4_RING_TP_OUT(x, val) \ 9586 out_dword( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), val) 9587 #define HWIO_REO_R2_REO2SW4_RING_TP_OUTM(x, mask, val) \ 9588 do {\ 9589 HWIO_INTLOCK(); \ 9590 out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_TP_IN(x)); \ 9591 HWIO_INTFREE();\ 9592 } while (0) 9593 9594 #define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_BMSK 0x000fffff 9595 #define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_SHFT 0x0 9596 9597 //// Register REO_R2_REO2TCL_RING_HP //// 9598 9599 #define HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x) (x+0x00003058) 9600 #define HWIO_REO_R2_REO2TCL_RING_HP_PHYS(x) (x+0x00003058) 9601 #define HWIO_REO_R2_REO2TCL_RING_HP_RMSK 0x000fffff 9602 #define HWIO_REO_R2_REO2TCL_RING_HP_SHFT 0 9603 #define HWIO_REO_R2_REO2TCL_RING_HP_IN(x) \ 9604 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_HP_RMSK) 9605 #define HWIO_REO_R2_REO2TCL_RING_HP_INM(x, mask) \ 9606 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask) 9607 #define HWIO_REO_R2_REO2TCL_RING_HP_OUT(x, val) \ 9608 out_dword( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), val) 9609 #define HWIO_REO_R2_REO2TCL_RING_HP_OUTM(x, mask, val) \ 9610 do {\ 9611 HWIO_INTLOCK(); \ 9612 out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_HP_IN(x)); \ 9613 HWIO_INTFREE();\ 9614 } while (0) 9615 9616 #define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_BMSK 0x000fffff 9617 #define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_SHFT 0x0 9618 9619 //// Register REO_R2_REO2TCL_RING_TP //// 9620 9621 #define HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x) (x+0x0000305c) 9622 #define HWIO_REO_R2_REO2TCL_RING_TP_PHYS(x) (x+0x0000305c) 9623 #define HWIO_REO_R2_REO2TCL_RING_TP_RMSK 0x000fffff 9624 #define HWIO_REO_R2_REO2TCL_RING_TP_SHFT 0 9625 #define HWIO_REO_R2_REO2TCL_RING_TP_IN(x) \ 9626 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_TP_RMSK) 9627 #define HWIO_REO_R2_REO2TCL_RING_TP_INM(x, mask) \ 9628 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask) 9629 #define HWIO_REO_R2_REO2TCL_RING_TP_OUT(x, val) \ 9630 out_dword( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), val) 9631 #define HWIO_REO_R2_REO2TCL_RING_TP_OUTM(x, mask, val) \ 9632 do {\ 9633 HWIO_INTLOCK(); \ 9634 out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_TP_IN(x)); \ 9635 HWIO_INTFREE();\ 9636 } while (0) 9637 9638 #define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_BMSK 0x000fffff 9639 #define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_SHFT 0x0 9640 9641 //// Register REO_R2_REO2FW_RING_HP //// 9642 9643 #define HWIO_REO_R2_REO2FW_RING_HP_ADDR(x) (x+0x00003060) 9644 #define HWIO_REO_R2_REO2FW_RING_HP_PHYS(x) (x+0x00003060) 9645 #define HWIO_REO_R2_REO2FW_RING_HP_RMSK 0x000fffff 9646 #define HWIO_REO_R2_REO2FW_RING_HP_SHFT 0 9647 #define HWIO_REO_R2_REO2FW_RING_HP_IN(x) \ 9648 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), HWIO_REO_R2_REO2FW_RING_HP_RMSK) 9649 #define HWIO_REO_R2_REO2FW_RING_HP_INM(x, mask) \ 9650 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask) 9651 #define HWIO_REO_R2_REO2FW_RING_HP_OUT(x, val) \ 9652 out_dword( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), val) 9653 #define HWIO_REO_R2_REO2FW_RING_HP_OUTM(x, mask, val) \ 9654 do {\ 9655 HWIO_INTLOCK(); \ 9656 out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_HP_IN(x)); \ 9657 HWIO_INTFREE();\ 9658 } while (0) 9659 9660 #define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_BMSK 0x000fffff 9661 #define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_SHFT 0x0 9662 9663 //// Register REO_R2_REO2FW_RING_TP //// 9664 9665 #define HWIO_REO_R2_REO2FW_RING_TP_ADDR(x) (x+0x00003064) 9666 #define HWIO_REO_R2_REO2FW_RING_TP_PHYS(x) (x+0x00003064) 9667 #define HWIO_REO_R2_REO2FW_RING_TP_RMSK 0x000fffff 9668 #define HWIO_REO_R2_REO2FW_RING_TP_SHFT 0 9669 #define HWIO_REO_R2_REO2FW_RING_TP_IN(x) \ 9670 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), HWIO_REO_R2_REO2FW_RING_TP_RMSK) 9671 #define HWIO_REO_R2_REO2FW_RING_TP_INM(x, mask) \ 9672 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask) 9673 #define HWIO_REO_R2_REO2FW_RING_TP_OUT(x, val) \ 9674 out_dword( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), val) 9675 #define HWIO_REO_R2_REO2FW_RING_TP_OUTM(x, mask, val) \ 9676 do {\ 9677 HWIO_INTLOCK(); \ 9678 out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_TP_IN(x)); \ 9679 HWIO_INTFREE();\ 9680 } while (0) 9681 9682 #define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_BMSK 0x000fffff 9683 #define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_SHFT 0x0 9684 9685 //// Register REO_R2_REO_RELEASE_RING_HP //// 9686 9687 #define HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x) (x+0x00003068) 9688 #define HWIO_REO_R2_REO_RELEASE_RING_HP_PHYS(x) (x+0x00003068) 9689 #define HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK 0x0000ffff 9690 #define HWIO_REO_R2_REO_RELEASE_RING_HP_SHFT 0 9691 #define HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x) \ 9692 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK) 9693 #define HWIO_REO_R2_REO_RELEASE_RING_HP_INM(x, mask) \ 9694 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask) 9695 #define HWIO_REO_R2_REO_RELEASE_RING_HP_OUT(x, val) \ 9696 out_dword( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), val) 9697 #define HWIO_REO_R2_REO_RELEASE_RING_HP_OUTM(x, mask, val) \ 9698 do {\ 9699 HWIO_INTLOCK(); \ 9700 out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x)); \ 9701 HWIO_INTFREE();\ 9702 } while (0) 9703 9704 #define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff 9705 #define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 9706 9707 //// Register REO_R2_REO_RELEASE_RING_TP //// 9708 9709 #define HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x) (x+0x0000306c) 9710 #define HWIO_REO_R2_REO_RELEASE_RING_TP_PHYS(x) (x+0x0000306c) 9711 #define HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK 0x0000ffff 9712 #define HWIO_REO_R2_REO_RELEASE_RING_TP_SHFT 0 9713 #define HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x) \ 9714 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK) 9715 #define HWIO_REO_R2_REO_RELEASE_RING_TP_INM(x, mask) \ 9716 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask) 9717 #define HWIO_REO_R2_REO_RELEASE_RING_TP_OUT(x, val) \ 9718 out_dword( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), val) 9719 #define HWIO_REO_R2_REO_RELEASE_RING_TP_OUTM(x, mask, val) \ 9720 do {\ 9721 HWIO_INTLOCK(); \ 9722 out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x)); \ 9723 HWIO_INTFREE();\ 9724 } while (0) 9725 9726 #define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff 9727 #define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 9728 9729 //// Register REO_R2_REO_STATUS_RING_HP //// 9730 9731 #define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x) (x+0x00003070) 9732 #define HWIO_REO_R2_REO_STATUS_RING_HP_PHYS(x) (x+0x00003070) 9733 #define HWIO_REO_R2_REO_STATUS_RING_HP_RMSK 0x0000ffff 9734 #define HWIO_REO_R2_REO_STATUS_RING_HP_SHFT 0 9735 #define HWIO_REO_R2_REO_STATUS_RING_HP_IN(x) \ 9736 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_HP_RMSK) 9737 #define HWIO_REO_R2_REO_STATUS_RING_HP_INM(x, mask) \ 9738 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask) 9739 #define HWIO_REO_R2_REO_STATUS_RING_HP_OUT(x, val) \ 9740 out_dword( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), val) 9741 #define HWIO_REO_R2_REO_STATUS_RING_HP_OUTM(x, mask, val) \ 9742 do {\ 9743 HWIO_INTLOCK(); \ 9744 out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_HP_IN(x)); \ 9745 HWIO_INTFREE();\ 9746 } while (0) 9747 9748 #define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_BMSK 0x0000ffff 9749 #define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 9750 9751 //// Register REO_R2_REO_STATUS_RING_TP //// 9752 9753 #define HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x) (x+0x00003074) 9754 #define HWIO_REO_R2_REO_STATUS_RING_TP_PHYS(x) (x+0x00003074) 9755 #define HWIO_REO_R2_REO_STATUS_RING_TP_RMSK 0x0000ffff 9756 #define HWIO_REO_R2_REO_STATUS_RING_TP_SHFT 0 9757 #define HWIO_REO_R2_REO_STATUS_RING_TP_IN(x) \ 9758 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_TP_RMSK) 9759 #define HWIO_REO_R2_REO_STATUS_RING_TP_INM(x, mask) \ 9760 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask) 9761 #define HWIO_REO_R2_REO_STATUS_RING_TP_OUT(x, val) \ 9762 out_dword( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), val) 9763 #define HWIO_REO_R2_REO_STATUS_RING_TP_OUTM(x, mask, val) \ 9764 do {\ 9765 HWIO_INTLOCK(); \ 9766 out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_TP_IN(x)); \ 9767 HWIO_INTFREE();\ 9768 } while (0) 9769 9770 #define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_BMSK 0x0000ffff 9771 #define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 9772 9773 9774 #endif 9775 9776