1 /*
2  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef _REO_FLUSH_QUEUE_H_
18 #define _REO_FLUSH_QUEUE_H_
19 #if !defined(__ASSEMBLER__)
20 #endif
21 
22 #include "uniform_reo_cmd_header.h"
23 
24 // ################ START SUMMARY #################
25 //
26 //	Dword	Fields
27 //	0	struct uniform_reo_cmd_header cmd_header;
28 //	1	flush_desc_addr_31_0[31:0]
29 //	2	flush_desc_addr_39_32[7:0], block_desc_addr_usage_after_flush[8], block_resource_index[10:9], invalidate_queue_and_flush[11], reserved_2a[31:12]
30 //	3	reserved_3a[31:0]
31 //	4	reserved_4a[31:0]
32 //	5	reserved_5a[31:0]
33 //	6	reserved_6a[31:0]
34 //	7	reserved_7a[31:0]
35 //	8	reserved_8a[31:0]
36 //
37 // ################ END SUMMARY #################
38 
39 #define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9
40 
41 struct reo_flush_queue {
42     struct            uniform_reo_cmd_header                       cmd_header;
43              uint32_t flush_desc_addr_31_0            : 32; //[31:0]
44              uint32_t flush_desc_addr_39_32           :  8, //[7:0]
45                       block_desc_addr_usage_after_flush:  1, //[8]
46                       block_resource_index            :  2, //[10:9]
47                       invalidate_queue_and_flush      :  1, //[11]
48                       reserved_2a                     : 20; //[31:12]
49              uint32_t reserved_3a                     : 32; //[31:0]
50              uint32_t reserved_4a                     : 32; //[31:0]
51              uint32_t reserved_5a                     : 32; //[31:0]
52              uint32_t reserved_6a                     : 32; //[31:0]
53              uint32_t reserved_7a                     : 32; //[31:0]
54              uint32_t reserved_8a                     : 32; //[31:0]
55 };
56 
57 /*
58 
59 struct uniform_reo_cmd_header cmd_header
60 
61 			Consumer: REO
62 
63 			Producer: SW
64 
65 
66 
67 			Details for command execution tracking purposes.
68 
69 flush_desc_addr_31_0
70 
71 			Consumer: REO
72 
73 			Producer: SW
74 
75 
76 
77 			Address (lower 32 bits) of the descriptor to flush
78 
79 			<legal all>
80 
81 flush_desc_addr_39_32
82 
83 			Consumer: REO
84 
85 			Producer: SW
86 
87 
88 
89 			Address (upper 8 bits) of the descriptor to flush
90 
91 			<legal all>
92 
93 block_desc_addr_usage_after_flush
94 
95 			When set, REO shall not re-fetch this address till SW
96 			explicitly unblocked this address
97 
98 
99 
100 			If the blocking resource was already used, this command
101 			shall fail and an error is reported
102 
103 
104 
105 			<legal all>
106 
107 block_resource_index
108 
109 			Field only valid when 'Block_desc_addr_usage_after_flush
110 			' is set.
111 
112 
113 
114 			Indicates which of the four blocking resources in REO
115 			will be assigned for managing the blocking of this address.
116 
117 			<legal all>
118 
119 invalidate_queue_and_flush
120 
121 			When set, after the queue has been completely flushed,
122 			invalidate the queue by clearing VLD and flush the queue
123 			descriptor from the cache.
124 
125 
126 
127 			<legal all>
128 
129 reserved_2a
130 
131 			<legal 0>
132 
133 reserved_3a
134 
135 			<legal 0>
136 
137 reserved_4a
138 
139 			<legal 0>
140 
141 reserved_5a
142 
143 			<legal 0>
144 
145 reserved_6a
146 
147 			<legal 0>
148 
149 reserved_7a
150 
151 			<legal 0>
152 
153 reserved_8a
154 
155 			<legal 0>
156 */
157 
158 
159  /* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */
160 
161 
162 /* Description		REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER
163 
164 			Consumer: REO/SW/DEBUG
165 
166 			Producer: SW
167 
168 
169 
170 			This number can be used by SW to track, identify and
171 			link the created commands with the command statusses
172 
173 
174 
175 
176 
177 			<legal all>
178 */
179 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET           0x00000000
180 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_LSB              0
181 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_MASK             0x0000ffff
182 
183 /* Description		REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED
184 
185 			Consumer: REO
186 
187 			Producer: SW
188 
189 
190 
191 			<enum 0 NoStatus> REO does not need to generate a status
192 			TLV for the execution of this command
193 
194 			<enum 1 StatusRequired> REO shall generate a status TLV
195 			for the execution of this command
196 
197 
198 
199 			<legal all>
200 */
201 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET      0x00000000
202 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB         16
203 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK        0x00010000
204 
205 /* Description		REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A
206 
207 			<legal 0>
208 */
209 #define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_OFFSET              0x00000000
210 #define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_LSB                 17
211 #define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_MASK                0xfffe0000
212 
213 /* Description		REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0
214 
215 			Consumer: REO
216 
217 			Producer: SW
218 
219 
220 
221 			Address (lower 32 bits) of the descriptor to flush
222 
223 			<legal all>
224 */
225 #define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_OFFSET                0x00000004
226 #define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_LSB                   0
227 #define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_MASK                  0xffffffff
228 
229 /* Description		REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32
230 
231 			Consumer: REO
232 
233 			Producer: SW
234 
235 
236 
237 			Address (upper 8 bits) of the descriptor to flush
238 
239 			<legal all>
240 */
241 #define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_OFFSET               0x00000008
242 #define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_LSB                  0
243 #define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_MASK                 0x000000ff
244 
245 /* Description		REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH
246 
247 			When set, REO shall not re-fetch this address till SW
248 			explicitly unblocked this address
249 
250 
251 
252 			If the blocking resource was already used, this command
253 			shall fail and an error is reported
254 
255 
256 
257 			<legal all>
258 */
259 #define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET   0x00000008
260 #define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB      8
261 #define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK     0x00000100
262 
263 /* Description		REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX
264 
265 			Field only valid when 'Block_desc_addr_usage_after_flush
266 			' is set.
267 
268 
269 
270 			Indicates which of the four blocking resources in REO
271 			will be assigned for managing the blocking of this address.
272 
273 			<legal all>
274 */
275 #define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_OFFSET                0x00000008
276 #define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_LSB                   9
277 #define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_MASK                  0x00000600
278 
279 /* Description		REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH
280 
281 			When set, after the queue has been completely flushed,
282 			invalidate the queue by clearing VLD and flush the queue
283 			descriptor from the cache.
284 
285 
286 
287 			<legal all>
288 */
289 #define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_OFFSET          0x00000008
290 #define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_LSB             11
291 #define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_MASK            0x00000800
292 
293 /* Description		REO_FLUSH_QUEUE_2_RESERVED_2A
294 
295 			<legal 0>
296 */
297 #define REO_FLUSH_QUEUE_2_RESERVED_2A_OFFSET                         0x00000008
298 #define REO_FLUSH_QUEUE_2_RESERVED_2A_LSB                            12
299 #define REO_FLUSH_QUEUE_2_RESERVED_2A_MASK                           0xfffff000
300 
301 /* Description		REO_FLUSH_QUEUE_3_RESERVED_3A
302 
303 			<legal 0>
304 */
305 #define REO_FLUSH_QUEUE_3_RESERVED_3A_OFFSET                         0x0000000c
306 #define REO_FLUSH_QUEUE_3_RESERVED_3A_LSB                            0
307 #define REO_FLUSH_QUEUE_3_RESERVED_3A_MASK                           0xffffffff
308 
309 /* Description		REO_FLUSH_QUEUE_4_RESERVED_4A
310 
311 			<legal 0>
312 */
313 #define REO_FLUSH_QUEUE_4_RESERVED_4A_OFFSET                         0x00000010
314 #define REO_FLUSH_QUEUE_4_RESERVED_4A_LSB                            0
315 #define REO_FLUSH_QUEUE_4_RESERVED_4A_MASK                           0xffffffff
316 
317 /* Description		REO_FLUSH_QUEUE_5_RESERVED_5A
318 
319 			<legal 0>
320 */
321 #define REO_FLUSH_QUEUE_5_RESERVED_5A_OFFSET                         0x00000014
322 #define REO_FLUSH_QUEUE_5_RESERVED_5A_LSB                            0
323 #define REO_FLUSH_QUEUE_5_RESERVED_5A_MASK                           0xffffffff
324 
325 /* Description		REO_FLUSH_QUEUE_6_RESERVED_6A
326 
327 			<legal 0>
328 */
329 #define REO_FLUSH_QUEUE_6_RESERVED_6A_OFFSET                         0x00000018
330 #define REO_FLUSH_QUEUE_6_RESERVED_6A_LSB                            0
331 #define REO_FLUSH_QUEUE_6_RESERVED_6A_MASK                           0xffffffff
332 
333 /* Description		REO_FLUSH_QUEUE_7_RESERVED_7A
334 
335 			<legal 0>
336 */
337 #define REO_FLUSH_QUEUE_7_RESERVED_7A_OFFSET                         0x0000001c
338 #define REO_FLUSH_QUEUE_7_RESERVED_7A_LSB                            0
339 #define REO_FLUSH_QUEUE_7_RESERVED_7A_MASK                           0xffffffff
340 
341 /* Description		REO_FLUSH_QUEUE_8_RESERVED_8A
342 
343 			<legal 0>
344 */
345 #define REO_FLUSH_QUEUE_8_RESERVED_8A_OFFSET                         0x00000020
346 #define REO_FLUSH_QUEUE_8_RESERVED_8A_LSB                            0
347 #define REO_FLUSH_QUEUE_8_RESERVED_8A_MASK                           0xffffffff
348 
349 
350 #endif // _REO_FLUSH_QUEUE_H_
351