1 /* 2 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _PHYRX_PKT_END_H_ 18 #define _PHYRX_PKT_END_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "phyrx_pkt_end_info.h" 23 24 // ################ START SUMMARY ################# 25 // 26 // Dword Fields 27 // 0-32 struct phyrx_pkt_end_info rx_pkt_end_details; 28 // 29 // ################ END SUMMARY ################# 30 31 #define NUM_OF_DWORDS_PHYRX_PKT_END 33 32 33 struct phyrx_pkt_end { 34 struct phyrx_pkt_end_info rx_pkt_end_details; 35 }; 36 37 /* 38 39 struct phyrx_pkt_end_info rx_pkt_end_details 40 41 Overview of the final receive related parameters from 42 the PHY RX 43 */ 44 45 46 /* EXTERNAL REFERENCE : struct phyrx_pkt_end_info rx_pkt_end_details */ 47 48 49 /* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP 50 51 When set, PHY RX entered an internal NAP state, as PHY 52 determined that this reception was not destined to this 53 device 54 */ 55 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_OFFSET 0x00000000 56 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_LSB 0 57 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_MASK 0x00000001 58 59 /* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID 60 61 Indicates that the RX_LOCATION_INFO structure later on 62 in the TLV contains valid info 63 */ 64 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x00000000 65 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1 66 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x00000002 67 68 /* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID 69 70 Indicates that the RX_TIMING_OFFSET_INFO structure later 71 on in the TLV contains valid info 72 */ 73 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x00000000 74 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2 75 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x00000004 76 77 /* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID 78 79 Indicates that the RECEIVE_RSSI_INFO structure later on 80 in the TLV contains valid info 81 */ 82 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x00000000 83 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3 84 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x00000008 85 86 /* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED 87 88 When clear, no action is needed in the MAC. 89 90 91 92 When set, the falling edge of the rx_frame happened 4us 93 too late. MAC will need to compensate for this delay in 94 order to maintain proper SIFS timing and/or not to get 95 de-slotted. 96 97 98 99 PHY uses this for very short 11a frames. 100 101 102 103 When set, PHY will have passed this TLV to the MAC up to 104 8 us into the 'real SIFS' time, and thus within 4us from the 105 falling edge of the rx_frame. 106 107 108 109 <legal all> 110 */ 111 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000 112 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_LSB 4 113 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010 114 115 /* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED 116 117 When set, PHY has received the 'frameless frame' . Can 118 be used in the 'MU-RTS -CTS exchange where CTS reception can 119 be problematic. 120 121 <legal all> 122 */ 123 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 124 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5 125 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 126 127 /* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A 128 129 <legal 0> 130 */ 131 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x00000000 132 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_LSB 6 133 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x00000fc0 134 135 /* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID 136 137 When set, the following DL_ofdma_... fields are valid. 138 139 It provides the MAC insight into which RU was allocated 140 to this device. 141 142 <legal all> 143 */ 144 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_OFFSET 0x00000000 145 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_LSB 12 146 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_MASK 0x00001000 147 148 /* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX 149 150 RU index number to which User is assigned 151 152 RU numbering is over the entire BW, starting from 0 and 153 in increasing frequency order and not primary-secondary 154 order 155 156 <legal 0-73> 157 */ 158 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000000 159 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_LSB 13 160 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_MASK 0x000fe000 161 162 /* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH 163 164 The size of the RU for this user. 165 166 In units of 1 (26 tone) RU 167 168 <legal 1-74> 169 */ 170 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_OFFSET 0x00000000 171 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_LSB 20 172 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_MASK 0x07f00000 173 174 /* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B 175 176 <legal 0> 177 */ 178 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x00000000 179 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_LSB 27 180 #define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0xf8000000 181 182 /* Description PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32 183 184 TODO PHY: cleanup descriptionThe PHY timestamp in the 185 AMPI of the first rising edge of rx_clear_pri after 186 TX_PHY_DESC. . This field should set to 0 by the PHY and 187 should be updated by the AMPI before being forwarded to the 188 rest of the MAC. This field indicates the lower 32 bits of 189 the timestamp 190 */ 191 #define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 192 #define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0 193 #define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff 194 195 /* Description PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32 196 197 TODO PHY: cleanup description 198 199 The PHY timestamp in the AMPI of the first rising edge 200 of rx_clear_pri after TX_PHY_DESC. This field should set to 201 0 by the PHY and should be updated by the AMPI before being 202 forwarded to the rest of the MAC. This field indicates the 203 upper 32 bits of the timestamp 204 */ 205 #define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 206 #define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 207 #define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff 208 209 /* Description PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32 210 211 TODO PHY: cleanup description 212 213 The PHY timestamp in the AMPI of the rising edge of 214 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 215 0 by the PHY and should be updated by the AMPI before being 216 forwarded to the rest of the MAC. This field indicates the 217 lower 32 bits of the timestamp 218 */ 219 #define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c 220 #define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0 221 #define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff 222 223 /* Description PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32 224 225 TODO PHY: cleanup description 226 227 The PHY timestamp in the AMPI of the rising edge of 228 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 229 0 by the PHY and should be updated by the AMPI before being 230 forwarded to the rest of the MAC. This field indicates the 231 upper 32 bits of the timestamp 232 */ 233 #define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 234 #define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 235 #define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff 236 237 /* EXTERNAL REFERENCE : struct rx_location_info rx_location_info_details */ 238 239 240 /* Description PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY 241 242 For 20/40/80, this field shows the RTT first arrival 243 correction value computed from L-LTF on the first selected 244 Rx chain 245 246 247 248 For 80+80, this field shows the RTT first arrival 249 correction value computed from L-LTF on pri80 on the 250 selected pri80 Rx chain 251 252 253 254 16 bits, signed 12.4. 12 bits integer to cover -6.4us to 255 6.4us, and 4 bits fraction to cover pri80 and 32x FAC 256 interpolation 257 258 259 260 clock unit is 320MHz 261 262 <legal all> 263 */ 264 #define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_OFFSET 0x00000014 265 #define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_LSB 0 266 #define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_MASK 0x0000ffff 267 268 /* Description PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80 269 270 For 20/40/80, this field shows the RTT first arrival 271 correction value computed from L-LTF on the second selected 272 Rx chain 273 274 275 276 For 80+80, this field shows the RTT first arrival 277 correction value computed from L-LTF on ext80 on the 278 selected ext80 Rx chain 279 280 281 282 16 bits, signed 12.4. 12 bits integer to cover -6.4us to 283 6.4us, and 4 bits fraction to cover ext80 and 32x FAC 284 interpolation 285 286 287 288 clock unit is 320MHz 289 290 <legal all> 291 */ 292 #define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000014 293 #define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_LSB 16 294 #define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000 295 296 /* Description PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT 297 298 For 20/40/80, this field shows the RTT first arrival 299 correction value computed from (V)HT/HE-LTF on the first 300 selected Rx chain 301 302 303 304 For 80+80, this field shows the RTT first arrival 305 correction value computed from (V)HT/HE-LTF on pri80 on the 306 selected pri80 Rx chain 307 308 309 310 16 bits, signed 12.4. 12 bits integer to cover -6.4us to 311 6.4us, and 4 bits fraction to cover pri80 and 32x FAC 312 interpolation 313 314 315 316 clock unit is 320MHz 317 318 <legal all> 319 */ 320 #define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_OFFSET 0x00000018 321 #define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_LSB 0 322 #define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_MASK 0x0000ffff 323 324 /* Description PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80 325 326 For 20/40/80, this field shows the RTT first arrival 327 correction value computed from (V)HT/HE-LTF on the second 328 selected Rx chain 329 330 331 332 For 80+80, this field shows the RTT first arrival 333 correction value computed from (V)HT/HE-LTF on ext80 on the 334 selected ext80 Rx chain 335 336 337 338 16 bits, signed 12.4. 12 bits integer to cover -6.4us to 339 6.4us, and 4 bits fraction to cover ext80 and 32x FAC 340 interpolation 341 342 343 344 clock unit is 320MHz 345 346 <legal all> 347 */ 348 #define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_OFFSET 0x00000018 349 #define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_LSB 16 350 #define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_MASK 0xffff0000 351 352 /* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS 353 354 Status of rtt_fac_legacy 355 356 357 358 <enum 0 location_fac_legacy_status_not_valid> 359 360 <enum 1 location_fac_legacy_status_valid> 361 362 <legal all> 363 */ 364 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_OFFSET 0x0000001c 365 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_LSB 0 366 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_MASK 0x00000001 367 368 /* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS 369 370 Status of rtt_fac_legacy_ext80 371 372 373 374 <enum 0 location_fac_legacy_ext80_status_not_valid> 375 376 <enum 1 location_fac_legacy_ext80_status_valid> 377 378 <legal all> 379 */ 380 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x0000001c 381 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1 382 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002 383 384 /* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS 385 386 Status of rtt_fac_vht 387 388 389 390 <enum 0 location_fac_vht_status_not_valid> 391 392 <enum 1 location_fac_vht_status_valid> 393 394 <legal all> 395 */ 396 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_OFFSET 0x0000001c 397 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_LSB 2 398 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_MASK 0x00000004 399 400 /* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS 401 402 Status of rtt_fac_vht_ext80 403 404 405 406 <enum 0 location_fac_vht_ext80_status_not_valid> 407 408 <enum 1 location_fac_vht_ext80_status_valid> 409 410 <legal all> 411 */ 412 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x0000001c 413 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_LSB 3 414 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008 415 416 /* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS 417 418 To support fine SIFS adjustment, need to provide FAC 419 value @ integer number of 320 MHz clock cycles to MAC. It 420 is from L-LTF if it is a Legacy packet and from (V)HT/HE-LTF 421 if it is a (V)HT/HE packet 422 423 424 425 12 bits, signed, no fractional part 426 427 <legal all> 428 */ 429 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_OFFSET 0x0000001c 430 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_LSB 4 431 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_MASK 0x0000fff0 432 433 /* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS 434 435 Status of rtt_fac_sifs 436 437 0: not valid 438 439 1: valid and from L-LTF 440 441 2: valid and from (V)HT/HE-LTF 442 443 3: reserved 444 445 <legal 0-2> 446 */ 447 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_OFFSET 0x0000001c 448 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_LSB 16 449 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_MASK 0x00030000 450 451 /* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS 452 453 Status of channel frequency response dump 454 455 456 457 <enum 0 location_CFR_dump_not_valid> 458 459 <enum 1 location_CFR_dump_valid> 460 461 <legal all> 462 */ 463 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000001c 464 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 18 465 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00040000 466 467 /* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS 468 469 Status of channel impulse response dump 470 471 472 473 <enum 0 location_CIR_dump_not_valid> 474 475 <enum 1 location_CIR_dump_valid> 476 477 <legal all> 478 */ 479 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000001c 480 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 19 481 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0x00080000 482 483 /* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE 484 485 Channel dump size. It shows how many tones in CFR in 486 one chain, for example, it will show 52 for Legacy20 and 484 487 for VHT160 488 489 490 491 <legal all> 492 */ 493 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x0000001c 494 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_LSB 20 495 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000 496 497 /* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE 498 499 Indicator showing if HW IFFT mode or SW IFFT mode 500 501 502 503 <enum 0 location_sw_ifft_mode> 504 505 <enum 1 location_hw_ifft_mode> 506 507 <legal all> 508 */ 509 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000001c 510 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 31 511 #define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x80000000 512 513 /* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS 514 515 Indicate if BTCF is used to capture the timestamps 516 517 518 519 <enum 0 location_not_BTCF_based_ts> 520 521 <enum 1 location_BTCF_based_ts> 522 523 <legal all> 524 */ 525 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_OFFSET 0x00000020 526 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_LSB 0 527 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_MASK 0x00000001 528 529 /* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE 530 531 Indicate preamble type 532 533 534 535 <enum 0 location_preamble_type_legacy> 536 537 <enum 1 location_preamble_type_ht> 538 539 <enum 2 location_preamble_type_vht> 540 541 <enum 3 location_preamble_type_he_su_4xltf> 542 543 <enum 4 location_preamble_type_he_su_2xltf> 544 545 <enum 5 location_preamble_type_he_su_1xltf> 546 547 <enum 6 548 location_preamble_type_he_trigger_based_ul_4xltf> 549 550 <enum 7 551 location_preamble_type_he_trigger_based_ul_2xltf> 552 553 <enum 8 554 location_preamble_type_he_trigger_based_ul_1xltf> 555 556 <enum 9 location_preamble_type_he_mu_4xltf> 557 558 <enum 10 location_preamble_type_he_mu_2xltf> 559 560 <enum 11 location_preamble_type_he_mu_1xltf> 561 562 <enum 12 563 location_preamble_type_he_extended_range_su_4xltf> 564 565 <enum 13 566 location_preamble_type_he_extended_range_su_2xltf> 567 568 <enum 14 569 location_preamble_type_he_extended_range_su_1xltf> 570 571 <legal 0-14> 572 */ 573 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000020 574 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 1 575 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000003e 576 577 /* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG 578 579 Indicate the bandwidth of L-LTF 580 581 582 583 <enum 0 location_pkt_bw_20MHz> 584 585 <enum 1 location_pkt_bw_40MHz> 586 587 <enum 2 location_pkt_bw_80MHz> 588 589 <enum 3 location_pkt_bw_160MHz> 590 591 <legal all> 592 */ 593 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x00000020 594 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 6 595 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x000000c0 596 597 /* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT 598 599 Indicate the bandwidth of (V)HT/HE-LTF 600 601 602 603 <enum 0 location_pkt_bw_20MHz> 604 605 <enum 1 location_pkt_bw_40MHz> 606 607 <enum 2 location_pkt_bw_80MHz> 608 609 <enum 3 location_pkt_bw_160MHz> 610 611 <legal all> 612 */ 613 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x00000020 614 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 8 615 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x00000300 616 617 /* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE 618 619 Indicate GI (guard interval) type 620 621 622 623 <enum 0 gi_0_8_us > HE related GI. Can also be used 624 for HE 625 626 <enum 1 gi_0_4_us > HE related GI. Can also be used 627 for HE 628 629 <enum 2 gi_1_6_us > HE related GI 630 631 <enum 3 gi_3_2_us > HE related GI 632 633 <legal 0 - 3> 634 */ 635 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000020 636 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 10 637 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000c00 638 639 /* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE 640 641 Bits 0~4 indicate MCS rate, if Legacy, 642 643 0: 48 Mbps, 644 645 1: 24 Mbps, 646 647 2: 12 Mbps, 648 649 3: 6 Mbps, 650 651 4: 54 Mbps, 652 653 5: 36 Mbps, 654 655 6: 18 Mbps, 656 657 7: 9 Mbps, 658 659 660 661 if HT, 0-7: MCS0-MCS7, 662 663 if VHT, 0-9: MCS0-MCS9, 664 665 666 <legal all> 667 */ 668 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x00000020 669 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 12 670 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0x0001f000 671 672 /* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN 673 674 For 20/40/80, this field shows the first selected Rx 675 chain that is used in HW IFFT mode 676 677 678 679 For 80+80, this field shows the selected pri80 Rx chain 680 that is used in HW IFFT mode 681 682 683 684 <enum 0 location_strongest_chain_is_0> 685 686 <enum 1 location_strongest_chain_is_1> 687 688 <enum 2 location_strongest_chain_is_2> 689 690 <enum 3 location_strongest_chain_is_3> 691 692 <enum 4 location_strongest_chain_is_4> 693 694 <enum 5 location_strongest_chain_is_5> 695 696 <enum 6 location_strongest_chain_is_6> 697 698 <enum 7 location_strongest_chain_is_7> 699 700 <legal all> 701 */ 702 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_OFFSET 0x00000020 703 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_LSB 17 704 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_MASK 0x000e0000 705 706 /* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80 707 708 For 20/40/80, this field shows the second selected Rx 709 chain that is used in HW IFFT mode 710 711 712 713 For 80+80, this field shows the selected ext80 Rx chain 714 that is used in HW IFFT mode 715 716 717 718 <enum 0 location_strongest_chain_is_0> 719 720 <enum 1 location_strongest_chain_is_1> 721 722 <enum 2 location_strongest_chain_is_2> 723 724 <enum 3 location_strongest_chain_is_3> 725 726 <enum 4 location_strongest_chain_is_4> 727 728 <enum 5 location_strongest_chain_is_5> 729 730 <enum 6 location_strongest_chain_is_6> 731 732 <enum 7 location_strongest_chain_is_7> 733 734 <legal all> 735 */ 736 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x00000020 737 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_LSB 20 738 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000 739 740 /* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK 741 742 Rx chain mask, each bit is a Rx chain 743 744 0: the Rx chain is not used 745 746 1: the Rx chain is used 747 748 Support up to 8 Rx chains 749 750 <legal all> 751 */ 752 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000020 753 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 23 754 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x7f800000 755 756 /* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3 757 758 <legal 0> 759 */ 760 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x00000020 761 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 31 762 #define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x80000000 763 764 /* Description PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS 765 766 RX packet start timestamp 767 768 769 770 It reports the time the first L-STF ADC sample arrived 771 at RX antenna 772 773 774 775 clock unit is 480MHz 776 777 <legal all> 778 */ 779 #define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000024 780 #define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0 781 #define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff 782 783 /* Description PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS 784 785 RX packet end timestamp 786 787 788 789 It reports the time the last symbol's last ADC sample 790 arrived at RX antenna 791 792 793 794 clock unit is 480MHz 795 796 <legal all> 797 */ 798 #define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x00000028 799 #define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0 800 #define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff 801 802 /* Description PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START 803 804 The phase of the SFO of the first symbol's first FFT 805 input sample 806 807 808 809 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to 810 66.7ns, and 6 bits fraction to provide a resolution of 811 0.03ns 812 813 814 815 clock unit is 480MHz 816 817 <legal all> 818 */ 819 #define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_OFFSET 0x0000002c 820 #define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_LSB 0 821 #define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_MASK 0x00000fff 822 823 /* Description PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END 824 825 The phase of the SFO of the last symbol's last FFT input 826 sample 827 828 829 830 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to 831 66.7ns, and 6 bits fraction to provide a resolution of 832 0.03ns 833 834 835 836 clock unit is 480MHz 837 838 <legal all> 839 */ 840 #define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_OFFSET 0x0000002c 841 #define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_LSB 12 842 #define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_MASK 0x00fff000 843 844 /* Description PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8 845 846 The high 8 bits of the 40 bits pointer pointed to the 847 external RTT channel information buffer 848 849 850 851 8 bits 852 853 <legal all> 854 */ 855 #define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000002c 856 #define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24 857 #define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000 858 859 /* Description PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32 860 861 The low 32 bits of the 40 bits pointer pointed to the 862 external RTT channel information buffer 863 864 865 866 32 bits 867 868 <legal all> 869 */ 870 #define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000030 871 #define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 872 #define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff 873 874 /* Description PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT 875 876 CFO measurement. Needed for passive locationing 877 878 879 880 14 bits, signed 1.13. 13 bits fraction to provide a 881 resolution of 153 Hz 882 883 884 885 In units of cycles/800 ns 886 887 <legal all> 888 */ 889 #define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000034 890 #define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 891 #define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x00003fff 892 893 /* Description PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD 894 895 Channel delay spread measurement. Needed for selecting 896 GI length 897 898 899 900 8 bits, unsigned. At 25 ns step. Can represent up to 901 6375 ns 902 903 904 905 In units of cycles @ 40 MHz 906 907 <legal all> 908 */ 909 #define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_OFFSET 0x00000034 910 #define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_LSB 14 911 #define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_MASK 0x003fc000 912 913 /* Description PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL 914 915 Indicate which timing backoff value is used 916 917 918 919 <enum 0 timing_backoff_low_rssi> 920 921 <enum 1 timing_backoff_mid_rssi> 922 923 <enum 2 timing_backoff_high_rssi> 924 925 <enum 3 reserved> 926 927 <legal all> 928 */ 929 #define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000034 930 #define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 22 931 #define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000 932 933 /* Description PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8 934 935 <legal 0> 936 */ 937 #define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_OFFSET 0x00000034 938 #define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_LSB 24 939 #define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_MASK 0x7f000000 940 941 /* Description PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID 942 943 <enum 0 rx_location_info_is_not_valid> 944 945 <enum 1 rx_location_info_is_valid> 946 947 <legal all> 948 */ 949 #define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000034 950 #define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 31 951 #define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x80000000 952 953 /* EXTERNAL REFERENCE : struct rx_timing_offset_info rx_timing_offset_info_details */ 954 955 956 /* Description PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET 957 958 Cumulative reference frequency error at end of RX 959 960 <legal all> 961 */ 962 #define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000038 963 #define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 964 #define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff 965 966 /* Description PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED 967 968 <legal 0> 969 */ 970 #define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000038 971 #define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12 972 #define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000 973 974 /* EXTERNAL REFERENCE : struct receive_rssi_info post_rssi_info_details */ 975 976 977 /* Description PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0 978 979 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 980 981 Value of 0x80 indicates invalid. 982 */ 983 #define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000003c 984 #define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 985 #define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff 986 987 /* Description PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0 988 989 RSSI of RX PPDU on chain 0 of extension 20 MHz 990 bandwidth. 991 992 Value of 0x80 indicates invalid. 993 */ 994 #define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000003c 995 #define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 996 #define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 997 998 /* Description PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0 999 1000 RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz 1001 bandwidth. 1002 1003 Value of 0x80 indicates invalid. 1004 */ 1005 #define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000003c 1006 #define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 1007 #define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 1008 1009 /* Description PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0 1010 1011 RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz 1012 bandwidth. 1013 1014 Value of 0x80 indicates invalid. 1015 */ 1016 #define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000003c 1017 #define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 1018 #define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 1019 1020 /* Description PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0 1021 1022 RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz 1023 bandwidth. 1024 1025 Value of 0x80 indicates invalid. 1026 */ 1027 #define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000040 1028 #define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 1029 #define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff 1030 1031 /* Description PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0 1032 1033 RSSI of RX PPDU on chain 0 of extension 80, low-high 20 1034 MHz bandwidth. 1035 1036 Value of 0x80 indicates invalid. 1037 */ 1038 #define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000040 1039 #define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 1040 #define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 1041 1042 /* Description PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0 1043 1044 RSSI of RX PPDU on chain 0 of extension 80, high-low 20 1045 MHz bandwidth. 1046 1047 Value of 0x80 indicates invalid. 1048 */ 1049 #define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000040 1050 #define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 1051 #define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 1052 1053 /* Description PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0 1054 1055 RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz 1056 bandwidth. 1057 1058 Value of 0x80 indicates invalid. 1059 */ 1060 #define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000040 1061 #define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 1062 #define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 1063 1064 /* Description PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1 1065 1066 RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. 1067 1068 Value of 0x80 indicates invalid. 1069 */ 1070 #define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000044 1071 #define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 1072 #define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff 1073 1074 /* Description PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1 1075 1076 RSSI of RX PPDU on chain 1 of extension 20 MHz 1077 bandwidth. 1078 1079 Value of 0x80 indicates invalid. 1080 */ 1081 #define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000044 1082 #define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 1083 #define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 1084 1085 /* Description PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1 1086 1087 RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz 1088 bandwidth. 1089 1090 Value of 0x80 indicates invalid. 1091 */ 1092 #define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000044 1093 #define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 1094 #define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 1095 1096 /* Description PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1 1097 1098 RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz 1099 bandwidth. 1100 1101 Value of 0x80 indicates invalid. 1102 */ 1103 #define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000044 1104 #define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 1105 #define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 1106 1107 /* Description PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1 1108 1109 RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz 1110 bandwidth. 1111 1112 Value of 0x80 indicates invalid. 1113 */ 1114 #define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000048 1115 #define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 1116 #define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff 1117 1118 /* Description PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1 1119 1120 RSSI of RX PPDU on chain 1 of extension 80, low-high 20 1121 MHz bandwidth. 1122 1123 Value of 0x80 indicates invalid. 1124 */ 1125 #define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000048 1126 #define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 1127 #define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 1128 1129 /* Description PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1 1130 1131 RSSI of RX PPDU on chain 1 of extension 80, high-low 20 1132 MHz bandwidth. 1133 1134 Value of 0x80 indicates invalid. 1135 */ 1136 #define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000048 1137 #define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 1138 #define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 1139 1140 /* Description PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1 1141 1142 RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz 1143 bandwidth. 1144 1145 Value of 0x80 indicates invalid. 1146 */ 1147 #define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000048 1148 #define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 1149 #define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 1150 1151 /* Description PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2 1152 1153 RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. 1154 1155 Value of 0x80 indicates invalid. 1156 */ 1157 #define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000004c 1158 #define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 1159 #define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff 1160 1161 /* Description PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2 1162 1163 RSSI of RX PPDU on chain 2 of extension 20 MHz 1164 bandwidth. 1165 1166 Value of 0x80 indicates invalid. 1167 */ 1168 #define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000004c 1169 #define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 1170 #define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 1171 1172 /* Description PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2 1173 1174 RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz 1175 bandwidth. 1176 1177 Value of 0x80 indicates invalid. 1178 */ 1179 #define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000004c 1180 #define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 1181 #define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 1182 1183 /* Description PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2 1184 1185 RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz 1186 bandwidth. 1187 1188 Value of 0x80 indicates invalid. 1189 */ 1190 #define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000004c 1191 #define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 1192 #define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 1193 1194 /* Description PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2 1195 1196 RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz 1197 bandwidth. 1198 1199 Value of 0x80 indicates invalid. 1200 */ 1201 #define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000050 1202 #define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 1203 #define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff 1204 1205 /* Description PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2 1206 1207 RSSI of RX PPDU on chain 2 of extension 80, low-high 20 1208 MHz bandwidth. 1209 1210 Value of 0x80 indicates invalid. 1211 */ 1212 #define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000050 1213 #define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 1214 #define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 1215 1216 /* Description PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2 1217 1218 RSSI of RX PPDU on chain 2 of extension 80, high-low 20 1219 MHz bandwidth. 1220 1221 Value of 0x80 indicates invalid. 1222 */ 1223 #define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000050 1224 #define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 1225 #define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 1226 1227 /* Description PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2 1228 1229 RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz 1230 bandwidth. 1231 1232 Value of 0x80 indicates invalid. 1233 */ 1234 #define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000050 1235 #define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 1236 #define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 1237 1238 /* Description PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3 1239 1240 RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. 1241 1242 Value of 0x80 indicates invalid. 1243 */ 1244 #define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000054 1245 #define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 1246 #define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff 1247 1248 /* Description PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3 1249 1250 RSSI of RX PPDU on chain 3 of extension 20 MHz 1251 bandwidth. 1252 1253 Value of 0x80 indicates invalid. 1254 */ 1255 #define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000054 1256 #define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 1257 #define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 1258 1259 /* Description PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3 1260 1261 RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz 1262 bandwidth. 1263 1264 Value of 0x80 indicates invalid. 1265 */ 1266 #define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000054 1267 #define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 1268 #define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 1269 1270 /* Description PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3 1271 1272 RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz 1273 bandwidth. 1274 1275 Value of 0x80 indicates invalid. 1276 */ 1277 #define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000054 1278 #define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 1279 #define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 1280 1281 /* Description PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3 1282 1283 RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz 1284 bandwidth. 1285 1286 Value of 0x80 indicates invalid. 1287 */ 1288 #define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000058 1289 #define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 1290 #define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff 1291 1292 /* Description PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3 1293 1294 RSSI of RX PPDU on chain 3 of extension 80, low-high 20 1295 MHz bandwidth. 1296 1297 Value of 0x80 indicates invalid. 1298 */ 1299 #define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000058 1300 #define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 1301 #define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 1302 1303 /* Description PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3 1304 1305 RSSI of RX PPDU on chain 3 of extension 80, high-low 20 1306 MHz bandwidth. 1307 1308 Value of 0x80 indicates invalid. 1309 */ 1310 #define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000058 1311 #define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 1312 #define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 1313 1314 /* Description PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3 1315 1316 RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz 1317 bandwidth. 1318 1319 Value of 0x80 indicates invalid. 1320 */ 1321 #define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000058 1322 #define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 1323 #define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 1324 1325 /* Description PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4 1326 1327 RSSI of RX PPDU on chain 4 of primary 20 MHz bandwidth. 1328 1329 Value of 0x80 indicates invalid. 1330 */ 1331 #define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000005c 1332 #define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 1333 #define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff 1334 1335 /* Description PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4 1336 1337 RSSI of RX PPDU on chain 4 of extension 20 MHz 1338 bandwidth. 1339 1340 Value of 0x80 indicates invalid. 1341 */ 1342 #define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000005c 1343 #define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 1344 #define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 1345 1346 /* Description PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4 1347 1348 RSSI of RX PPDU on chain 4 of extension 40, low 20 MHz 1349 bandwidth. 1350 1351 Value of 0x80 indicates invalid. 1352 */ 1353 #define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000005c 1354 #define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 1355 #define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 1356 1357 /* Description PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4 1358 1359 RSSI of RX PPDU on chain 4 of extension 40, high 20 MHz 1360 bandwidth. 1361 1362 Value of 0x80 indicates invalid. 1363 */ 1364 #define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000005c 1365 #define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 1366 #define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 1367 1368 /* Description PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4 1369 1370 RSSI of RX PPDU on chain 4 of extension 80, low 20 MHz 1371 bandwidth. 1372 1373 Value of 0x80 indicates invalid. 1374 */ 1375 #define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000060 1376 #define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 1377 #define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff 1378 1379 /* Description PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4 1380 1381 RSSI of RX PPDU on chain 4 of extension 80, low-high 20 1382 MHz bandwidth. 1383 1384 Value of 0x80 indicates invalid. 1385 */ 1386 #define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000060 1387 #define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 1388 #define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 1389 1390 /* Description PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4 1391 1392 RSSI of RX PPDU on chain 4 of extension 80, high-low 20 1393 MHz bandwidth. 1394 1395 Value of 0x80 indicates invalid. 1396 */ 1397 #define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000060 1398 #define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 1399 #define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 1400 1401 /* Description PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4 1402 1403 RSSI of RX PPDU on chain 4 of extension 80, high 20 MHz 1404 bandwidth. 1405 1406 Value of 0x80 indicates invalid. 1407 */ 1408 #define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000060 1409 #define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 1410 #define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 1411 1412 /* Description PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5 1413 1414 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 1415 1416 Value of 0x80 indicates invalid. 1417 */ 1418 #define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000064 1419 #define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 1420 #define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff 1421 1422 /* Description PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5 1423 1424 RSSI of RX PPDU on chain 5 of extension 20 MHz 1425 bandwidth. 1426 1427 Value of 0x80 indicates invalid. 1428 */ 1429 #define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000064 1430 #define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 1431 #define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 1432 1433 /* Description PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5 1434 1435 RSSI of RX PPDU on chain 5 of extension 40, low 20 MHz 1436 bandwidth. 1437 1438 Value of 0x80 indicates invalid. 1439 */ 1440 #define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000064 1441 #define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 1442 #define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 1443 1444 /* Description PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5 1445 1446 RSSI of RX PPDU on chain 5 of extension 40, high 20 MHz 1447 bandwidth. 1448 1449 Value of 0x80 indicates invalid. 1450 */ 1451 #define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000064 1452 #define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 1453 #define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 1454 1455 /* Description PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5 1456 1457 RSSI of RX PPDU on chain 5 of extension 80, low 20 MHz 1458 bandwidth. 1459 1460 Value of 0x80 indicates invalid. 1461 */ 1462 #define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000068 1463 #define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 1464 #define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff 1465 1466 /* Description PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5 1467 1468 RSSI of RX PPDU on chain 5 of extension 80, low-high 20 1469 MHz bandwidth. 1470 1471 Value of 0x80 indicates invalid. 1472 */ 1473 #define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000068 1474 #define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 1475 #define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 1476 1477 /* Description PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5 1478 1479 RSSI of RX PPDU on chain 5 of extension 80, high-low 20 1480 MHz bandwidth. 1481 1482 Value of 0x80 indicates invalid. 1483 */ 1484 #define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000068 1485 #define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 1486 #define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 1487 1488 /* Description PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5 1489 1490 RSSI of RX PPDU on chain 5 of extension 80, high 20 MHz 1491 bandwidth. 1492 1493 Value of 0x80 indicates invalid. 1494 */ 1495 #define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000068 1496 #define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 1497 #define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 1498 1499 /* Description PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6 1500 1501 RSSI of RX PPDU on chain 6 of primary 20 MHz bandwidth. 1502 1503 Value of 0x80 indicates invalid. 1504 */ 1505 #define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000006c 1506 #define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 1507 #define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff 1508 1509 /* Description PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6 1510 1511 RSSI of RX PPDU on chain 6 of extension 20 MHz 1512 bandwidth. 1513 1514 Value of 0x80 indicates invalid. 1515 */ 1516 #define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000006c 1517 #define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 1518 #define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 1519 1520 /* Description PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6 1521 1522 RSSI of RX PPDU on chain 6 of extension 40, low 20 MHz 1523 bandwidth. 1524 1525 Value of 0x80 indicates invalid. 1526 */ 1527 #define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000006c 1528 #define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 1529 #define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 1530 1531 /* Description PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6 1532 1533 RSSI of RX PPDU on chain 6 of extension 40, high 20 MHz 1534 bandwidth. 1535 1536 Value of 0x80 indicates invalid. 1537 */ 1538 #define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000006c 1539 #define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 1540 #define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 1541 1542 /* Description PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6 1543 1544 RSSI of RX PPDU on chain 6 of extension 80, low 20 MHz 1545 bandwidth. 1546 1547 Value of 0x80 indicates invalid. 1548 */ 1549 #define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000070 1550 #define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 1551 #define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff 1552 1553 /* Description PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6 1554 1555 RSSI of RX PPDU on chain 6 of extension 80, low-high 20 1556 MHz bandwidth. 1557 1558 Value of 0x80 indicates invalid. 1559 */ 1560 #define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000070 1561 #define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 1562 #define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 1563 1564 /* Description PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6 1565 1566 RSSI of RX PPDU on chain 6 of extension 80, high-low 20 1567 MHz bandwidth. 1568 1569 Value of 0x80 indicates invalid. 1570 */ 1571 #define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000070 1572 #define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 1573 #define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 1574 1575 /* Description PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6 1576 1577 RSSI of RX PPDU on chain 6 of extension 80, high 20 MHz 1578 bandwidth. 1579 1580 Value of 0x80 indicates invalid. 1581 */ 1582 #define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000070 1583 #define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 1584 #define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 1585 1586 /* Description PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7 1587 1588 RSSI of RX PPDU on chain 7 of primary 20 MHz bandwidth. 1589 1590 Value of 0x80 indicates invalid. 1591 */ 1592 #define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000074 1593 #define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 1594 #define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff 1595 1596 /* Description PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7 1597 1598 RSSI of RX PPDU on chain 7 of extension 20 MHz 1599 bandwidth. 1600 1601 Value of 0x80 indicates invalid. 1602 */ 1603 #define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000074 1604 #define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 1605 #define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 1606 1607 /* Description PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7 1608 1609 RSSI of RX PPDU on chain 7 of extension 40, low 20 MHz 1610 bandwidth. 1611 1612 Value of 0x80 indicates invalid. 1613 */ 1614 #define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000074 1615 #define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 1616 #define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 1617 1618 /* Description PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7 1619 1620 RSSI of RX PPDU on chain 7 of extension 40, high 20 MHz 1621 bandwidth. 1622 1623 Value of 0x80 indicates invalid. 1624 */ 1625 #define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000074 1626 #define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 1627 #define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 1628 1629 /* Description PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7 1630 1631 RSSI of RX PPDU on chain 7 of extension 80, low 20 MHz 1632 bandwidth. 1633 1634 Value of 0x80 indicates invalid. 1635 */ 1636 #define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000078 1637 #define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 1638 #define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff 1639 1640 /* Description PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7 1641 1642 RSSI of RX PPDU on chain 7 of extension 80, low-high 20 1643 MHz bandwidth. 1644 1645 Value of 0x80 indicates invalid. 1646 */ 1647 #define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000078 1648 #define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 1649 #define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 1650 1651 /* Description PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7 1652 1653 RSSI of RX PPDU on chain 7 of extension 80, high-low 20 1654 MHz bandwidth. 1655 1656 Value of 0x80 indicates invalid. 1657 */ 1658 #define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000078 1659 #define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 1660 #define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 1661 1662 /* Description PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7 1663 1664 RSSI of RX PPDU on chain 7 of extension 80, high 20 MHz 1665 bandwidth. 1666 1667 Value of 0x80 indicates invalid. 1668 */ 1669 #define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000078 1670 #define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 1671 #define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 1672 1673 /* Description PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0 1674 1675 Some PHY micro code status that can be put in here. 1676 Details of definition within SW specification 1677 1678 This field can be used for debugging, FW - SW message 1679 exchange, etc. 1680 1681 It could for example be a pointer to a DDR memory 1682 location where PHY FW put some debug info. 1683 1684 <legal all> 1685 */ 1686 #define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000007c 1687 #define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0 1688 #define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0xffffffff 1689 1690 /* Description PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32 1691 1692 Some PHY micro code status that can be put in here. 1693 Details of definition within SW specification 1694 1695 This field can be used for debugging, FW - SW message 1696 exchange, etc. 1697 1698 It could for example be a pointer to a DDR memory 1699 location where PHY FW put some debug info. 1700 1701 <legal all> 1702 */ 1703 #define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x00000080 1704 #define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 0 1705 #define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff 1706 1707 1708 #endif // _PHYRX_PKT_END_H_ 1709