1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ 18 #define _UNIFORM_DESCRIPTOR_HEADER_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 23 24 25 struct uniform_descriptor_header { 26 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 27 uint32_t owner : 4, // [3:0] 28 buffer_type : 4, // [7:4] 29 tx_mpdu_queue_number : 20, // [27:8] 30 reserved_0a : 4; // [31:28] 31 #else 32 uint32_t reserved_0a : 4, // [31:28] 33 tx_mpdu_queue_number : 20, // [27:8] 34 buffer_type : 4, // [7:4] 35 owner : 4; // [3:0] 36 #endif 37 }; 38 39 40 /* Description OWNER 41 42 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 43 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 44 45 The owner of this data structure: 46 <enum 0 WBM_owned> Buffer Manager currently owns this data 47 structure. 48 <enum 1 SW_OR_FW_owned> Software of FW currently owns this 49 data structure. 50 <enum 2 TQM_owned> Transmit Queue Manager currently owns 51 this data structure. 52 <enum 3 RXDMA_owned> Receive DMA currently owns this data 53 structure. 54 <enum 4 REO_owned> Reorder currently owns this data structure. 55 56 <enum 5 SWITCH_owned> SWITCH currently owns this data structure. 57 58 59 <legal 0-5> 60 */ 61 62 #define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 63 #define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB 0 64 #define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB 3 65 #define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 66 67 68 /* Description BUFFER_TYPE 69 70 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 71 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 72 73 Field describing what contents format is of this descriptor 74 75 76 <enum 0 Transmit_MSDU_Link_descriptor> 77 <enum 1 Transmit_MPDU_Link_descriptor> 78 <enum 2 Transmit_MPDU_Queue_head_descriptor> 79 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 80 <enum 4 Transmit_flow_descriptor> 81 <enum 5 Transmit_buffer> NOT TO BE USED: 82 83 <enum 6 Receive_MSDU_Link_descriptor> 84 <enum 7 Receive_MPDU_Link_descriptor> 85 <enum 8 Receive_REO_queue_descriptor> 86 <enum 9 Receive_REO_queue_1k_descriptor> 87 <enum 10 Receive_REO_queue_ext_descriptor> 88 89 <enum 11 Receive_buffer> 90 91 <enum 12 Idle_link_list_entry> 92 93 <legal 0-12> 94 */ 95 96 #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 97 #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 98 #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 99 #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 100 101 102 /* Description TX_MPDU_QUEUE_NUMBER 103 104 Consumer: TQM/Debug 105 Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) 106 107 Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor 108 109 110 Indicates the MPDU queue ID to which this MPDU descriptor 111 belongs 112 Used for tracking and debugging 113 114 <legal all> 115 */ 116 117 #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 118 #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 119 #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 120 #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 121 122 123 /* Description RESERVED_0A 124 125 <legal 0> 126 */ 127 128 #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 129 #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 130 #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 131 #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 132 133 134 135 #endif // UNIFORM_DESCRIPTOR_HEADER 136