1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _TX_QUEUE_EXTENSION_H_ 18 #define _TX_QUEUE_EXTENSION_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 14 23 24 #define NUM_OF_QWORDS_TX_QUEUE_EXTENSION 7 25 26 27 struct tx_queue_extension { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t frame_ctl : 16, // [15:0] 30 qos_ctl : 16; // [31:16] 31 uint32_t ampdu_flag : 1, // [0:0] 32 tx_notify_no_htc_override : 1, // [1:1] 33 reserved_1a : 7, // [8:2] 34 checksum_tso_disable_for_frag : 1, // [9:9] 35 key_id : 8, // [17:10] 36 qos_buf_state_overwrite : 1, // [18:18] 37 buf_state_sta_id : 1, // [19:19] 38 buf_state_source : 1, // [20:20] 39 ht_control_overwrite_enable : 1, // [21:21] 40 ht_control_overwrite_source : 4, // [25:22] 41 reserved_1b : 6; // [31:26] 42 uint32_t ul_headroom_insertion_enable : 1, // [0:0] 43 ul_headroom_offset : 5, // [5:1] 44 bqrp_insertion_enable : 1, // [6:6] 45 bqrp_offset : 5, // [11:7] 46 ul_headroom_rsvd_7_6 : 2, // [13:12] 47 bqr_rsvd_9_8 : 2, // [15:14] 48 base_pn_63_48 : 16; // [31:16] 49 uint32_t base_pn_95_64 : 32; // [31:0] 50 uint32_t base_pn_127_96 : 32; // [31:0] 51 uint32_t ht_control_field_bw20 : 32; // [31:0] 52 uint32_t ht_control_field_bw40 : 32; // [31:0] 53 uint32_t ht_control_field_bw80 : 32; // [31:0] 54 uint32_t ht_control_field_bw160 : 32; // [31:0] 55 uint32_t ht_control_overwrite_mask : 32; // [31:0] 56 uint32_t cas_control_info : 8, // [7:0] 57 cas_offset : 5, // [12:8] 58 cas_insertion_enable : 1, // [13:13] 59 reserved_10a : 2, // [15:14] 60 ht_control_overwrite_source_for_srp : 4, // [19:16] 61 ht_control_overwrite_source_for_bsrp : 4, // [23:20] 62 reserved_10b : 6, // [29:24] 63 mpdu_hdr_len_override_en : 1, // [30:30] 64 bar_ssn_overwrite_enable : 1; // [31:31] 65 uint32_t bar_ssn_offset : 12, // [11:0] 66 mpdu_hdr_len_override_val : 9, // [20:12] 67 reserved_11a : 11; // [31:21] 68 uint32_t ht_control_field_bw320 : 32; // [31:0] 69 uint32_t fw2sw_info : 32; // [31:0] 70 #else 71 uint32_t qos_ctl : 16, // [31:16] 72 frame_ctl : 16; // [15:0] 73 uint32_t reserved_1b : 6, // [31:26] 74 ht_control_overwrite_source : 4, // [25:22] 75 ht_control_overwrite_enable : 1, // [21:21] 76 buf_state_source : 1, // [20:20] 77 buf_state_sta_id : 1, // [19:19] 78 qos_buf_state_overwrite : 1, // [18:18] 79 key_id : 8, // [17:10] 80 checksum_tso_disable_for_frag : 1, // [9:9] 81 reserved_1a : 7, // [8:2] 82 tx_notify_no_htc_override : 1, // [1:1] 83 ampdu_flag : 1; // [0:0] 84 uint32_t base_pn_63_48 : 16, // [31:16] 85 bqr_rsvd_9_8 : 2, // [15:14] 86 ul_headroom_rsvd_7_6 : 2, // [13:12] 87 bqrp_offset : 5, // [11:7] 88 bqrp_insertion_enable : 1, // [6:6] 89 ul_headroom_offset : 5, // [5:1] 90 ul_headroom_insertion_enable : 1; // [0:0] 91 uint32_t base_pn_95_64 : 32; // [31:0] 92 uint32_t base_pn_127_96 : 32; // [31:0] 93 uint32_t ht_control_field_bw20 : 32; // [31:0] 94 uint32_t ht_control_field_bw40 : 32; // [31:0] 95 uint32_t ht_control_field_bw80 : 32; // [31:0] 96 uint32_t ht_control_field_bw160 : 32; // [31:0] 97 uint32_t ht_control_overwrite_mask : 32; // [31:0] 98 uint32_t bar_ssn_overwrite_enable : 1, // [31:31] 99 mpdu_hdr_len_override_en : 1, // [30:30] 100 reserved_10b : 6, // [29:24] 101 ht_control_overwrite_source_for_bsrp : 4, // [23:20] 102 ht_control_overwrite_source_for_srp : 4, // [19:16] 103 reserved_10a : 2, // [15:14] 104 cas_insertion_enable : 1, // [13:13] 105 cas_offset : 5, // [12:8] 106 cas_control_info : 8; // [7:0] 107 uint32_t reserved_11a : 11, // [31:21] 108 mpdu_hdr_len_override_val : 9, // [20:12] 109 bar_ssn_offset : 12; // [11:0] 110 uint32_t ht_control_field_bw320 : 32; // [31:0] 111 uint32_t fw2sw_info : 32; // [31:0] 112 #endif 113 }; 114 115 116 /* Description FRAME_CTL 117 118 Consumer: TXOLE 119 Producer: SW 120 121 122 802.11 Frame control field: 123 fc [1:0]: Protocol Version 124 fc[7:2]: type/subtypeFor non-11ah fc[3:2] = Type fc[7:4] = 125 Subtype For 11ah fc[4:2] = Typefc[7:5] = PTID/SubType 126 fc [8]: To DS ( for Non-11ah) From DS ( for 11ah ) 127 fc [9]: From DS ( for Non-11ah ) 128 More Frag ( for 11ah ) 129 fc [10]: More Frag ( for Non-11ah ) 130 Power Management ( for 11ah) 131 fc [11]: Retry ( for Non-11ah ) 132 More Data ( for 11ah ) 133 fc [12]: Pwr Mgt ( for Non-11ah ) 134 Protected Frame ( for 11ah ) 135 fc [13]: More Data( for Non-11ah ) 136 EOSP ( for 11ah ) 137 fc [14]: Protected Frame ( for Non-11ah) 138 Relayed Frame ( for 11ah ) 139 fc [15]: Order ( for Non-11ah ) 140 Ack Policy ( for 11ah ) 141 Used by OLE during the encapsulation process for Native 142 WiFi, Ethernet II, and 802.3. 143 When the Order field is set, TXOLE shall insert 4 placeholder 144 bytes for the HE-control field in the frame. TXPCU will 145 overwrite them with the final actual value... 146 */ 147 148 #define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x0000000000000000 149 #define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0 150 #define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15 151 #define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x000000000000ffff 152 153 154 /* Description QOS_CTL 155 156 Consumer: TXOLE 157 Producer: SW 158 159 QoS control field is valid if the type field is data and 160 the upper bit of the subtype field is set. The field decode 161 is as below: 162 qos_ctl[3:0]: TID 163 qos_ctl[4]: EOSP (with some exceptions) 164 qos_ctl[6:5]: Ack Policy 165 0x0: Normal Ack or Implicit BAR 166 0x1: No Ack 167 0x2: No explicit Ack or PSMP Ack (not supported) 168 0x3: Block Ack (Not supported) 169 Qos_ctl[7]: A-MSDU Present (with some exceptions) 170 Qos_ctl[15:8]: TXOP limit, AP PS buffer state, TXOP duration 171 requested or queue size 172 This field is inserted into the 802.11 header during the 173 encapsulation process 174 <legal all> 175 */ 176 177 #define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x0000000000000000 178 #define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16 179 #define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31 180 #define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0x00000000ffff0000 181 182 183 /* Description AMPDU_FLAG 184 185 Consumer: PDG/TXPCU 186 Producer: SW 187 188 Note: 189 For legacy rate transmissions (11 b and 11a, an 11g), this 190 bit shall always be set to zero. 191 192 0: 193 For legacy and .11n rates: 194 MPDUs are only allowed to be sent out 1 at a time in NON 195 A-MPDU format. 196 For .11ac and .11ax rates: 197 MPDUs are sent out in S-MPDU format (TXPCU sets the 'EOF' 198 bit in the MPDU delimiter). 199 1: All MPDUs should be sent out using the A-MPDU format, 200 even if there is only one MPDU. 201 202 Note that this bit should be set to 0 in order to construct 203 an S-MPDU frame. VHT and HE frames are all A-MPDU format 204 but if this bit is clear, EOF bit is set to 1 for the MPDU 205 delimiter in A-MPDU, which is the indicator of S-MPDU and 206 solicits ACK rather than BA as response frame. 207 208 This bit shall be set to 1 for any MD (Multi Destination) 209 transmission. 210 */ 211 212 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x0000000000000000 213 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 32 214 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 32 215 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x0000000100000000 216 217 218 /* Description TX_NOTIFY_NO_HTC_OVERRIDE 219 220 When set, and a 'TX_MPDU_START' TLV has Tx_notify_frame 221 set to TX_HARD_NOTIFY or TX_SOFT_NOTIFY or TX_SEMI_HARD_NOTIFY, 222 then PDG would have updated the rate fields for a legacy 223 PPDU which may not support HT Control. 224 225 In this case TXOLE shall not: 226 set the Order/+HTC bit in the 'Frame Control,' 227 include 4 bytes for TXPCU to fill the HT Control, or 228 set vht_control_present in 'TX_MPDU_START,' 229 even if requested, and instead shall subtract '4' from the 230 mpdu_length in 'TX_MPDU_START' and overwrite it. 231 232 <legal all> 233 */ 234 235 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x0000000000000000 236 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 33 237 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 33 238 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x0000000200000000 239 240 241 242 #define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x0000000000000000 243 #define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 34 244 #define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 40 245 #define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc00000000 246 247 248 /* Description CHECKSUM_TSO_DISABLE_FOR_FRAG 249 250 Field only valid in case of level-1 fragmentation, identified 251 by TXOLE getting the 'TX_FRAG_STATE' TLV 252 253 If set, TXOLE disables all checksum and TSO overwrites for 254 the fragment(s) being transmitted. 255 256 This is useful if it is known that the checksum and TSO 257 overwrites affect only the first fragment (or first few 258 fragments) and for the rest these can be safely disabled. 259 260 261 <legal all> 262 */ 263 264 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x0000000000000000 265 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 41 266 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 41 267 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x0000020000000000 268 269 270 /* Description KEY_ID 271 272 Field only valid in case of encryption, and TXOLE being 273 instructured to insert the IV. 274 275 TXOLE blindly copies this field into the key ID octet (which 276 is part of the IV) of the encrypted frame. 277 278 For AES/TKIP the encoding is: 279 key_id_octet[7:6]: key ID 280 key_id_octet[5]: extended IV: 281 key_id_octet[4:0]: Reserved bits 282 283 For WEP the encoding is: 284 key_id_octet[7:6]: key ID 285 key_id_octet[5]: extended IV: 286 key_id_octet[4:0]: Reserved bits 287 288 For WAPI the encoding is: 289 key_id_octet[7:2]: Reserved bits 290 key_id_octet[1:0]: key ID 291 292 <legal all> 293 */ 294 295 #define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x0000000000000000 296 #define TX_QUEUE_EXTENSION_KEY_ID_LSB 42 297 #define TX_QUEUE_EXTENSION_KEY_ID_MSB 49 298 #define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc0000000000 299 300 301 /* Description QOS_BUF_STATE_OVERWRITE 302 303 When clear, TXPCU shall not overwrite buffer state field 304 in the QoS frame control field. 305 306 When set, TXPCU shall overwrite the buffer state field in 307 the QoS frame control field, with info that SW has programmed 308 in TXPCU registers. Note that TXPCU shall pick up the values 309 related to this TID. 310 <legal all> 311 */ 312 313 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x0000000000000000 314 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 50 315 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 50 316 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x0004000000000000 317 318 319 /* Description BUF_STATE_STA_ID 320 321 Field only valid when QoS_Buf_state_overwrite is set. 322 323 This field indicates what the STA ID register source is 324 of the buffer status. 325 326 1'b0: TXPCU registers: STA0_buf_status_... 327 1'b1: TXPCU registers: STA1_buf_status_... 328 <legal all> 329 */ 330 331 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x0000000000000000 332 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 51 333 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 51 334 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x0008000000000000 335 336 337 /* Description BUF_STATE_SOURCE 338 339 Field only valid when QoS_Buf_state_overwrite is set. 340 341 This field indicates what the source is of the actual value 342 TXPCU will insert 343 344 <enum 0 BUF_STATE_TID_BASED> TXPCU looks at the TID field 345 in the QoS control frame and based on this TID, selects 346 the buffer source value from the corresponding TID register. 347 348 <enum 1 BUF_STATE_SUM_BASED> TXPCU inserts the value from 349 the buffer_state_sum register 350 351 <legal all> 352 */ 353 354 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x0000000000000000 355 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 52 356 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 52 357 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x0010000000000000 358 359 360 /* Description HT_CONTROL_OVERWRITE_ENABLE 361 362 When set, TXPCU shall overwrite some (or all) of the HT_CONTROL 363 field with values that are programmed in TXPCU registers: 364 HT_CONTROL_OVERWRITE_IX??? 365 366 See HT/HE control overwrite order NOTE after this table 367 368 <legal all> 369 */ 370 371 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x0000000000000000 372 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 53 373 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 53 374 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x0020000000000000 375 376 377 /* Description HT_CONTROL_OVERWRITE_SOURCE 378 379 Field only valid when HT_control_overwrite_enable is set. 380 381 382 This field indicates the index of the TXPCU register HT_CONTROL_OVERWRITE_IX??? 383 That is the source of the overwrite data. 384 <legal all> 385 */ 386 387 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x0000000000000000 388 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 54 389 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 57 390 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c0000000000000 391 392 393 394 #define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x0000000000000000 395 #define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 58 396 #define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 63 397 #define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc00000000000000 398 399 400 /* Description UL_HEADROOM_INSERTION_ENABLE 401 402 When set, and this transmission services a trigger response 403 transmission, TXPCU shall create and insert the UL headroom 404 info in the HE control field, starting at offset indicated 405 by field: UL_headroom_offset 406 407 See HT/HE control overwrite order NOTE after this table 408 <legal all> 409 */ 410 411 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x0000000000000008 412 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0 413 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0 414 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x0000000000000001 415 416 417 /* Description UL_HEADROOM_OFFSET 418 419 Field only valid when UL_headroom_insertion_enable is set. 420 421 422 The bit location in HE_CONTROL Field where TXPCU will start 423 writing the the 4 bit Control ID field that needs to be 424 inserted, followed by the lower 6 bits of the 8 bit bit 425 UL_headroom info (UPH Control). 426 427 NOTE: currently on 6 bits are defined in the UPH control 428 field. The upper two bits are provided by SW in UL_headroom_rsvd_7_6. 429 430 431 <legal 2-20> 432 */ 433 434 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x0000000000000008 435 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1 436 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5 437 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x000000000000003e 438 439 440 /* Description BQRP_INSERTION_ENABLE 441 442 When set, and this transmission services a BQRP trigger 443 response transmission, TXPCU shall create and insert the 444 BQR control field into the HE control field, as well as 445 the 4 bit preceding Control ID field. 446 447 See HT/HE control overwrite order NOTE after this table 448 <legal all> 449 */ 450 451 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x0000000000000008 452 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6 453 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6 454 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x0000000000000040 455 456 457 /* Description BQRP_OFFSET 458 459 Field only valid when BQRP_insertion_enable is set. 460 461 The bit location in HE_CONTROL Field where TXPCU will start 462 writing the 4 bit Control ID field that needs to be inserted, 463 followed by the lower 8 bits of the 10 bit BQR control field. 464 465 466 NOTE: currently only 8 bits are defined in the 10 bit BQR 467 control field. The upper two bits are provided by SW in 468 BQR_rsvd_9_8. 469 470 <legal 2-20> 471 */ 472 473 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x0000000000000008 474 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7 475 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11 476 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x0000000000000f80 477 478 479 /* Description UL_HEADROOM_RSVD_7_6 480 481 These will be used by TXPCU to fill the upper two bits of 482 the UPH control field. 483 <legal all> 484 */ 485 486 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x0000000000000008 487 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12 488 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13 489 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x0000000000003000 490 491 492 /* Description BQR_RSVD_9_8 493 494 These will be used by TXPCU to fill the upper two bits of 495 the BQR control field. 496 NOTE: When overwriting CAS control (8-bit) at the same offset 497 as BQR control (10-bit), TXPCU will ignore the BQR overwrite, 498 including these upper two bits. 499 <legal all> 500 */ 501 502 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x0000000000000008 503 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14 504 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15 505 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x000000000000c000 506 507 508 /* Description BASE_PN_63_48 509 510 Upper bits PN number, in case a larger then 48 bit PN number 511 needs to be inserted in the transmit frame. 512 513 63-48 bits of the 128-bit packet number 514 <legal all> 515 */ 516 517 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x0000000000000008 518 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16 519 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31 520 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0x00000000ffff0000 521 522 523 /* Description BASE_PN_95_64 524 525 Upper bits PN number, in case a larger then 48 bit PN number 526 needs to be inserted in the transmit frame. 527 528 95-64 bits of the 128-bit packet number 529 <legal all> 530 */ 531 532 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000000000008 533 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 32 534 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 63 535 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff00000000 536 537 538 /* Description BASE_PN_127_96 539 540 Upper bits PN number, in case a larger then 48 bit PN number 541 needs to be inserted in the transmit frame. 542 543 127-96 bits of the 128-bit packet number 544 <legal all> 545 */ 546 547 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x0000000000000010 548 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0 549 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31 550 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0x00000000ffffffff 551 552 553 /* Description HT_CONTROL_FIELD_BW20 554 555 Field used by TXPCU when in TX_MPDU_START TLV field vht_control_present 556 is set. 557 558 Note that TXPCU might overwrite some fields. This is controlled 559 with field HT_control_overwrite_enable 560 561 See HT/HE control overwrite order NOTE after this table 562 563 <legal all> 564 */ 565 566 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_OFFSET 0x0000000000000010 567 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_LSB 32 568 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MSB 63 569 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MASK 0xffffffff00000000 570 571 572 /* Description HT_CONTROL_FIELD_BW40 573 574 Field used by TXPCU when in TX_MPDU_START TLV field vht_control_present 575 is set. 576 577 Note that TXPCU might overwrite some fields. This is controlled 578 with field HT_control_overwrite_enable 579 580 See HT/HE control overwrite order NOTE after this table 581 582 <legal all> 583 */ 584 585 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_OFFSET 0x0000000000000018 586 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_LSB 0 587 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MSB 31 588 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MASK 0x00000000ffffffff 589 590 591 /* Description HT_CONTROL_FIELD_BW80 592 593 Field used by TXPCU when in TX_MPDU_START TLV field vht_control_present 594 is set. 595 596 Note that TXPCU might overwrite some fields. This is controlled 597 with field HT_control_overwrite_enable 598 599 See HT/HE control overwrite order NOTE after this table 600 601 <legal all> 602 */ 603 604 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_OFFSET 0x0000000000000018 605 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_LSB 32 606 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MSB 63 607 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MASK 0xffffffff00000000 608 609 610 /* Description HT_CONTROL_FIELD_BW160 611 612 Field used by TXPCU when in TX_MPDU_START TLV field vht_control_present 613 is set. 614 615 Note that TXPCU might overwrite some fields. This is controlled 616 with field HT_control_overwrite_enable 617 618 See HT/HE control overwrite order NOTE after this table 619 620 <legal all> 621 */ 622 623 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_OFFSET 0x0000000000000020 624 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_LSB 0 625 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MSB 31 626 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MASK 0x00000000ffffffff 627 628 629 /* Description HT_CONTROL_OVERWRITE_MASK 630 631 Field only valid when HT_control_overwrite_enable is set. 632 633 634 This field indicates which bits of the HT_CONTROL_FIELD 635 shall be overwritten with bits from TXPCU register HT_CONTROL_OVERWRITE_IX??? 636 637 Every bit that needs to be overwritten is set to 1 in this 638 register. 639 <legal all> 640 */ 641 642 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x0000000000000020 643 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 32 644 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 63 645 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff00000000 646 647 648 /* Description CAS_CONTROL_INFO 649 650 This contains 8-bit CAS control field to be used for transmission 651 during SRP window 652 <legal all> 653 */ 654 655 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x0000000000000028 656 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0 657 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7 658 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x00000000000000ff 659 660 661 /* Description CAS_OFFSET 662 663 5 bit offset for CAS insertion 664 <legal 2-20> 665 */ 666 667 #define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x0000000000000028 668 #define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8 669 #define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12 670 #define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x0000000000001f00 671 672 673 /* Description CAS_INSERTION_ENABLE 674 675 single bit used as ENABLE for CAS control insertion for 676 transmission during SRP window 677 <legal all> 678 */ 679 680 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x0000000000000028 681 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13 682 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13 683 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x0000000000002000 684 685 686 /* Description RESERVED_10A 687 688 <legal 0> 689 */ 690 691 #define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x0000000000000028 692 #define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14 693 #define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15 694 #define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x000000000000c000 695 696 697 /* Description HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP 698 699 4-bit index similar to HT_control_overwrite_source field 700 to be used for transmission during SRP window 701 <legal all> 702 */ 703 704 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x0000000000000028 705 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16 706 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19 707 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x00000000000f0000 708 709 710 /* Description HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP 711 712 4-bit index similar to HT_control_overwrite_source field 713 to be used for response to BSRP triggers (even during SRP 714 window) 715 <legal all> 716 */ 717 718 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x0000000000000028 719 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20 720 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23 721 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x0000000000f00000 722 723 724 /* Description RESERVED_10B 725 726 <legal 0> 727 */ 728 729 #define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x0000000000000028 730 #define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 24 731 #define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29 732 #define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x000000003f000000 733 734 735 /* Description MPDU_HDR_LEN_OVERRIDE_EN 736 737 This is for the FW override of MPDU overhead length programmed 738 in the TQM queue. 739 740 If enabled, PDG will update the length of each MPDU by subtracting 741 the value of field Mpdu_header_length in 'MPDU_QUEUE_OVERVIEW' 742 and adding Mpdu_hdr_len_override_val (in this TLV). 743 <legal all> 744 */ 745 746 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x0000000000000028 747 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30 748 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30 749 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x0000000040000000 750 751 752 /* Description BAR_SSN_OVERWRITE_ENABLE 753 754 If enabled, TXPCU will overwrite the starting sequence number 755 in case of Tx BAR or MU-BAR Trigger from with the sequence 756 number from 'MPDU_QUEUE_OVERVIEW' 757 <legal all> 758 */ 759 760 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 761 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31 762 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31 763 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x0000000080000000 764 765 766 /* Description BAR_SSN_OFFSET 767 768 Offset to the starting sequence number in case of Tx BAR 769 or MU-BAR Trigger that TXPCU can overwrite with the sequence 770 number from 'MPDU_QUEUE_OVERVIEW' 771 <legal all> 772 */ 773 774 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000000000000028 775 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 32 776 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 43 777 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff00000000 778 779 780 /* Description MPDU_HDR_LEN_OVERRIDE_VAL 781 782 This is for the FW override of MPDU overhead length programmed 783 in the TQM queue. 784 785 <legal all> 786 */ 787 788 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000000000000028 789 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 44 790 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 52 791 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff00000000000 792 793 794 795 #define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000000000000028 796 #define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 53 797 #define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 63 798 #define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe0000000000000 799 800 801 /* Description HT_CONTROL_FIELD_BW320 802 803 Field used by TXPCU when in TX_MPDU_START TLV field vht_control_present 804 is set. 805 806 Note that TXPCU might overwrite some fields. This is controlled 807 with field HT_control_overwrite_enable 808 809 <legal all> 810 */ 811 812 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_OFFSET 0x0000000000000030 813 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_LSB 0 814 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MSB 31 815 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MASK 0x00000000ffffffff 816 817 818 /* Description FW2SW_INFO 819 820 This field is provided by FW, to be logged via TXMON to 821 host SW. It is transparent to HW. 822 823 <legal all> 824 */ 825 826 #define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x0000000000000030 827 #define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 32 828 #define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 63 829 #define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0xffffffff00000000 830 831 832 833 #endif // TX_QUEUE_EXTENSION 834