1 /*
2  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef _TX_MSDU_START_H_
18 #define _TX_MSDU_START_H_
19 #if !defined(__ASSEMBLER__)
20 #endif
21 
22 #define NUM_OF_DWORDS_TX_MSDU_START 8
23 
24 #define NUM_OF_QWORDS_TX_MSDU_START 4
25 
26 
27 struct tx_msdu_start {
28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
29              uint32_t msdu_len                                                : 14, // [13:0]
30                       first_msdu                                              :  1, // [14:14]
31                       last_msdu                                               :  1, // [15:15]
32                       encap_type                                              :  2, // [17:16]
33                       epd_en                                                  :  1, // [18:18]
34                       da_sa_present                                           :  2, // [20:19]
35                       ipv4_checksum_en                                        :  1, // [21:21]
36                       udp_over_ipv4_checksum_en                               :  1, // [22:22]
37                       udp_over_ipv6_checksum_en                               :  1, // [23:23]
38                       tcp_over_ipv4_checksum_en                               :  1, // [24:24]
39                       tcp_over_ipv6_checksum_en                               :  1, // [25:25]
40                       dummy_msdu_delimitation                                 :  1, // [26:26]
41                       reserved_0a                                             :  5; // [31:27]
42              uint32_t tso_enable                                              :  1, // [0:0]
43                       reserved_1a                                             :  6, // [6:1]
44                       tcp_flag                                                :  9, // [15:7]
45                       tcp_flag_mask                                           :  9, // [24:16]
46                       mesh_enable                                             :  1, // [25:25]
47                       reserved_1b                                             :  6; // [31:26]
48              uint32_t l2_length                                               : 16, // [15:0]
49                       ip_length                                               : 16; // [31:16]
50              uint32_t tcp_seq_number                                          : 32; // [31:0]
51              uint32_t ip_identification                                       : 16, // [15:0]
52                       checksum_offset                                         : 13, // [28:16]
53                       partial_checksum_en                                     :  1, // [29:29]
54                       reserved_4                                              :  2; // [31:30]
55              uint32_t payload_start_offset                                    : 14, // [13:0]
56                       reserved_5a                                             :  2, // [15:14]
57                       payload_end_offset                                      : 14, // [29:16]
58                       reserved_5b                                             :  2; // [31:30]
59              uint32_t udp_length                                              : 16, // [15:0]
60                       reserved_6                                              : 16; // [31:16]
61              uint32_t tlv64_padding                                           : 32; // [31:0]
62 #else
63              uint32_t reserved_0a                                             :  5, // [31:27]
64                       dummy_msdu_delimitation                                 :  1, // [26:26]
65                       tcp_over_ipv6_checksum_en                               :  1, // [25:25]
66                       tcp_over_ipv4_checksum_en                               :  1, // [24:24]
67                       udp_over_ipv6_checksum_en                               :  1, // [23:23]
68                       udp_over_ipv4_checksum_en                               :  1, // [22:22]
69                       ipv4_checksum_en                                        :  1, // [21:21]
70                       da_sa_present                                           :  2, // [20:19]
71                       epd_en                                                  :  1, // [18:18]
72                       encap_type                                              :  2, // [17:16]
73                       last_msdu                                               :  1, // [15:15]
74                       first_msdu                                              :  1, // [14:14]
75                       msdu_len                                                : 14; // [13:0]
76              uint32_t reserved_1b                                             :  6, // [31:26]
77                       mesh_enable                                             :  1, // [25:25]
78                       tcp_flag_mask                                           :  9, // [24:16]
79                       tcp_flag                                                :  9, // [15:7]
80                       reserved_1a                                             :  6, // [6:1]
81                       tso_enable                                              :  1; // [0:0]
82              uint32_t ip_length                                               : 16, // [31:16]
83                       l2_length                                               : 16; // [15:0]
84              uint32_t tcp_seq_number                                          : 32; // [31:0]
85              uint32_t reserved_4                                              :  2, // [31:30]
86                       partial_checksum_en                                     :  1, // [29:29]
87                       checksum_offset                                         : 13, // [28:16]
88                       ip_identification                                       : 16; // [15:0]
89              uint32_t reserved_5b                                             :  2, // [31:30]
90                       payload_end_offset                                      : 14, // [29:16]
91                       reserved_5a                                             :  2, // [15:14]
92                       payload_start_offset                                    : 14; // [13:0]
93              uint32_t reserved_6                                              : 16, // [31:16]
94                       udp_length                                              : 16; // [15:0]
95              uint32_t tlv64_padding                                           : 32; // [31:0]
96 #endif
97 };
98 
99 
100 /* Description		MSDU_LEN
101 
102 			MSDU length before encapsulation. It is the same value as
103 			 the length in the MSDU packet TLV
104 */
105 
106 #define TX_MSDU_START_MSDU_LEN_OFFSET                                               0x0000000000000000
107 #define TX_MSDU_START_MSDU_LEN_LSB                                                  0
108 #define TX_MSDU_START_MSDU_LEN_MSB                                                  13
109 #define TX_MSDU_START_MSDU_LEN_MASK                                                 0x0000000000003fff
110 
111 
112 /* Description		FIRST_MSDU
113 
114 			If set the current MSDU is the first MSDU in MPDU.  Used
115 			 by the OLE during encapsulation.
116 */
117 
118 #define TX_MSDU_START_FIRST_MSDU_OFFSET                                             0x0000000000000000
119 #define TX_MSDU_START_FIRST_MSDU_LSB                                                14
120 #define TX_MSDU_START_FIRST_MSDU_MSB                                                14
121 #define TX_MSDU_START_FIRST_MSDU_MASK                                               0x0000000000004000
122 
123 
124 /* Description		LAST_MSDU
125 
126 			If set the current MSDU is the last MSDU in MPDU.  Used
127 			by the OLE during encapsulation.
128 */
129 
130 #define TX_MSDU_START_LAST_MSDU_OFFSET                                              0x0000000000000000
131 #define TX_MSDU_START_LAST_MSDU_LSB                                                 15
132 #define TX_MSDU_START_LAST_MSDU_MSB                                                 15
133 #define TX_MSDU_START_LAST_MSDU_MASK                                                0x0000000000008000
134 
135 
136 /* Description		ENCAP_TYPE
137 
138 			Indicates the encapsulation that HW will perform:
139 			<enum 0 RAW> No encapsulation
140 			<enum 1 Native_WiFi>
141 			<enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC)
142 
143 			<enum 3 802_3> DO NOT USE. Indicate Ethernet
144 			Used by the OLE during encapsulation.
145 			<legal all>
146 */
147 
148 #define TX_MSDU_START_ENCAP_TYPE_OFFSET                                             0x0000000000000000
149 #define TX_MSDU_START_ENCAP_TYPE_LSB                                                16
150 #define TX_MSDU_START_ENCAP_TYPE_MSB                                                17
151 #define TX_MSDU_START_ENCAP_TYPE_MASK                                               0x0000000000030000
152 
153 
154 /* Description		EPD_EN
155 
156 			Consumer: TXOLE
157 			Producer: SW/TCL
158 
159 			If set to one use EPD instead of LPD
160 			<legal all>
161 */
162 
163 #define TX_MSDU_START_EPD_EN_OFFSET                                                 0x0000000000000000
164 #define TX_MSDU_START_EPD_EN_LSB                                                    18
165 #define TX_MSDU_START_EPD_EN_MSB                                                    18
166 #define TX_MSDU_START_EPD_EN_MASK                                                   0x0000000000040000
167 
168 
169 /* Description		DA_SA_PRESENT
170 
171 			Used for 11ah
172 
173 			Indicates the encapsulation that HW will perform:
174 			<enum 0 DA_SA_IS_ABSENT> DA and SA absent
175 			<enum 1 DA_IS_PRESENT>  DA Present, SA Absent
176 			<enum 2 SA_IS_PRESENT>
177 			<enum 3 DA_SA_IS_PRESENT>  Both DA and SA are present
178 			Used by the OLE during encapsulation.
179 
180 			TXDMA gets this configuration from a sw configuration register.
181 
182 
183 			<legal all>
184 */
185 
186 #define TX_MSDU_START_DA_SA_PRESENT_OFFSET                                          0x0000000000000000
187 #define TX_MSDU_START_DA_SA_PRESENT_LSB                                             19
188 #define TX_MSDU_START_DA_SA_PRESENT_MSB                                             20
189 #define TX_MSDU_START_DA_SA_PRESENT_MASK                                            0x0000000000180000
190 
191 
192 /* Description		IPV4_CHECKSUM_EN
193 
194 			Enable IPv4 checksum replacement
195 */
196 
197 #define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET                                       0x0000000000000000
198 #define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB                                          21
199 #define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB                                          21
200 #define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK                                         0x0000000000200000
201 
202 
203 /* Description		UDP_OVER_IPV4_CHECKSUM_EN
204 
205 			Enable UDP over IPv4 checksum replacement.  UDP checksum
206 			 over IPv4 is optional for TCP/IP stacks.
207 */
208 
209 #define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET                              0x0000000000000000
210 #define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB                                 22
211 #define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB                                 22
212 #define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK                                0x0000000000400000
213 
214 
215 /* Description		UDP_OVER_IPV6_CHECKSUM_EN
216 
217 			Enable UDP over IPv6 checksum replacement.  UDP checksum
218 			 over IPv6 is mandatory for TCP/IP stacks.
219 */
220 
221 #define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET                              0x0000000000000000
222 #define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB                                 23
223 #define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB                                 23
224 #define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK                                0x0000000000800000
225 
226 
227 /* Description		TCP_OVER_IPV4_CHECKSUM_EN
228 
229 			Enable TCP checksum over IPv4 replacement
230 */
231 
232 #define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET                              0x0000000000000000
233 #define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB                                 24
234 #define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB                                 24
235 #define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK                                0x0000000001000000
236 
237 
238 /* Description		TCP_OVER_IPV6_CHECKSUM_EN
239 
240 			Enable TCP checksum over IPv6 eplacement
241 */
242 
243 #define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET                              0x0000000000000000
244 #define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB                                 25
245 #define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB                                 25
246 #define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK                                0x0000000002000000
247 
248 
249 /* Description		DUMMY_MSDU_DELIMITATION
250 
251 			This bit is mainly for debug.
252 
253 			TXDMA sets this bit when sending a dummy 'TX_MSDU_END' + 'TX_MSDU_START'
254 			sequence for a user to delimit user arbitration where it
255 			 could switch to packet data from other users before continuing
256 			 this MSDU.
257 
258 			This is done mainly for long raw Wi-Fi packets where TXDMA
259 			 needs to switch users in the midst of the packet but other
260 			 blocks assume TXDMA switch only at MSDU boundaries.
261 			<legal all>
262 */
263 
264 #define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET                                0x0000000000000000
265 #define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB                                   26
266 #define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB                                   26
267 #define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK                                  0x0000000004000000
268 
269 
270 /* Description		RESERVED_0A
271 
272 			FW will set to 0, MAC will ignore.  <legal 0>
273 */
274 
275 #define TX_MSDU_START_RESERVED_0A_OFFSET                                            0x0000000000000000
276 #define TX_MSDU_START_RESERVED_0A_LSB                                               27
277 #define TX_MSDU_START_RESERVED_0A_MSB                                               31
278 #define TX_MSDU_START_RESERVED_0A_MASK                                              0x00000000f8000000
279 
280 
281 /* Description		TSO_ENABLE
282 
283 			Enable transmit segmentation offload.
284 
285 			In case MSDU_EXTENSION is used, TXDMA gets the setting for
286 			 this bit from that descriptor.
287 			In case MSDU_EXTENSION is NOT use, TXDMA gets the setting
288 			 for this bit from an internal SW programmable register.
289 
290 			 <legal all>
291 */
292 
293 #define TX_MSDU_START_TSO_ENABLE_OFFSET                                             0x0000000000000000
294 #define TX_MSDU_START_TSO_ENABLE_LSB                                                32
295 #define TX_MSDU_START_TSO_ENABLE_MSB                                                32
296 #define TX_MSDU_START_TSO_ENABLE_MASK                                               0x0000000100000000
297 
298 
299 /* Description		RESERVED_1A
300 
301 			FW will set to 0, MAC will ignore.  <legal 0>
302 */
303 
304 #define TX_MSDU_START_RESERVED_1A_OFFSET                                            0x0000000000000000
305 #define TX_MSDU_START_RESERVED_1A_LSB                                               33
306 #define TX_MSDU_START_RESERVED_1A_MSB                                               38
307 #define TX_MSDU_START_RESERVED_1A_MASK                                              0x0000007e00000000
308 
309 
310 /* Description		TCP_FLAG
311 
312 			TCP flags
313 			{NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}<legal all>
314 */
315 
316 #define TX_MSDU_START_TCP_FLAG_OFFSET                                               0x0000000000000000
317 #define TX_MSDU_START_TCP_FLAG_LSB                                                  39
318 #define TX_MSDU_START_TCP_FLAG_MSB                                                  47
319 #define TX_MSDU_START_TCP_FLAG_MASK                                                 0x0000ff8000000000
320 
321 
322 /* Description		TCP_FLAG_MASK
323 
324 			TCP flag mask. Tcp_flag is inserted into the header based
325 			 on the mask, if TSO is enabled
326 */
327 
328 #define TX_MSDU_START_TCP_FLAG_MASK_OFFSET                                          0x0000000000000000
329 #define TX_MSDU_START_TCP_FLAG_MASK_LSB                                             48
330 #define TX_MSDU_START_TCP_FLAG_MASK_MSB                                             56
331 #define TX_MSDU_START_TCP_FLAG_MASK_MASK                                            0x01ff000000000000
332 
333 
334 /* Description		MESH_ENABLE
335 
336 			If set to 1:
337 
338 			* For raw WiFi frames, this indicates transmission to a
339 			mesh STA but is ignored by HW
340 
341 			* For native WiFi frames, this is used to indicate to TX
342 			 OLE that a 'Mesh Control' field is present between the
343 			header and the LLC
344 */
345 
346 #define TX_MSDU_START_MESH_ENABLE_OFFSET                                            0x0000000000000000
347 #define TX_MSDU_START_MESH_ENABLE_LSB                                               57
348 #define TX_MSDU_START_MESH_ENABLE_MSB                                               57
349 #define TX_MSDU_START_MESH_ENABLE_MASK                                              0x0200000000000000
350 
351 
352 /* Description		RESERVED_1B
353 
354 			FW will set to 0, MAC will ignore.  <legal 0>
355 */
356 
357 #define TX_MSDU_START_RESERVED_1B_OFFSET                                            0x0000000000000000
358 #define TX_MSDU_START_RESERVED_1B_LSB                                               58
359 #define TX_MSDU_START_RESERVED_1B_MSB                                               63
360 #define TX_MSDU_START_RESERVED_1B_MASK                                              0xfc00000000000000
361 
362 
363 /* Description		L2_LENGTH
364 
365 			L2 length for the msdu, if TSO is enabled <legal all>
366 */
367 
368 #define TX_MSDU_START_L2_LENGTH_OFFSET                                              0x0000000000000008
369 #define TX_MSDU_START_L2_LENGTH_LSB                                                 0
370 #define TX_MSDU_START_L2_LENGTH_MSB                                                 15
371 #define TX_MSDU_START_L2_LENGTH_MASK                                                0x000000000000ffff
372 
373 
374 /* Description		IP_LENGTH
375 
376 			IP length for the msdu, if TSO is enabled <legal all>
377 */
378 
379 #define TX_MSDU_START_IP_LENGTH_OFFSET                                              0x0000000000000008
380 #define TX_MSDU_START_IP_LENGTH_LSB                                                 16
381 #define TX_MSDU_START_IP_LENGTH_MSB                                                 31
382 #define TX_MSDU_START_IP_LENGTH_MASK                                                0x00000000ffff0000
383 
384 
385 /* Description		TCP_SEQ_NUMBER
386 
387 			Tcp_seq_number for the msdu, if TSO is enabled <legal all>
388 
389 */
390 
391 #define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET                                         0x0000000000000008
392 #define TX_MSDU_START_TCP_SEQ_NUMBER_LSB                                            32
393 #define TX_MSDU_START_TCP_SEQ_NUMBER_MSB                                            63
394 #define TX_MSDU_START_TCP_SEQ_NUMBER_MASK                                           0xffffffff00000000
395 
396 
397 /* Description		IP_IDENTIFICATION
398 
399 			IP_identification for the msdu, if TSO is enabled <legal
400 			 all>
401 */
402 
403 #define TX_MSDU_START_IP_IDENTIFICATION_OFFSET                                      0x0000000000000010
404 #define TX_MSDU_START_IP_IDENTIFICATION_LSB                                         0
405 #define TX_MSDU_START_IP_IDENTIFICATION_MSB                                         15
406 #define TX_MSDU_START_IP_IDENTIFICATION_MASK                                        0x000000000000ffff
407 
408 
409 /* Description		CHECKSUM_OFFSET
410 
411 			The calculated checksum from start offset to end offset
412 			will be added to the checksum at the offset given by this
413 			 field<legal all>
414 */
415 
416 #define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET                                        0x0000000000000010
417 #define TX_MSDU_START_CHECKSUM_OFFSET_LSB                                           16
418 #define TX_MSDU_START_CHECKSUM_OFFSET_MSB                                           28
419 #define TX_MSDU_START_CHECKSUM_OFFSET_MASK                                          0x000000001fff0000
420 
421 
422 /* Description		PARTIAL_CHECKSUM_EN
423 
424 			Enable Partial Checksum, MAV feature
425 */
426 
427 #define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET                                    0x0000000000000010
428 #define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB                                       29
429 #define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB                                       29
430 #define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK                                      0x0000000020000000
431 
432 
433 /* Description		RESERVED_4
434 
435 			<legal 0>
436 */
437 
438 #define TX_MSDU_START_RESERVED_4_OFFSET                                             0x0000000000000010
439 #define TX_MSDU_START_RESERVED_4_LSB                                                30
440 #define TX_MSDU_START_RESERVED_4_MSB                                                31
441 #define TX_MSDU_START_RESERVED_4_MASK                                               0x00000000c0000000
442 
443 
444 /* Description		PAYLOAD_START_OFFSET
445 
446 			L4 checksum calculations will start fromt this offset
447 			<legal all>
448 */
449 
450 #define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET                                   0x0000000000000010
451 #define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB                                      32
452 #define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB                                      45
453 #define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK                                     0x00003fff00000000
454 
455 
456 /* Description		RESERVED_5A
457 
458 			<legal 0>
459 */
460 
461 #define TX_MSDU_START_RESERVED_5A_OFFSET                                            0x0000000000000010
462 #define TX_MSDU_START_RESERVED_5A_LSB                                               46
463 #define TX_MSDU_START_RESERVED_5A_MSB                                               47
464 #define TX_MSDU_START_RESERVED_5A_MASK                                              0x0000c00000000000
465 
466 
467 /* Description		PAYLOAD_END_OFFSET
468 
469 			L4 checksum calculations will end at this offset.
470 			<legal all>
471 */
472 
473 #define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET                                     0x0000000000000010
474 #define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB                                        48
475 #define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB                                        61
476 #define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK                                       0x3fff000000000000
477 
478 
479 /* Description		RESERVED_5B
480 
481 			<legal 0>
482 */
483 
484 #define TX_MSDU_START_RESERVED_5B_OFFSET                                            0x0000000000000010
485 #define TX_MSDU_START_RESERVED_5B_LSB                                               62
486 #define TX_MSDU_START_RESERVED_5B_MSB                                               63
487 #define TX_MSDU_START_RESERVED_5B_MASK                                              0xc000000000000000
488 
489 
490 /* Description		UDP_LENGTH
491 
492 			This field indicates UDP length/UDP lite checksum coverage
493 			 field to be used by L4 checksum engine in case TSO is enabled
494 			 for UDP/UDP lite respectively
495 			<legal all>
496 */
497 
498 #define TX_MSDU_START_UDP_LENGTH_OFFSET                                             0x0000000000000018
499 #define TX_MSDU_START_UDP_LENGTH_LSB                                                0
500 #define TX_MSDU_START_UDP_LENGTH_MSB                                                15
501 #define TX_MSDU_START_UDP_LENGTH_MASK                                               0x000000000000ffff
502 
503 
504 /* Description		RESERVED_6
505 
506 			<legal 0>
507 */
508 
509 #define TX_MSDU_START_RESERVED_6_OFFSET                                             0x0000000000000018
510 #define TX_MSDU_START_RESERVED_6_LSB                                                16
511 #define TX_MSDU_START_RESERVED_6_MSB                                                31
512 #define TX_MSDU_START_RESERVED_6_MASK                                               0x00000000ffff0000
513 
514 
515 /* Description		TLV64_PADDING
516 
517 			Automatic DWORD padding inserted while converting TLV32
518 			to TLV64 for 64 bit ARCH
519 			<legal 0>
520 */
521 
522 #define TX_MSDU_START_TLV64_PADDING_OFFSET                                          0x0000000000000018
523 #define TX_MSDU_START_TLV64_PADDING_LSB                                             32
524 #define TX_MSDU_START_TLV64_PADDING_MSB                                             63
525 #define TX_MSDU_START_TLV64_PADDING_MASK                                            0xffffffff00000000
526 
527 
528 
529 #endif   // TX_MSDU_START
530