1 /*
2  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef _TX_MSDU_EXTENSION_H_
18 #define _TX_MSDU_EXTENSION_H_
19 #if !defined(__ASSEMBLER__)
20 #endif
21 
22 #define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18
23 
24 
25 struct tx_msdu_extension {
26 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
27              uint32_t tso_enable                                              :  1, // [0:0]
28                       reserved_0a                                             :  6, // [6:1]
29                       tcp_flag                                                :  9, // [15:7]
30                       tcp_flag_mask                                           :  9, // [24:16]
31                       reserved_0b                                             :  7; // [31:25]
32              uint32_t l2_length                                               : 16, // [15:0]
33                       ip_length                                               : 16; // [31:16]
34              uint32_t tcp_seq_number                                          : 32; // [31:0]
35              uint32_t ip_identification                                       : 16, // [15:0]
36                       udp_length                                              : 16; // [31:16]
37              uint32_t checksum_offset                                         : 14, // [13:0]
38                       partial_checksum_en                                     :  1, // [14:14]
39                       reserved_4a                                             :  1, // [15:15]
40                       payload_start_offset                                    : 14, // [29:16]
41                       reserved_4b                                             :  2; // [31:30]
42              uint32_t payload_end_offset                                      : 14, // [13:0]
43                       reserved_5a                                             :  2, // [15:14]
44                       wds                                                     :  1, // [16:16]
45                       reserved_5b                                             : 15; // [31:17]
46              uint32_t buf0_ptr_31_0                                           : 32; // [31:0]
47              uint32_t buf0_ptr_39_32                                          :  8, // [7:0]
48                       extn_override                                           :  1, // [8:8]
49                       encap_type                                              :  2, // [10:9]
50                       encrypt_type                                            :  4, // [14:11]
51                       tqm_no_drop                                             :  1, // [15:15]
52                       buf0_len                                                : 16; // [31:16]
53              uint32_t buf1_ptr_31_0                                           : 32; // [31:0]
54              uint32_t buf1_ptr_39_32                                          :  8, // [7:0]
55                       epd                                                     :  1, // [8:8]
56                       mesh_enable                                             :  2, // [10:9]
57                       reserved_9a                                             :  5, // [15:11]
58                       buf1_len                                                : 16; // [31:16]
59              uint32_t buf2_ptr_31_0                                           : 32; // [31:0]
60              uint32_t buf2_ptr_39_32                                          :  8, // [7:0]
61                       dscp_tid_table_num                                      :  6, // [13:8]
62                       reserved_11a                                            :  2, // [15:14]
63                       buf2_len                                                : 16; // [31:16]
64              uint32_t buf3_ptr_31_0                                           : 32; // [31:0]
65              uint32_t buf3_ptr_39_32                                          :  8, // [7:0]
66                       reserved_13a                                            :  8, // [15:8]
67                       buf3_len                                                : 16; // [31:16]
68              uint32_t buf4_ptr_31_0                                           : 32; // [31:0]
69              uint32_t buf4_ptr_39_32                                          :  8, // [7:0]
70                       reserved_15a                                            :  8, // [15:8]
71                       buf4_len                                                : 16; // [31:16]
72              uint32_t buf5_ptr_31_0                                           : 32; // [31:0]
73              uint32_t buf5_ptr_39_32                                          :  8, // [7:0]
74                       reserved_17a                                            :  8, // [15:8]
75                       buf5_len                                                : 16; // [31:16]
76 #else
77              uint32_t reserved_0b                                             :  7, // [31:25]
78                       tcp_flag_mask                                           :  9, // [24:16]
79                       tcp_flag                                                :  9, // [15:7]
80                       reserved_0a                                             :  6, // [6:1]
81                       tso_enable                                              :  1; // [0:0]
82              uint32_t ip_length                                               : 16, // [31:16]
83                       l2_length                                               : 16; // [15:0]
84              uint32_t tcp_seq_number                                          : 32; // [31:0]
85              uint32_t udp_length                                              : 16, // [31:16]
86                       ip_identification                                       : 16; // [15:0]
87              uint32_t reserved_4b                                             :  2, // [31:30]
88                       payload_start_offset                                    : 14, // [29:16]
89                       reserved_4a                                             :  1, // [15:15]
90                       partial_checksum_en                                     :  1, // [14:14]
91                       checksum_offset                                         : 14; // [13:0]
92              uint32_t reserved_5b                                             : 15, // [31:17]
93                       wds                                                     :  1, // [16:16]
94                       reserved_5a                                             :  2, // [15:14]
95                       payload_end_offset                                      : 14; // [13:0]
96              uint32_t buf0_ptr_31_0                                           : 32; // [31:0]
97              uint32_t buf0_len                                                : 16, // [31:16]
98                       tqm_no_drop                                             :  1, // [15:15]
99                       encrypt_type                                            :  4, // [14:11]
100                       encap_type                                              :  2, // [10:9]
101                       extn_override                                           :  1, // [8:8]
102                       buf0_ptr_39_32                                          :  8; // [7:0]
103              uint32_t buf1_ptr_31_0                                           : 32; // [31:0]
104              uint32_t buf1_len                                                : 16, // [31:16]
105                       reserved_9a                                             :  5, // [15:11]
106                       mesh_enable                                             :  2, // [10:9]
107                       epd                                                     :  1, // [8:8]
108                       buf1_ptr_39_32                                          :  8; // [7:0]
109              uint32_t buf2_ptr_31_0                                           : 32; // [31:0]
110              uint32_t buf2_len                                                : 16, // [31:16]
111                       reserved_11a                                            :  2, // [15:14]
112                       dscp_tid_table_num                                      :  6, // [13:8]
113                       buf2_ptr_39_32                                          :  8; // [7:0]
114              uint32_t buf3_ptr_31_0                                           : 32; // [31:0]
115              uint32_t buf3_len                                                : 16, // [31:16]
116                       reserved_13a                                            :  8, // [15:8]
117                       buf3_ptr_39_32                                          :  8; // [7:0]
118              uint32_t buf4_ptr_31_0                                           : 32; // [31:0]
119              uint32_t buf4_len                                                : 16, // [31:16]
120                       reserved_15a                                            :  8, // [15:8]
121                       buf4_ptr_39_32                                          :  8; // [7:0]
122              uint32_t buf5_ptr_31_0                                           : 32; // [31:0]
123              uint32_t buf5_len                                                : 16, // [31:16]
124                       reserved_17a                                            :  8, // [15:8]
125                       buf5_ptr_39_32                                          :  8; // [7:0]
126 #endif
127 };
128 
129 
130 /* Description		TSO_ENABLE
131 
132 			Enable transmit segmentation offload <legal all>
133 */
134 
135 #define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET                                         0x00000000
136 #define TX_MSDU_EXTENSION_TSO_ENABLE_LSB                                            0
137 #define TX_MSDU_EXTENSION_TSO_ENABLE_MSB                                            0
138 #define TX_MSDU_EXTENSION_TSO_ENABLE_MASK                                           0x00000001
139 
140 
141 /* Description		RESERVED_0A
142 
143 			FW will set to 0, MAC will ignore.  <legal 0>
144 */
145 
146 #define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET                                        0x00000000
147 #define TX_MSDU_EXTENSION_RESERVED_0A_LSB                                           1
148 #define TX_MSDU_EXTENSION_RESERVED_0A_MSB                                           6
149 #define TX_MSDU_EXTENSION_RESERVED_0A_MASK                                          0x0000007e
150 
151 
152 /* Description		TCP_FLAG
153 
154 			TCP flags
155 			{NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}<legal all>
156 */
157 
158 #define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET                                           0x00000000
159 #define TX_MSDU_EXTENSION_TCP_FLAG_LSB                                              7
160 #define TX_MSDU_EXTENSION_TCP_FLAG_MSB                                              15
161 #define TX_MSDU_EXTENSION_TCP_FLAG_MASK                                             0x0000ff80
162 
163 
164 /* Description		TCP_FLAG_MASK
165 
166 			TCP flag mask. Tcp_flag is inserted into the header based
167 			 on the mask, if TSO is enabled
168 */
169 
170 #define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET                                      0x00000000
171 #define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB                                         16
172 #define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB                                         24
173 #define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK                                        0x01ff0000
174 
175 
176 /* Description		RESERVED_0B
177 
178 			FW will set to 0, MAC will ignore.  <legal 0>
179 */
180 
181 #define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET                                        0x00000000
182 #define TX_MSDU_EXTENSION_RESERVED_0B_LSB                                           25
183 #define TX_MSDU_EXTENSION_RESERVED_0B_MSB                                           31
184 #define TX_MSDU_EXTENSION_RESERVED_0B_MASK                                          0xfe000000
185 
186 
187 /* Description		L2_LENGTH
188 
189 			L2 length for the msdu, if TSO is enabled <legal all>
190 */
191 
192 #define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET                                          0x00000004
193 #define TX_MSDU_EXTENSION_L2_LENGTH_LSB                                             0
194 #define TX_MSDU_EXTENSION_L2_LENGTH_MSB                                             15
195 #define TX_MSDU_EXTENSION_L2_LENGTH_MASK                                            0x0000ffff
196 
197 
198 /* Description		IP_LENGTH
199 
200 			IP length for the msdu, if TSO is enabled <legal all>
201 */
202 
203 #define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET                                          0x00000004
204 #define TX_MSDU_EXTENSION_IP_LENGTH_LSB                                             16
205 #define TX_MSDU_EXTENSION_IP_LENGTH_MSB                                             31
206 #define TX_MSDU_EXTENSION_IP_LENGTH_MASK                                            0xffff0000
207 
208 
209 /* Description		TCP_SEQ_NUMBER
210 
211 			Tcp_seq_number for the msdu, if TSO is enabled <legal all>
212 
213 */
214 
215 #define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET                                     0x00000008
216 #define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB                                        0
217 #define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB                                        31
218 #define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK                                       0xffffffff
219 
220 
221 /* Description		IP_IDENTIFICATION
222 
223 			IP_identification for the msdu, if TSO is enabled <legal
224 			 all>
225 */
226 
227 #define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET                                  0x0000000c
228 #define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB                                     0
229 #define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB                                     15
230 #define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK                                    0x0000ffff
231 
232 
233 /* Description		UDP_LENGTH
234 
235 			TXDMA is copies this field into MSDU START TLV
236 */
237 
238 #define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET                                         0x0000000c
239 #define TX_MSDU_EXTENSION_UDP_LENGTH_LSB                                            16
240 #define TX_MSDU_EXTENSION_UDP_LENGTH_MSB                                            31
241 #define TX_MSDU_EXTENSION_UDP_LENGTH_MASK                                           0xffff0000
242 
243 
244 /* Description		CHECKSUM_OFFSET
245 
246 			The calculated checksum from start offset to end offset
247 			will be added to the checksum at the offset given by this
248 			 field<legal all>
249 */
250 
251 #define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET                                    0x00000010
252 #define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB                                       0
253 #define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB                                       13
254 #define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK                                      0x00003fff
255 
256 
257 /* Description		PARTIAL_CHECKSUM_EN
258 
259 			Partial Checksum Enable Bit.
260 			<legal 0-1>
261 */
262 
263 #define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET                                0x00000010
264 #define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB                                   14
265 #define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB                                   14
266 #define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK                                  0x00004000
267 
268 
269 /* Description		RESERVED_4A
270 
271 			<Legal 0>
272 */
273 
274 #define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET                                        0x00000010
275 #define TX_MSDU_EXTENSION_RESERVED_4A_LSB                                           15
276 #define TX_MSDU_EXTENSION_RESERVED_4A_MSB                                           15
277 #define TX_MSDU_EXTENSION_RESERVED_4A_MASK                                          0x00008000
278 
279 
280 /* Description		PAYLOAD_START_OFFSET
281 
282 			L4 checksum calculations will start fromt this offset
283 			<Legal all>
284 */
285 
286 #define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET                               0x00000010
287 #define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB                                  16
288 #define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB                                  29
289 #define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK                                 0x3fff0000
290 
291 
292 /* Description		RESERVED_4B
293 
294 			<Legal 0>
295 */
296 
297 #define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET                                        0x00000010
298 #define TX_MSDU_EXTENSION_RESERVED_4B_LSB                                           30
299 #define TX_MSDU_EXTENSION_RESERVED_4B_MSB                                           31
300 #define TX_MSDU_EXTENSION_RESERVED_4B_MASK                                          0xc0000000
301 
302 
303 /* Description		PAYLOAD_END_OFFSET
304 
305 			L4 checksum calculations will end at this offset.
306 			<Legal all>
307 */
308 
309 #define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET                                 0x00000014
310 #define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB                                    0
311 #define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB                                    13
312 #define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK                                   0x00003fff
313 
314 
315 /* Description		RESERVED_5A
316 
317 			<Legal 0>
318 */
319 
320 #define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET                                        0x00000014
321 #define TX_MSDU_EXTENSION_RESERVED_5A_LSB                                           14
322 #define TX_MSDU_EXTENSION_RESERVED_5A_MSB                                           15
323 #define TX_MSDU_EXTENSION_RESERVED_5A_MASK                                          0x0000c000
324 
325 
326 /* Description		WDS
327 
328 			If set the current packet is 4-address frame.  Required
329 			because an aggregate can include some frames with 3 address
330 			 format and other frames with 4 address format.  Used by
331 			 the OLE during encapsulation.
332 			Note: there is also global wds tx control in the TX_PEER_ENTRY
333 
334 			<legal all>
335 */
336 
337 #define TX_MSDU_EXTENSION_WDS_OFFSET                                                0x00000014
338 #define TX_MSDU_EXTENSION_WDS_LSB                                                   16
339 #define TX_MSDU_EXTENSION_WDS_MSB                                                   16
340 #define TX_MSDU_EXTENSION_WDS_MASK                                                  0x00010000
341 
342 
343 /* Description		RESERVED_5B
344 
345 			<Legal 0>
346 */
347 
348 #define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET                                        0x00000014
349 #define TX_MSDU_EXTENSION_RESERVED_5B_LSB                                           17
350 #define TX_MSDU_EXTENSION_RESERVED_5B_MSB                                           31
351 #define TX_MSDU_EXTENSION_RESERVED_5B_MASK                                          0xfffe0000
352 
353 
354 /* Description		BUF0_PTR_31_0
355 
356 			Lower 32 bits of the first buffer pointer
357 
358 			NOTE: SW/FW manages the 'cookie' info related to this buffer
359 			 together with the 'cookie' info for this MSDU_EXTENSION
360 			 descriptor
361 			<legal all>
362 */
363 
364 #define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET                                      0x00000018
365 #define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB                                         0
366 #define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB                                         31
367 #define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK                                        0xffffffff
368 
369 
370 /* Description		BUF0_PTR_39_32
371 
372 			Upper 8 bits of the first buffer pointer <legal all>
373 */
374 
375 #define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET                                     0x0000001c
376 #define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB                                        0
377 #define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB                                        7
378 #define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK                                       0x000000ff
379 
380 
381 /* Description		EXTN_OVERRIDE
382 
383 			Field only used by TCL
384 
385 			When set, the fields encap_type, Encrypt_type, TQM_NO_DROP,
386 			EPD and mesh_enable are valid and override any TCL per-bank
387 			 registers specifying these values (except TQM_NO_DROP).
388 
389 
390 			When clear, the values for encap_type, Encrypt_type, EPD,
391 			mesh_enable and DSCP_TID_TABLE_NUM are taken from per-bank
392 			 registers in TCL and TQM_NO_DROP is not being requested
393 			 by SW.
394 
395 			<legal all>
396 */
397 
398 #define TX_MSDU_EXTENSION_EXTN_OVERRIDE_OFFSET                                      0x0000001c
399 #define TX_MSDU_EXTENSION_EXTN_OVERRIDE_LSB                                         8
400 #define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MSB                                         8
401 #define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MASK                                        0x00000100
402 
403 
404 /* Description		ENCAP_TYPE
405 
406 			Field only used by TCL, only valid if Extn_override is set.
407 
408 
409 			Indicates the encapsulation that HW will perform:
410 			<enum 0 RAW> No encapsulation
411 			<enum 1 Native_WiFi>
412 			<enum 2 Ethernet> Ethernet 2 (DIX)  or 802.3 (uses SNAP/LLC)
413 
414 			<enum 3 802_3> DO NOT USE. Indicate Ethernet
415 
416 			Used by the OLE during encapsulation.
417 			<legal all>
418 */
419 
420 #define TX_MSDU_EXTENSION_ENCAP_TYPE_OFFSET                                         0x0000001c
421 #define TX_MSDU_EXTENSION_ENCAP_TYPE_LSB                                            9
422 #define TX_MSDU_EXTENSION_ENCAP_TYPE_MSB                                            10
423 #define TX_MSDU_EXTENSION_ENCAP_TYPE_MASK                                           0x00000600
424 
425 
426 /* Description		ENCRYPT_TYPE
427 
428 			Field only used by TCL, only valid if Extn_override is set
429 			 and encap_type = RAW
430 
431 			Indicates type of decrypt cipher used (as defined in the
432 			 peer entry)
433 			<enum 0 wep_40> WEP 40-bit
434 			<enum 1 wep_104> WEP 104-bit
435 			<enum 2 tkip_no_mic> TKIP without MIC
436 			<enum 3 wep_128> WEP 128-bit
437 			<enum 4 tkip_with_mic> TKIP with MIC
438 			<enum 5 wapi> WAPI
439 			<enum 6 aes_ccmp_128> AES CCMP 128
440 			<enum 7 no_cipher> No crypto
441 			<enum 8 aes_ccmp_256> AES CCMP 256
442 			<enum 9 aes_gcmp_128> AES CCMP 128
443 			<enum 10 aes_gcmp_256> AES CCMP 256
444 			<enum 11 wapi_gcm_sm4> WAPI GCM SM4
445 
446 			<enum 12 wep_varied_width> DO not use... Only for higher
447 			 layer modules..
448 			<legal 0-12>
449 */
450 
451 #define TX_MSDU_EXTENSION_ENCRYPT_TYPE_OFFSET                                       0x0000001c
452 #define TX_MSDU_EXTENSION_ENCRYPT_TYPE_LSB                                          11
453 #define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MSB                                          14
454 #define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MASK                                         0x00007800
455 
456 
457 /* Description		TQM_NO_DROP
458 
459 			Field only used by TCL, only valid if Extn_override is set.
460 
461 
462 			This bit is used to stop TQM from dropping MSDUs while adding
463 			 them to MSDU flows1'b1: Do not drop MSDU when any of the
464 			 threshold value is met while adding MSDU in a flow1'b1:
465 			Drop MSDU when any of the threshold value is met while adding
466 			 MSDU in a flow
467 			Note: TCL can also have CCE/LCE rules to set 'TQM_NO_DROP'
468 			which will be OR'd to this value.
469 			<legal all>
470 */
471 
472 #define TX_MSDU_EXTENSION_TQM_NO_DROP_OFFSET                                        0x0000001c
473 #define TX_MSDU_EXTENSION_TQM_NO_DROP_LSB                                           15
474 #define TX_MSDU_EXTENSION_TQM_NO_DROP_MSB                                           15
475 #define TX_MSDU_EXTENSION_TQM_NO_DROP_MASK                                          0x00008000
476 
477 
478 /* Description		BUF0_LEN
479 
480 			Length of the first buffer <legal all>
481 */
482 
483 #define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET                                           0x0000001c
484 #define TX_MSDU_EXTENSION_BUF0_LEN_LSB                                              16
485 #define TX_MSDU_EXTENSION_BUF0_LEN_MSB                                              31
486 #define TX_MSDU_EXTENSION_BUF0_LEN_MASK                                             0xffff0000
487 
488 
489 /* Description		BUF1_PTR_31_0
490 
491 			Lower 32 bits of the second buffer pointer
492 
493 			NOTE: SW/FW manages the 'cookie' info related to this buffer
494 			 together with the 'cookie' info for this MSDU_EXTENSION
495 			 descriptor
496 			<legal all>
497 */
498 
499 #define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET                                      0x00000020
500 #define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB                                         0
501 #define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB                                         31
502 #define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK                                        0xffffffff
503 
504 
505 /* Description		BUF1_PTR_39_32
506 
507 			Upper 8 bits of the second buffer pointer <legal all>
508 */
509 
510 #define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET                                     0x00000024
511 #define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB                                        0
512 #define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB                                        7
513 #define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK                                       0x000000ff
514 
515 
516 /* Description		EPD
517 
518 			Field only used by TCL, only valid if Extn_override is set.
519 
520 
521 			When this bit is set then input packet is an EPD type
522 			<legal all>
523 */
524 
525 #define TX_MSDU_EXTENSION_EPD_OFFSET                                                0x00000024
526 #define TX_MSDU_EXTENSION_EPD_LSB                                                   8
527 #define TX_MSDU_EXTENSION_EPD_MSB                                                   8
528 #define TX_MSDU_EXTENSION_EPD_MASK                                                  0x00000100
529 
530 
531 /* Description		MESH_ENABLE
532 
533 			Field only used by TCL, only valid if Extn_override is set.
534 
535 
536 			If set to a non-zero value:
537 			* For raw WiFi frames, this indicates transmission to a
538 			mesh STA, enabling the interpretation of the 'Mesh Control
539 			 Present' bit (bit 8) of QoS Control (otherwise this bit
540 			 is ignored). The interpretation of the A-MSDU 'Length'
541 			field is decided by the e-numerations below.
542 			* For native WiFi frames, this indicates that a 'Mesh Control'
543 			field is present between the header and the LLC. The three
544 			 non-zero values are interchangeable.
545 
546 			<enum 0 MESH_DISABLE>
547 			<enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and includes
548 			 the length of Mesh Control.
549 			<enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and excludes
550 			 the length of Mesh Control.
551 			<enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian and
552 			 excludes the length of Mesh Control. This is 802.11s-compliant.
553 
554 			<legal 0-3>
555 */
556 
557 #define TX_MSDU_EXTENSION_MESH_ENABLE_OFFSET                                        0x00000024
558 #define TX_MSDU_EXTENSION_MESH_ENABLE_LSB                                           9
559 #define TX_MSDU_EXTENSION_MESH_ENABLE_MSB                                           10
560 #define TX_MSDU_EXTENSION_MESH_ENABLE_MASK                                          0x00000600
561 
562 
563 /* Description		RESERVED_9A
564 
565 			<Legal 0>
566 */
567 
568 #define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET                                        0x00000024
569 #define TX_MSDU_EXTENSION_RESERVED_9A_LSB                                           11
570 #define TX_MSDU_EXTENSION_RESERVED_9A_MSB                                           15
571 #define TX_MSDU_EXTENSION_RESERVED_9A_MASK                                          0x0000f800
572 
573 
574 /* Description		BUF1_LEN
575 
576 			Length of the second buffer <legal all>
577 */
578 
579 #define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET                                           0x00000024
580 #define TX_MSDU_EXTENSION_BUF1_LEN_LSB                                              16
581 #define TX_MSDU_EXTENSION_BUF1_LEN_MSB                                              31
582 #define TX_MSDU_EXTENSION_BUF1_LEN_MASK                                             0xffff0000
583 
584 
585 /* Description		BUF2_PTR_31_0
586 
587 			Lower 32 bits of the third buffer pointer
588 			NOTE: SW/FW manages the 'cookie' info related to this buffer
589 			 together with the 'cookie' info for this MSDU_EXTENSION
590 			 descriptor
591 			<legal all>
592 */
593 
594 #define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET                                      0x00000028
595 #define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB                                         0
596 #define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB                                         31
597 #define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK                                        0xffffffff
598 
599 
600 /* Description		BUF2_PTR_39_32
601 
602 			Upper 8 bits of the third buffer pointer <legal all>
603 */
604 
605 #define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET                                     0x0000002c
606 #define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB                                        0
607 #define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB                                        7
608 #define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK                                       0x000000ff
609 
610 
611 /* Description		DSCP_TID_TABLE_NUM
612 
613 			Field only used by TCL, only valid if Extn_override is set.
614 
615 
616 			This specifies the DSCP to TID mapping table to be used
617 			for the MSDU
618 			<legal all>
619 */
620 
621 #define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_OFFSET                                 0x0000002c
622 #define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_LSB                                    8
623 #define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MSB                                    13
624 #define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MASK                                   0x00003f00
625 
626 
627 /* Description		RESERVED_11A
628 
629 			<Legal 0>
630 */
631 
632 #define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET                                       0x0000002c
633 #define TX_MSDU_EXTENSION_RESERVED_11A_LSB                                          14
634 #define TX_MSDU_EXTENSION_RESERVED_11A_MSB                                          15
635 #define TX_MSDU_EXTENSION_RESERVED_11A_MASK                                         0x0000c000
636 
637 
638 /* Description		BUF2_LEN
639 
640 			Length of the third buffer <legal all>
641 */
642 
643 #define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET                                           0x0000002c
644 #define TX_MSDU_EXTENSION_BUF2_LEN_LSB                                              16
645 #define TX_MSDU_EXTENSION_BUF2_LEN_MSB                                              31
646 #define TX_MSDU_EXTENSION_BUF2_LEN_MASK                                             0xffff0000
647 
648 
649 /* Description		BUF3_PTR_31_0
650 
651 			Lower 32 bits of the fourth buffer pointer
652 
653 			NOTE: SW/FW manages the 'cookie' info related to this buffer
654 			 together with the 'cookie' info for this MSDU_EXTENSION
655 			 descriptor
656 			 <legal all>
657 */
658 
659 #define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET                                      0x00000030
660 #define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB                                         0
661 #define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB                                         31
662 #define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK                                        0xffffffff
663 
664 
665 /* Description		BUF3_PTR_39_32
666 
667 			Upper 8 bits of the fourth buffer pointer <legal all>
668 */
669 
670 #define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET                                     0x00000034
671 #define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB                                        0
672 #define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB                                        7
673 #define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK                                       0x000000ff
674 
675 
676 /* Description		RESERVED_13A
677 
678 			<Legal 0>
679 */
680 
681 #define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET                                       0x00000034
682 #define TX_MSDU_EXTENSION_RESERVED_13A_LSB                                          8
683 #define TX_MSDU_EXTENSION_RESERVED_13A_MSB                                          15
684 #define TX_MSDU_EXTENSION_RESERVED_13A_MASK                                         0x0000ff00
685 
686 
687 /* Description		BUF3_LEN
688 
689 			Length of the fourth buffer <legal all>
690 */
691 
692 #define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET                                           0x00000034
693 #define TX_MSDU_EXTENSION_BUF3_LEN_LSB                                              16
694 #define TX_MSDU_EXTENSION_BUF3_LEN_MSB                                              31
695 #define TX_MSDU_EXTENSION_BUF3_LEN_MASK                                             0xffff0000
696 
697 
698 /* Description		BUF4_PTR_31_0
699 
700 			Lower 32 bits of the fifth buffer pointer
701 
702 			NOTE: SW/FW manages the 'cookie' info related to this buffer
703 			 together with the 'cookie' info for this MSDU_EXTENSION
704 			 descriptor
705 			<legal all>
706 */
707 
708 #define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET                                      0x00000038
709 #define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB                                         0
710 #define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB                                         31
711 #define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK                                        0xffffffff
712 
713 
714 /* Description		BUF4_PTR_39_32
715 
716 			Upper 8 bits of the fifth buffer pointer <legal all>
717 */
718 
719 #define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET                                     0x0000003c
720 #define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB                                        0
721 #define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB                                        7
722 #define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK                                       0x000000ff
723 
724 
725 /* Description		RESERVED_15A
726 
727 			<Legal 0>
728 */
729 
730 #define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET                                       0x0000003c
731 #define TX_MSDU_EXTENSION_RESERVED_15A_LSB                                          8
732 #define TX_MSDU_EXTENSION_RESERVED_15A_MSB                                          15
733 #define TX_MSDU_EXTENSION_RESERVED_15A_MASK                                         0x0000ff00
734 
735 
736 /* Description		BUF4_LEN
737 
738 			Length of the fifth buffer <legal all>
739 */
740 
741 #define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET                                           0x0000003c
742 #define TX_MSDU_EXTENSION_BUF4_LEN_LSB                                              16
743 #define TX_MSDU_EXTENSION_BUF4_LEN_MSB                                              31
744 #define TX_MSDU_EXTENSION_BUF4_LEN_MASK                                             0xffff0000
745 
746 
747 /* Description		BUF5_PTR_31_0
748 
749 			Lower 32 bits of the sixth buffer pointer
750 
751 			NOTE: SW/FW manages the 'cookie' info related to this buffer
752 			 together with the 'cookie' info for this MSDU_EXTENSION
753 			 descriptor
754 			 <legal all>
755 */
756 
757 #define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET                                      0x00000040
758 #define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB                                         0
759 #define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB                                         31
760 #define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK                                        0xffffffff
761 
762 
763 /* Description		BUF5_PTR_39_32
764 
765 			Upper 8 bits of the sixth buffer pointer <legal all>
766 */
767 
768 #define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET                                     0x00000044
769 #define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB                                        0
770 #define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB                                        7
771 #define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK                                       0x000000ff
772 
773 
774 /* Description		RESERVED_17A
775 
776 			<Legal 0>
777 */
778 
779 #define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET                                       0x00000044
780 #define TX_MSDU_EXTENSION_RESERVED_17A_LSB                                          8
781 #define TX_MSDU_EXTENSION_RESERVED_17A_MSB                                          15
782 #define TX_MSDU_EXTENSION_RESERVED_17A_MASK                                         0x0000ff00
783 
784 
785 /* Description		BUF5_LEN
786 
787 			Length of the sixth buffer <legal all>
788 */
789 
790 #define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET                                           0x00000044
791 #define TX_MSDU_EXTENSION_BUF5_LEN_LSB                                              16
792 #define TX_MSDU_EXTENSION_BUF5_LEN_MSB                                              31
793 #define TX_MSDU_EXTENSION_BUF5_LEN_MASK                                             0xffff0000
794 
795 
796 
797 #endif   // TX_MSDU_EXTENSION
798