1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _TX_FES_STATUS_END_H_ 18 #define _TX_FES_STATUS_END_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "phytx_abort_request_info.h" 23 #define NUM_OF_DWORDS_TX_FES_STATUS_END 22 24 25 #define NUM_OF_QWORDS_TX_FES_STATUS_END 11 26 27 28 struct tx_fes_status_end { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 uint32_t prot_coex_bt_tx_while_wlan_tx : 1, // [0:0] 31 prot_coex_bt_tx_while_wlan_rx : 1, // [1:1] 32 prot_coex_wan_tx_while_wlan_tx : 1, // [2:2] 33 prot_coex_wan_tx_while_wlan_rx : 1, // [3:3] 34 prot_coex_wlan_tx_while_wlan_tx : 1, // [4:4] 35 prot_coex_wlan_tx_while_wlan_rx : 1, // [5:5] 36 coex_bt_tx_while_wlan_tx : 1, // [6:6] 37 coex_bt_tx_while_wlan_rx : 1, // [7:7] 38 coex_wan_tx_while_wlan_tx : 1, // [8:8] 39 coex_wan_tx_while_wlan_rx : 1, // [9:9] 40 coex_wlan_tx_while_wlan_tx : 1, // [10:10] 41 coex_wlan_tx_while_wlan_rx : 1, // [11:11] 42 global_data_underflow_warning : 1, // [12:12] 43 global_fes_transmit_result : 4, // [16:13] 44 cbf_bw_received_valid : 1, // [17:17] 45 cbf_bw_received : 3, // [20:18] 46 actual_received_ack_type : 4, // [24:21] 47 sta_response_count : 6, // [30:25] 48 dpdtrain_done : 1; // [31:31] 49 struct phytx_abort_request_info phytx_abort_request_info_details; 50 uint16_t reserved_after_struct16 : 4, // [19:16] 51 brp_info_valid : 1, // [20:20] 52 reserved_1a : 6, // [26:21] 53 phytx_pkt_end_info_valid : 1, // [27:27] 54 phytx_abort_request_info_valid : 1, // [28:28] 55 fes_in_11ax_trigger_response_config : 1, // [29:29] 56 null_delim_inserted_before_mpdus : 1, // [30:30] 57 only_null_delim_sent : 1; // [31:31] 58 uint32_t start_of_frame_timestamp_15_0 : 16, // [15:0] 59 start_of_frame_timestamp_31_16 : 16; // [31:16] 60 uint32_t end_of_frame_timestamp_15_0 : 16, // [15:0] 61 end_of_frame_timestamp_31_16 : 16; // [31:16] 62 uint32_t terminate_ranging_sequence : 1, // [0:0] 63 reserved_4a : 7, // [7:1] 64 timing_status : 2, // [9:8] 65 response_type : 5, // [14:10] 66 r2r_end_status_to_follow : 1, // [15:15] 67 transmit_delay : 16; // [31:16] 68 uint32_t tx_group_delay : 12, // [11:0] 69 reserved_5a : 4, // [15:12] 70 tpc_dbg_info_cmn_15_0 : 16; // [31:16] 71 uint32_t tpc_dbg_info_cmn_31_16 : 16, // [15:0] 72 tpc_dbg_info_47_32 : 16; // [31:16] 73 uint32_t tpc_dbg_info_chn1_15_0 : 16, // [15:0] 74 tpc_dbg_info_chn1_31_16 : 16; // [31:16] 75 uint32_t tpc_dbg_info_chn1_47_32 : 16, // [15:0] 76 tpc_dbg_info_chn1_63_48 : 16; // [31:16] 77 uint32_t tpc_dbg_info_chn1_79_64 : 16, // [15:0] 78 tpc_dbg_info_chn2_15_0 : 16; // [31:16] 79 uint32_t tpc_dbg_info_chn2_31_16 : 16, // [15:0] 80 tpc_dbg_info_chn2_47_32 : 16; // [31:16] 81 uint32_t tpc_dbg_info_chn2_63_48 : 16, // [15:0] 82 tpc_dbg_info_chn2_79_64 : 16; // [31:16] 83 uint32_t phytx_tx_end_sw_info_15_0 : 16, // [15:0] 84 phytx_tx_end_sw_info_31_16 : 16; // [31:16] 85 uint32_t phytx_tx_end_sw_info_47_32 : 16, // [15:0] 86 phytx_tx_end_sw_info_63_48 : 16; // [31:16] 87 uint32_t beamform_masked_user_bitmap_15_0 : 16, // [15:0] 88 beamform_masked_user_bitmap_31_16 : 16; // [31:16] 89 uint32_t cbf_segment_request_mask : 8, // [7:0] 90 cbf_segment_sent_mask : 8, // [15:8] 91 highest_achieved_data_null_ratio : 5, // [20:16] 92 use_alt_power_sr : 1, // [21:21] 93 static_2_pwr_mode_status : 1, // [22:22] 94 obss_srg_opport_transmit_status : 1, // [23:23] 95 srp_based_transmit_status : 1, // [24:24] 96 obss_pd_based_transmit_status : 1, // [25:25] 97 beamform_masked_user_bitmap_36_32 : 5, // [30:26] 98 pdg_mpdu_ready : 1; // [31:31] 99 uint32_t pdg_mpdu_count : 16, // [15:0] 100 pdg_est_mpdu_tx_count : 16; // [31:16] 101 uint32_t pdg_overview_length : 24, // [23:0] 102 txop_duration : 7, // [30:24] 103 pdg_dropped_mpdu_warning : 1; // [31:31] 104 uint32_t packet_extension_a_factor : 2, // [1:0] 105 packet_extension_pe_disambiguity : 1, // [2:2] 106 packet_extension : 3, // [5:3] 107 fec_type : 1, // [6:6] 108 stbc : 1, // [7:7] 109 num_data_symbols : 16, // [23:8] 110 ru_size : 4, // [27:24] 111 reserved_17a : 4; // [31:28] 112 uint32_t num_ltf_symbols : 3, // [2:0] 113 ltf_size : 2, // [4:3] 114 cp_setting : 2, // [6:5] 115 reserved_18a : 5, // [11:7] 116 dcm : 1, // [12:12] 117 ldpc_extra_symbol : 1, // [13:13] 118 force_extra_symbol : 1, // [14:14] 119 reserved_18b : 1, // [15:15] 120 tx_pwr_shared : 8, // [23:16] 121 tx_pwr_unshared : 8; // [31:24] 122 uint32_t ranging_active_user_map : 16, // [15:0] 123 ranging_sent_dummy_tx : 1, // [16:16] 124 ranging_ftm_frame_sent : 1, // [17:17] 125 reserved_20a : 6, // [23:18] 126 cv_corr_status : 8; // [31:24] 127 uint32_t current_tx_duration : 16, // [15:0] 128 reserved_21a : 16; // [31:16] 129 #else 130 uint32_t dpdtrain_done : 1, // [31:31] 131 sta_response_count : 6, // [30:25] 132 actual_received_ack_type : 4, // [24:21] 133 cbf_bw_received : 3, // [20:18] 134 cbf_bw_received_valid : 1, // [17:17] 135 global_fes_transmit_result : 4, // [16:13] 136 global_data_underflow_warning : 1, // [12:12] 137 coex_wlan_tx_while_wlan_rx : 1, // [11:11] 138 coex_wlan_tx_while_wlan_tx : 1, // [10:10] 139 coex_wan_tx_while_wlan_rx : 1, // [9:9] 140 coex_wan_tx_while_wlan_tx : 1, // [8:8] 141 coex_bt_tx_while_wlan_rx : 1, // [7:7] 142 coex_bt_tx_while_wlan_tx : 1, // [6:6] 143 prot_coex_wlan_tx_while_wlan_rx : 1, // [5:5] 144 prot_coex_wlan_tx_while_wlan_tx : 1, // [4:4] 145 prot_coex_wan_tx_while_wlan_rx : 1, // [3:3] 146 prot_coex_wan_tx_while_wlan_tx : 1, // [2:2] 147 prot_coex_bt_tx_while_wlan_rx : 1, // [1:1] 148 prot_coex_bt_tx_while_wlan_tx : 1; // [0:0] 149 uint32_t only_null_delim_sent : 1, // [31:31] 150 null_delim_inserted_before_mpdus : 1, // [30:30] 151 fes_in_11ax_trigger_response_config : 1, // [29:29] 152 phytx_abort_request_info_valid : 1, // [28:28] 153 phytx_pkt_end_info_valid : 1, // [27:27] 154 reserved_1a : 6, // [26:21] 155 brp_info_valid : 1, // [20:20] 156 reserved_after_struct16 : 4; // [19:16] 157 struct phytx_abort_request_info phytx_abort_request_info_details; 158 uint32_t start_of_frame_timestamp_31_16 : 16, // [31:16] 159 start_of_frame_timestamp_15_0 : 16; // [15:0] 160 uint32_t end_of_frame_timestamp_31_16 : 16, // [31:16] 161 end_of_frame_timestamp_15_0 : 16; // [15:0] 162 uint32_t transmit_delay : 16, // [31:16] 163 r2r_end_status_to_follow : 1, // [15:15] 164 response_type : 5, // [14:10] 165 timing_status : 2, // [9:8] 166 reserved_4a : 7, // [7:1] 167 terminate_ranging_sequence : 1; // [0:0] 168 uint32_t tpc_dbg_info_cmn_15_0 : 16, // [31:16] 169 reserved_5a : 4, // [15:12] 170 tx_group_delay : 12; // [11:0] 171 uint32_t tpc_dbg_info_47_32 : 16, // [31:16] 172 tpc_dbg_info_cmn_31_16 : 16; // [15:0] 173 uint32_t tpc_dbg_info_chn1_31_16 : 16, // [31:16] 174 tpc_dbg_info_chn1_15_0 : 16; // [15:0] 175 uint32_t tpc_dbg_info_chn1_63_48 : 16, // [31:16] 176 tpc_dbg_info_chn1_47_32 : 16; // [15:0] 177 uint32_t tpc_dbg_info_chn2_15_0 : 16, // [31:16] 178 tpc_dbg_info_chn1_79_64 : 16; // [15:0] 179 uint32_t tpc_dbg_info_chn2_47_32 : 16, // [31:16] 180 tpc_dbg_info_chn2_31_16 : 16; // [15:0] 181 uint32_t tpc_dbg_info_chn2_79_64 : 16, // [31:16] 182 tpc_dbg_info_chn2_63_48 : 16; // [15:0] 183 uint32_t phytx_tx_end_sw_info_31_16 : 16, // [31:16] 184 phytx_tx_end_sw_info_15_0 : 16; // [15:0] 185 uint32_t phytx_tx_end_sw_info_63_48 : 16, // [31:16] 186 phytx_tx_end_sw_info_47_32 : 16; // [15:0] 187 uint32_t beamform_masked_user_bitmap_31_16 : 16, // [31:16] 188 beamform_masked_user_bitmap_15_0 : 16; // [15:0] 189 uint32_t pdg_mpdu_ready : 1, // [31:31] 190 beamform_masked_user_bitmap_36_32 : 5, // [30:26] 191 obss_pd_based_transmit_status : 1, // [25:25] 192 srp_based_transmit_status : 1, // [24:24] 193 obss_srg_opport_transmit_status : 1, // [23:23] 194 static_2_pwr_mode_status : 1, // [22:22] 195 use_alt_power_sr : 1, // [21:21] 196 highest_achieved_data_null_ratio : 5, // [20:16] 197 cbf_segment_sent_mask : 8, // [15:8] 198 cbf_segment_request_mask : 8; // [7:0] 199 uint32_t pdg_est_mpdu_tx_count : 16, // [31:16] 200 pdg_mpdu_count : 16; // [15:0] 201 uint32_t pdg_dropped_mpdu_warning : 1, // [31:31] 202 txop_duration : 7, // [30:24] 203 pdg_overview_length : 24; // [23:0] 204 uint32_t reserved_17a : 4, // [31:28] 205 ru_size : 4, // [27:24] 206 num_data_symbols : 16, // [23:8] 207 stbc : 1, // [7:7] 208 fec_type : 1, // [6:6] 209 packet_extension : 3, // [5:3] 210 packet_extension_pe_disambiguity : 1, // [2:2] 211 packet_extension_a_factor : 2; // [1:0] 212 uint32_t tx_pwr_unshared : 8, // [31:24] 213 tx_pwr_shared : 8, // [23:16] 214 reserved_18b : 1, // [15:15] 215 force_extra_symbol : 1, // [14:14] 216 ldpc_extra_symbol : 1, // [13:13] 217 dcm : 1, // [12:12] 218 reserved_18a : 5, // [11:7] 219 cp_setting : 2, // [6:5] 220 ltf_size : 2, // [4:3] 221 num_ltf_symbols : 3; // [2:0] 222 uint32_t cv_corr_status : 8, // [31:24] 223 reserved_20a : 6, // [23:18] 224 ranging_ftm_frame_sent : 1, // [17:17] 225 ranging_sent_dummy_tx : 1, // [16:16] 226 ranging_active_user_map : 16; // [15:0] 227 uint32_t reserved_21a : 16, // [31:16] 228 current_tx_duration : 16; // [15:0] 229 #endif 230 }; 231 232 233 /* Description PROT_COEX_BT_TX_WHILE_WLAN_TX 234 235 When set, a BT tx coex event started while wlan was in the 236 middle of TX a transmission. 237 238 Field set when coex_status_broadcast TLV received with bt 239 tx activity set and during WLAN tx 240 <legal all> 241 */ 242 243 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 244 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 245 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 246 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000001 247 248 249 /* Description PROT_COEX_BT_TX_WHILE_WLAN_RX 250 251 When set, a BT tx coex event started while wlan was in the 252 middle of TX a transmission. 253 254 Field set when coex broadcast TLV received with bt tx activity 255 set and during WLAN rx 256 <legal all> 257 */ 258 259 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 260 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_LSB 1 261 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MSB 1 262 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x0000000000000002 263 264 265 /* Description PROT_COEX_WAN_TX_WHILE_WLAN_TX 266 267 When set, a WAN tx coex event started while wlan was in 268 the middle of TX a transmission. 269 270 Field set when coex_status_broadcast TLV received with WAN 271 tx activity set and during WLAN tx 272 <legal all> 273 */ 274 275 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 276 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_LSB 2 277 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MSB 2 278 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000004 279 280 281 /* Description PROT_COEX_WAN_TX_WHILE_WLAN_RX 282 283 When set, a WAN tx coex event started while wlan was in 284 the middle of TX a transmission. 285 286 Field set when coex broadcast TLV received with WAN tx activity 287 set and during WLAN rx 288 <legal all> 289 */ 290 291 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 292 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_LSB 3 293 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MSB 3 294 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000008 295 296 297 /* Description PROT_COEX_WLAN_TX_WHILE_WLAN_TX 298 299 When set, a WLAN tx coex event started while wlan was in 300 the middle of TX a transmission. 301 302 Field set when coex_status_broadcast TLV received with WLAN 303 tx activity set and during WLAN tx 304 <legal all> 305 */ 306 307 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 308 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 4 309 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 4 310 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000010 311 312 313 /* Description PROT_COEX_WLAN_TX_WHILE_WLAN_RX 314 315 When set, a WLAN tx coex event started while wlan was in 316 the middle of TX a transmission. 317 318 Field set when coex broadcast TLV received with WLAN tx 319 activity set and during WLAN rx 320 <legal all> 321 */ 322 323 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 324 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 5 325 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 5 326 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000020 327 328 329 /* Description COEX_BT_TX_WHILE_WLAN_TX 330 331 When set, a BT tx coex event started while wlan was in the 332 middle of TX a transmission. 333 334 Field set when coex_status_broadcast TLV received with bt 335 tx activity set and during WLAN tx 336 <legal all> 337 */ 338 339 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 340 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_LSB 6 341 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MSB 6 342 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000040 343 344 345 /* Description COEX_BT_TX_WHILE_WLAN_RX 346 347 When set, a BT tx coex event started while wlan was in the 348 middle of TX a transmission. 349 350 Field set when coex broadcast TLV received with bt tx activity 351 set and during WLAN rx 352 <legal all> 353 */ 354 355 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 356 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_LSB 7 357 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MSB 7 358 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x0000000000000080 359 360 361 /* Description COEX_WAN_TX_WHILE_WLAN_TX 362 363 When set, a WAN tx coex event started while wlan was in 364 the middle of TX a transmission. 365 366 Field set when coex_status_broadcast TLV received with WAN 367 tx activity set and during WLAN tx 368 <legal all> 369 */ 370 371 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 372 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_LSB 8 373 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MSB 8 374 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000100 375 376 377 /* Description COEX_WAN_TX_WHILE_WLAN_RX 378 379 When set, a WAN tx coex event started while wlan was in 380 the middle of TX a transmission. 381 382 Field set when coex broadcast TLV received with WAN tx activity 383 set and during WLAN rx 384 <legal all> 385 */ 386 387 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 388 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_LSB 9 389 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MSB 9 390 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000200 391 392 393 /* Description COEX_WLAN_TX_WHILE_WLAN_TX 394 395 When set, a WLAN tx coex event started while wlan was in 396 the middle of TX a transmission. 397 398 Field set when coex_status_broadcast TLV received with WLAN 399 tx activity set and during WLAN tx 400 <legal all> 401 */ 402 403 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 404 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 10 405 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 10 406 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000400 407 408 409 /* Description COEX_WLAN_TX_WHILE_WLAN_RX 410 411 When set, a WLAN tx coex event started while wlan was in 412 the middle of TX a transmission. 413 414 Field set when coex broadcast TLV received with WLAN tx 415 activity set and during WLAN rx 416 <legal all> 417 */ 418 419 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 420 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 11 421 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 11 422 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000800 423 424 425 /* Description GLOBAL_DATA_UNDERFLOW_WARNING 426 427 Consumer: SCH/SW 428 Producer: TXPCU 429 430 When set, during transmission a data underflow occurred 431 for one or more users.<legal all> 432 */ 433 434 #define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 435 #define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 12 436 #define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 12 437 #define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000001000 438 439 440 /* Description GLOBAL_FES_TRANSMIT_RESULT 441 442 Consumer: SCH/SW 443 Producer: TXPCU 444 445 Global Transmit result, not per USER transmit result 446 447 Note: field "Response_type" indicates if the expected response 448 was MU related or not. 449 450 <enum 0 tx_ok> Successful transmission of entire Frame exchange 451 sequence 452 <enum 1 prot_resp_rx_timeout> 453 No Protection response frame received so timeout is triggered. 454 455 <enum 2 ppdu_resp_rx_timeout> No PPDU response frame received 456 so timeout is triggered. 457 <enum 3 resp_frame_crc_err> Response frame was received 458 with an invalid FCS. 459 <enum 4 SU_Response_type_mismatch> Response frame is received 460 without CRC error but it's not matched with expected SU_Response_type. 461 462 <enum 5 cbf_mimo_ctrl_mismatch> Set if CBF is received without 463 any error but the Nr, Nc, BW, type or token in VHT MIMO 464 control field is not matched with expected values which 465 are specified by TX_FES_SETUP.cbf_* fields. 466 <enum 7 MU_Response_type_mismatch> Response frame is received 467 without CRC error but it's not matched with expected SU_Response_type. 468 469 <enum 8 MU_Response_mpdu_not_valid> For this user, no MPDU 470 was received at all, or all received MPDUs had an FCS error. 471 472 <enum 9 MU_UL_not_enough_user_response> An MU UL response 473 reception was expected. That response came but the threshold 474 for number of successful user receptions was not met. 475 NOTE: This e-num will only be used in the TX_FES_STATUS_END 476 TLV... 477 <enum 10 Transmit_data_null_ratio_not_met> transmission 478 was successful and proper responses have been received. 479 But the required ratio between useful MPDU data and null 480 delimiters was not met as specified by field : Fes_continuation_ratio_threshold. 481 The FES (and potentially the SIFS burst) shall be terminated 482 by the SCHeduler 483 NOTE 1: This e-num will only be used in the TX_FES_STATUS_END 484 TLV... 485 486 <enum 6 TB_ranging_resp_timeout> A TB ranging response was 487 expected for a sounding TF, but the response did not arrive 488 and timeout is triggered. 489 NOTE: This e-num will only be used in the TX_FES_STATUS_END 490 TLV... 491 <enum 11 tb_ranging_resp_mismatch> A TB ranging response 492 was expected for a sounding TF, but the reception did not 493 match the expected response. 494 NOTE: This e-num will only be used in the TX_FES_STATUS_END 495 TLV... 496 497 <legal 0-11> 498 */ 499 500 #define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 501 #define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB 13 502 #define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB 16 503 #define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK 0x000000000001e000 504 505 506 /* Description CBF_BW_RECEIVED_VALID 507 508 Field only valid in case of SU reception. 509 In MU set to 0 510 511 When set, the cbf_bw_received field contains valid info 512 */ 513 514 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET 0x0000000000000000 515 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB 17 516 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB 17 517 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK 0x0000000000020000 518 519 520 /* Description CBF_BW_RECEIVED 521 522 Field only valid when cbf_bw_received_valid is set. 523 524 In MU set to 0 525 526 <enum 0 20_mhz>20 Mhz BW 527 <enum 1 40_mhz>40 Mhz BW 528 <enum 2 80_mhz>80 Mhz BW 529 <enum 3 160_mhz>160 Mhz BW 530 <enum 4 320_mhz>320 Mhz BW 531 <enum 5 240_mhz>240 Mhz BW 532 */ 533 534 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET 0x0000000000000000 535 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB 18 536 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB 20 537 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK 0x00000000001c0000 538 539 540 /* Description ACTUAL_RECEIVED_ACK_TYPE 541 542 Field only valid in case of SU reception. 543 In MU set to 0 544 545 546 Field indicates what type of ACK was received. Can help 547 determine if unexpected ACK Types (like 256 BA instead of 548 64 BA) is received. 549 550 <enum 0 Ack_not_applicable> No ACK type response was received 551 or expected 552 <enum 1 ACK_basic_received > a basic ACk frame is received 553 554 <enum 2 ACK_BA_0 > An ACK embedded in BA frame is received 555 556 <enum 3 ACK_BA_32_received > a 32 bit BA has been received 557 558 <enum 4 ACK_BA_64_received > a 64 bit BA has been received 559 560 <enum 5 ACK_BA_128_received > a 128 bit BA has been received 561 562 563 <enum 6 ACK_BA_256_received > a 256 bit BA has been received 564 565 <enum 8 ACK_BA_512_received> a 512-bit BA has been received 566 567 <enum 9 ACK_BA_1024_received> a 1024-bit BA has been received 568 569 <enum 7 ACK_BA_multiple_received > multiple BA responses 570 have been received. This field to be used in scenarios 571 where multi TID data was send or data with management frames 572 was send 573 574 <legal 0-9> 575 */ 576 577 #define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET 0x0000000000000000 578 #define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB 21 579 #define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB 24 580 #define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK 0x0000000001e00000 581 582 583 /* Description STA_RESPONSE_COUNT 584 585 In of case of a transmission where a response from multiple 586 STAs in SIFS time is expected, this field indicates how 587 many STAs actually send a response. 588 589 <legal 0-63> 590 */ 591 592 #define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET 0x0000000000000000 593 #define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB 25 594 #define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB 30 595 #define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK 0x000000007e000000 596 597 598 /* Description DPDTRAIN_DONE 599 600 Field only valid when PHYTX_PKT_END_info_valid is set 601 602 For DPD Training packets, this bit is set to indicate that 603 DPD Training was successfully run to completion. Also 604 reused by Implicit BF Calibration Packets. This bit is intended 605 for debug purposes. 606 <legal all> 607 */ 608 609 #define TX_FES_STATUS_END_DPDTRAIN_DONE_OFFSET 0x0000000000000000 610 #define TX_FES_STATUS_END_DPDTRAIN_DONE_LSB 31 611 #define TX_FES_STATUS_END_DPDTRAIN_DONE_MSB 31 612 #define TX_FES_STATUS_END_DPDTRAIN_DONE_MASK 0x0000000080000000 613 614 615 /* Description PHYTX_ABORT_REQUEST_INFO_DETAILS 616 617 Field only valid when PHYTX_ABORT_REQUEST_info_valid is 618 set 619 620 The reason why PHYTX is requested an abort 621 */ 622 623 624 /* Description PHYTX_ABORT_REASON 625 626 Reason for early termination of TX packet by the PHY 627 628 <enum_type PHYTX_ABORT_ENUM> 629 */ 630 631 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 632 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 633 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 634 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 635 636 637 /* Description USER_NUMBER 638 639 For some errors, the user for which this error was detected 640 can be indicated in this field. 641 <legal 0-36> 642 */ 643 644 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 645 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 646 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 647 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 648 649 650 /* Description RESERVED 651 652 <legal 0> 653 */ 654 655 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 656 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 657 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 658 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 659 660 661 /* Description RESERVED_AFTER_STRUCT16 662 663 <legal 0> 664 */ 665 666 #define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 667 #define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB 48 668 #define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB 51 669 #define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK 0x000f000000000000 670 671 672 /* Description BRP_INFO_VALID 673 674 When set, TXPCU sent CBF segments. 675 676 Fields cbf_segment_request_mask and cbf_segment_sent_mask 677 contain valid info. 678 679 <legal all> 680 */ 681 682 #define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET 0x0000000000000000 683 #define TX_FES_STATUS_END_BRP_INFO_VALID_LSB 52 684 #define TX_FES_STATUS_END_BRP_INFO_VALID_MSB 52 685 #define TX_FES_STATUS_END_BRP_INFO_VALID_MASK 0x0010000000000000 686 687 688 /* Description RESERVED_1A 689 690 <legal 0> 691 */ 692 693 #define TX_FES_STATUS_END_RESERVED_1A_OFFSET 0x0000000000000000 694 #define TX_FES_STATUS_END_RESERVED_1A_LSB 53 695 #define TX_FES_STATUS_END_RESERVED_1A_MSB 58 696 #define TX_FES_STATUS_END_RESERVED_1A_MASK 0x07e0000000000000 697 698 699 /* Description PHYTX_PKT_END_INFO_VALID 700 701 All the fields originating from PHYTX_PKT_END TLV contain 702 valid info 703 */ 704 705 #define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 706 #define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB 59 707 #define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB 59 708 #define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK 0x0800000000000000 709 710 711 /* Description PHYTX_ABORT_REQUEST_INFO_VALID 712 713 Field Phytx_abort_request_info_details contains valid info 714 715 */ 716 717 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 718 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 60 719 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 60 720 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x1000000000000000 721 722 723 /* Description FES_IN_11AX_TRIGGER_RESPONSE_CONFIG 724 725 When set, this transmission was the result of responding 726 to the reception of an 11ax trigger. This is a copy of 727 field Fes_in_11ax_Trigger_response_config in the TX_FES_SETUP 728 TLV. 729 <legal all> 730 */ 731 732 #define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 733 #define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 61 734 #define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 61 735 #define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x2000000000000000 736 737 738 /* Description NULL_DELIM_INSERTED_BEFORE_MPDUS 739 740 Field only valid when "Fes_in_11ax_Trigger_response_config" 741 is set. 742 743 This bit will get set if any NULL delimiter is sent out 744 to PHY, during the whole transmit duration(self_gen + FES). 745 746 This bit will NOT be set, if no MPDU data is sent out to 747 PHY and whole transmit duration is filled with NULL delimiters. 748 749 750 Note that SCH does not evaluate this field. It is only for 751 SW to look at. 752 753 <legal all> 754 */ 755 756 #define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET 0x0000000000000000 757 #define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB 62 758 #define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB 62 759 #define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK 0x4000000000000000 760 761 762 /* Description ONLY_NULL_DELIM_SENT 763 764 Field only valid when "Fes_in_11ax_Trigger_response_config" 765 is set. 766 767 This bit will be set if only NULL delimiters are sent to 768 the PHY and no SCH sourced MPDU data is sent out. 769 NOTE here that self-gen MPDU data will not be considered 770 while evaluating this bit. 771 772 Note that SCH does not evaluate this field. It is only for 773 SW to look at. 774 775 <legal all> 776 */ 777 778 #define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000000 779 #define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB 63 780 #define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB 63 781 #define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK 0x8000000000000000 782 783 784 /* Description START_OF_FRAME_TIMESTAMP_15_0 785 786 PHYTX_PKT_END info 787 788 Field only valid when PHYTX_PKT_END_info_valid is set 789 790 bits 15:0 of a 64 bit time stamp 791 Start of frame in the medium @960 MHz 792 <legal all> 793 */ 794 795 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 796 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 797 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 798 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff 799 800 801 /* Description START_OF_FRAME_TIMESTAMP_31_16 802 803 PHYTX_PKT_END info 804 805 Field only valid when PHYTX_PKT_END_info_valid is set 806 807 bits 31:16 of a 64 bit time stamp 808 Start of frame in the medium @960 MHz 809 <legal all> 810 */ 811 812 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 813 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 16 814 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 31 815 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 816 817 818 /* Description END_OF_FRAME_TIMESTAMP_15_0 819 820 PHYTX_PKT_END info 821 822 Field only valid when PHYTX_PKT_END_info_valid is set 823 824 bits 15:0 of a 64 bit time stamp 825 End of frame in the medium @960 MHz 826 <legal all> 827 */ 828 829 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 830 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 32 831 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 47 832 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 833 834 835 /* Description END_OF_FRAME_TIMESTAMP_31_16 836 837 PHYTX_PKT_END info 838 839 Field only valid when PHYTX_PKT_END_info_valid is set 840 841 bits 31:16 of a 64 bit time stamp 842 End of frame in the medium @960 MHz 843 <legal all> 844 */ 845 846 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 847 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 48 848 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 63 849 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 850 851 852 /* Description TERMINATE_RANGING_SEQUENCE 853 854 Consumer: SW/SCH 855 Producer: TXPCU 856 857 If set to 1, HWSCH will flush the TX pipeline and terminate 858 the ongoing SIFS sequence for TB Ranging. 859 860 TXPCU to set it only in the context of TB Ranging, when 861 the condition to terminate the TB Ranging sequence is met 862 863 864 <legal all> 865 */ 866 867 #define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_OFFSET 0x0000000000000010 868 #define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_LSB 0 869 #define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MSB 0 870 #define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MASK 0x0000000000000001 871 872 873 /* Description RESERVED_4A 874 875 <legal 0> 876 */ 877 878 #define TX_FES_STATUS_END_RESERVED_4A_OFFSET 0x0000000000000010 879 #define TX_FES_STATUS_END_RESERVED_4A_LSB 1 880 #define TX_FES_STATUS_END_RESERVED_4A_MSB 7 881 #define TX_FES_STATUS_END_RESERVED_4A_MASK 0x00000000000000fe 882 883 884 /* Description TIMING_STATUS 885 886 PHYTX_PKT_END info 887 888 Field only valid when PHYTX_PKT_END_info_valid is set 889 890 <enum 0 No_tx_timing_request> The MAC did not request for 891 the transmission to start at a particular time 892 <enum 1 successful_tx_timing > MAC did request for transmission 893 to start at a particular time and PHY was able to do so. 894 895 <enum 2 tx_timing_not_honoured> PHY was not able to honour 896 the requested transmit time by the MAC. The transmission 897 started later, and field transmit_delay indicates how much 898 later. 899 <legal 0-2> 900 */ 901 902 #define TX_FES_STATUS_END_TIMING_STATUS_OFFSET 0x0000000000000010 903 #define TX_FES_STATUS_END_TIMING_STATUS_LSB 8 904 #define TX_FES_STATUS_END_TIMING_STATUS_MSB 9 905 #define TX_FES_STATUS_END_TIMING_STATUS_MASK 0x0000000000000300 906 907 908 /* Description RESPONSE_TYPE 909 910 The response type that TXPCU was checking for 911 912 <enum 0 no_response_expected>After transmission of this 913 frame, no response in SIFS time is expected 914 915 When TXPCU sees this setting, it shall not generated the 916 EXPECTED_RESPONSE TLV. 917 918 RXPCU should never see this setting 919 <enum 1 ack_expected>An ACK frame is expected as response 920 921 922 RXPCU is just expecting any response. It is TXPCU who checks 923 that the right response was received. 924 <enum 2 ba_64_bitmap_expected>BA with 64 bitmap is expected. 925 926 927 PDG DOES NOT use the size info to calculated response duration. 928 The length of the response will have to be programmed by 929 SW in the per-BW 'Expected_ppdu_resp_length' field. 930 931 For TXPCU only the fact that it is a BA is important. Actual 932 received BA size is not important 933 934 RXPCU is just expecting any response. It is TXPCU who checks 935 that the right response was received. 936 <enum 3 ba_256_expected>BA with 256 bitmap is expected. 937 938 PDG DOES NOT use the size info to calculated response duration. 939 The length of the response will have to be programmed by 940 SW in the per-BW 'Expected_ppdu_resp_length' field. 941 942 For TXPCU only the fact that it is a BA is important. Actual 943 received BA size is not important 944 945 RXPCU is just expecting any response. It is TXPCU who checks 946 that the right response was received. 947 <enum 4 actionnoack_expected>SW sets this after sending 948 NDP or BR-Poll. 949 950 As PDG has no idea on how long the reception is going to 951 be, the reception time of the response will have to be 952 programmed by SW in the 'Extend_duration_value_bw...' field 953 954 955 RXPCU is just expecting any response. It is TXPCU who checks 956 that the right response was received. 957 <enum 5 ack_ba_expected>PDG uses the size info and assumes 958 single BA format with ACK and 64 bitmap embedded. 959 If SW expects more bitmaps in case of multi-TID, is shall 960 program the 'Extend_duration_value_bw...' field for additional 961 duration time. 962 For TXPCU only the fact that an ACK and/or BA is received 963 is important. Reception of only ACK or BA is also considered 964 a success. 965 SW also typically sets this when sending VHT single MPDU. 966 Some chip vendors might send BA rather than ACK in response 967 to VHT single MPDU but still we want to accept BA as well. 968 969 970 RXPCU is just expecting any response. It is TXPCU who checks 971 that the right response was received. 972 <enum 6 cts_expected>SW sets this after queuing RTS frame 973 as standalone packet and sending it. 974 975 RXPCU is just expecting any response. It is TXPCU who checks 976 that the right response was received. 977 <enum 7 ack_data_expected>SW sets this after sending PS-Poll. 978 979 980 For TXPCU either ACK and/or data reception is considered 981 success. 982 PDG basis it's response duration calculation on an ACK. 983 For the data portion, SW shall program the 'Extend_duration_value_bw...' 984 field 985 <enum 8 ndp_ack_expected>Reserved for 11ah usage. 986 <enum 9 ndp_modified_ack>Reserved for 11ah usage 987 <enum 10 ndp_ba_expected>Reserved for 11ah usage. 988 <enum 11 ndp_cts_expected>Reserved for 11ah usage 989 <enum 12 ndp_ack_or_ndp_modified_ack_expected>Reserved for 990 11ah usage 991 992 TXPCU expects UL MU OFDMA or UL MU MIMO reception. 993 As PDG does not know how RUs are assigned for the uplink 994 portion, PDG can not calculate the uplink duration. Therefor 995 SW shall program the 'Extend_duration_value_bw...' field 996 997 998 RXPCU will report any frame received, irrespective of it 999 having been UL MU or SU It is TXPCUs responsibility to 1000 distinguish between the UL MU or SU 1001 1002 TXPCU can check in TLV RECEIVED_RESPONSE_INFO MU_Response_BA_bitmap 1003 if indeed BA was received 1004 1005 TXPCU expects UL MU OFDMA or UL MU MIMO reception. 1006 As PDG does not know how RUs are assigned for the uplink 1007 portion, PDG can not calculate the uplink duration. Therefor 1008 SW shall program the 'Extend_duration_value_bw...' field 1009 1010 1011 RXPCU will report any frame received, irrespective of it 1012 having been UL MU or SU It is TXPCUs responsibility to 1013 distinguish between the UL MU or SU 1014 1015 TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_data_bitmap 1016 and MU_Response_BA_bitmap if indeed BA and data was received 1017 1018 When selected, CBF frames are expected to be received in 1019 MU reception (uplink OFDMA or uplink MIMO) 1020 1021 RXPCU is just expecting any response. It is TXPCU who checks 1022 that the right response was received 1023 TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_cbf_bitmap 1024 if indeed CBF frames were received. 1025 <enum 16 ul_mu_frames_expected>When selected, MPDU frames 1026 are expected in the MU reception (uplink OFDMA or uplink 1027 MIMO) 1028 1029 RXPCU is just expecting any response. It is TXPCU who checks 1030 that the right response was received 1031 1032 TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_bitmap 1033 if indeed frames were received. 1034 <enum 17 any_response_to_this_device>Any response expected 1035 to be send to this device in SIFS time is acceptable. 1036 1037 RXPCU is just expecting any response. It is TXPCU who checks 1038 that the right response was received 1039 1040 For TXPCU, UL MU or SU is both acceptable. 1041 1042 Can be used for complex OFDMA scenarios. PDG can not calculate 1043 the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' 1044 field 1045 <enum 18 any_response_accepted>Any frame in the medium to 1046 this or any other device, is acceptable as response. 1047 RXPCU is just expecting any response. It is TXPCU who checks 1048 that the right response was received 1049 1050 For TXPCU, UL MU or SU is both acceptable. 1051 1052 Can be used for complex OFDMA scenarios. PDG can not calculate 1053 the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' 1054 field 1055 <enum 19 frameless_phyrx_response_accepted>Any MU frameless 1056 reception generated by the PHY is acceptable. 1057 1058 PHY indicates this type of reception explicitly in TLV PHYRX_RSSI_LEGACY, 1059 field Reception_type == reception_is_frameless 1060 1061 RXPCU will report any frame received, irrespective of it 1062 having been UL MU or SU. 1063 1064 This can be used for complex MU-MIMO or OFDMA scenarios, 1065 like receiving MU-CTS. 1066 1067 PDG can not calculate the uplink duration. Therefor SW shall 1068 program the 'Extend_duration_value_bw...' field 1069 <enum 20 ranging_ndp_and_lmr_expected>SW sets this after 1070 sending ranging NDPA followed by NDP as an ISTA and NDP 1071 and LMR (Action No Ack) are expected as back-to-back reception 1072 in SIFS. 1073 1074 As PDG has no idea on how long the reception is going to 1075 be, the reception time of the response will have to be 1076 programmed by SW in the 'Extend_duration_value_bw...' field 1077 1078 1079 RXPCU is just expecting any response. It is TXPCU who checks 1080 that the right response was received. 1081 <enum 21 ba_512_expected>BA with 512 bitmap is expected. 1082 1083 1084 PDG DOES NOT use the size info to calculated response duration. 1085 The length of the response will have to be programmed by 1086 SW in the per-BW 'Expected_ppdu_resp_length' field. 1087 1088 For TXPCU only the fact that it is a BA is important. Actual 1089 received BA size is not important 1090 1091 RXPCU is just expecting any response. It is TXPCU who checks 1092 that the right response was received. 1093 <enum 22 ba_1024_expected>BA with 1024 bitmap is expected. 1094 1095 1096 PDG DOES NOT use the size info to calculated response duration. 1097 The length of the response will have to be programmed by 1098 SW in the per-BW 'Expected_ppdu_resp_length' field. 1099 1100 For TXPCU only the fact that it is a BA is important. Actual 1101 received BA size is not important 1102 1103 RXPCU is just expecting any response. It is TXPCU who checks 1104 that the right response was received. 1105 <enum 23 ul_mu_ranging_cts2s_expected>When selected, CTS2S 1106 frames are expected to be received in MU reception (uplink 1107 OFDMA) 1108 1109 RXPCU shall check each response for CTS2S and report to 1110 TXPCU. 1111 1112 TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields 1113 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed CTS2S 1114 frames were received. 1115 <enum 24 ul_mu_ranging_ndp_expected>When selected, UL NDP 1116 frames are expected to be received in MU reception (uplink 1117 spatial multiplexing) 1118 1119 RXPCU shall check each response for NDP and report to TXPCU. 1120 1121 1122 TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields 1123 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed NDP 1124 frames were received. 1125 <enum 25 ul_mu_ranging_lmr_expected>When selected, LMR frames 1126 are expected to be received in MU reception (uplink OFDMA 1127 or uplink MIMO) 1128 1129 RXPCU shall check each response for LMR and report to TXPCU. 1130 1131 1132 TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields 1133 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed LMR 1134 frames were received. 1135 */ 1136 1137 #define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET 0x0000000000000010 1138 #define TX_FES_STATUS_END_RESPONSE_TYPE_LSB 10 1139 #define TX_FES_STATUS_END_RESPONSE_TYPE_MSB 14 1140 #define TX_FES_STATUS_END_RESPONSE_TYPE_MASK 0x0000000000007c00 1141 1142 1143 /* Description R2R_END_STATUS_TO_FOLLOW 1144 1145 When set, TXPCU will still generate an R2R frame (typically 1146 M-BA), and the 'R2R_STATUS_END' TLV. 1147 <legal all> 1148 */ 1149 1150 #define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000010 1151 #define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB 15 1152 #define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB 15 1153 #define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000000008000 1154 1155 1156 /* Description TRANSMIT_DELAY 1157 1158 PHYTX_PKT_END info 1159 1160 Field only valid when PHYTX_PKT_END_info_valid is set 1161 1162 The number of 480 MHz clock cycles that the transmission 1163 started after the actual requested transmit start time. 1164 1165 Value saturates at 0xFFFF 1166 <legal all> 1167 */ 1168 1169 #define TX_FES_STATUS_END_TRANSMIT_DELAY_OFFSET 0x0000000000000010 1170 #define TX_FES_STATUS_END_TRANSMIT_DELAY_LSB 16 1171 #define TX_FES_STATUS_END_TRANSMIT_DELAY_MSB 31 1172 #define TX_FES_STATUS_END_TRANSMIT_DELAY_MASK 0x00000000ffff0000 1173 1174 1175 /* Description TX_GROUP_DELAY 1176 1177 PHYTX_PKT_END info 1178 1179 Field only valid when PHYTX_PKT_END_info_valid is set 1180 1181 Group delay on TxTD+PHYRF path for this PPDU (packet BW 1182 dependent), useful for RTT 1183 1184 Unit is 960MHz cycles. 1185 <legal all> 1186 */ 1187 1188 #define TX_FES_STATUS_END_TX_GROUP_DELAY_OFFSET 0x0000000000000010 1189 #define TX_FES_STATUS_END_TX_GROUP_DELAY_LSB 32 1190 #define TX_FES_STATUS_END_TX_GROUP_DELAY_MSB 43 1191 #define TX_FES_STATUS_END_TX_GROUP_DELAY_MASK 0x00000fff00000000 1192 1193 1194 /* Description RESERVED_5A 1195 1196 Bits [14:12]: service_cbw: 1197 1198 Field only valid when a response was received 1199 1200 Source of the info here is the 'RECEIVED_RESPONSE_INFO' 1201 TLV 1202 1203 This field reflects the BW extracted from the Serivce Field 1204 for 11ac mode of operation . 1205 1206 This field is used in the context of Dynamic BW evaluation 1207 purposes in SCH in case of SW-queued protection frame. 1208 1209 Please refer 'BW_ENUM' e-num for the values used. 1210 <legal 0-5> 1211 */ 1212 1213 #define TX_FES_STATUS_END_RESERVED_5A_OFFSET 0x0000000000000010 1214 #define TX_FES_STATUS_END_RESERVED_5A_LSB 44 1215 #define TX_FES_STATUS_END_RESERVED_5A_MSB 47 1216 #define TX_FES_STATUS_END_RESERVED_5A_MASK 0x0000f00000000000 1217 1218 1219 /* Description TPC_DBG_INFO_CMN_15_0 1220 1221 PHYTX_PKT_END info 1222 1223 Field only valid when PHYTX_PKT_END_info_valid is set 1224 1225 Some TPC debug info that PHY can pass back to MAC FW 1226 <legal all> 1227 */ 1228 1229 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010 1230 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_LSB 48 1231 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MSB 63 1232 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MASK 0xffff000000000000 1233 1234 1235 /* Description TPC_DBG_INFO_CMN_31_16 1236 1237 PHYTX_PKT_END info 1238 1239 Field only valid when PHYTX_PKT_END_info_valid is set 1240 1241 Some TPC debug info that PHY can pass back to MAC FW 1242 <legal all> 1243 */ 1244 1245 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000018 1246 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_LSB 0 1247 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MSB 15 1248 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MASK 0x000000000000ffff 1249 1250 1251 /* Description TPC_DBG_INFO_47_32 1252 1253 PHYTX_PKT_END info 1254 1255 Field only valid when PHYTX_PKT_END_info_valid is set 1256 1257 Some TPC debu info that PHY can pass back to MAC FW 1258 <legal all> 1259 */ 1260 1261 #define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_OFFSET 0x0000000000000018 1262 #define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_LSB 16 1263 #define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MSB 31 1264 #define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MASK 0x00000000ffff0000 1265 1266 1267 /* Description TPC_DBG_INFO_CHN1_15_0 1268 1269 PHYTX_PKT_END info 1270 1271 Field only valid when PHYTX_PKT_END_info_valid is set 1272 1273 Some per-chain TPC debug info for the first selected chain 1274 that PHY can pass back to MAC FW 1275 <legal all> 1276 */ 1277 1278 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018 1279 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_LSB 32 1280 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MSB 47 1281 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff00000000 1282 1283 1284 /* Description TPC_DBG_INFO_CHN1_31_16 1285 1286 PHYTX_PKT_END info 1287 1288 Field only valid when PHYTX_PKT_END_info_valid is set 1289 1290 Some per-chain TPC debug info for the first selected chain 1291 that PHY can pass back to MAC FW 1292 <legal all> 1293 */ 1294 1295 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018 1296 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_LSB 48 1297 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MSB 63 1298 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MASK 0xffff000000000000 1299 1300 1301 /* Description TPC_DBG_INFO_CHN1_47_32 1302 1303 PHYTX_PKT_END info 1304 1305 Field only valid when PHYTX_PKT_END_info_valid is set 1306 1307 Some per-chain TPC debug info for the first selected chain 1308 that PHY can pass back to MAC FW 1309 <legal all> 1310 */ 1311 1312 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000020 1313 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_LSB 0 1314 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MSB 15 1315 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x000000000000ffff 1316 1317 1318 /* Description TPC_DBG_INFO_CHN1_63_48 1319 1320 PHYTX_PKT_END info 1321 1322 Field only valid when PHYTX_PKT_END_info_valid is set 1323 1324 Some per-chain TPC debug info for the first selected chain 1325 that PHY can pass back to MAC FW 1326 <legal all> 1327 */ 1328 1329 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020 1330 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_LSB 16 1331 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MSB 31 1332 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x00000000ffff0000 1333 1334 1335 /* Description TPC_DBG_INFO_CHN1_79_64 1336 1337 PHYTX_PKT_END info 1338 1339 Field only valid when PHYTX_PKT_END_info_valid is set 1340 1341 Some per-chain TPC debug info for the first selected chain 1342 that PHY can pass back to MAC FW 1343 <legal all> 1344 */ 1345 1346 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020 1347 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_LSB 32 1348 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MSB 47 1349 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff00000000 1350 1351 1352 /* Description TPC_DBG_INFO_CHN2_15_0 1353 1354 PHYTX_PKT_END info 1355 1356 Field only valid when PHYTX_PKT_END_info_valid is set 1357 1358 Some per-chain TPC debug info for the second selected chain 1359 that PHY can pass back to MAC FW 1360 <legal all> 1361 */ 1362 1363 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020 1364 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_LSB 48 1365 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MSB 63 1366 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MASK 0xffff000000000000 1367 1368 1369 /* Description TPC_DBG_INFO_CHN2_31_16 1370 1371 PHYTX_PKT_END info 1372 1373 Field only valid when PHYTX_PKT_END_info_valid is set 1374 1375 Some per-chain TPC debug info for the second selected chain 1376 that PHY can pass back to MAC FW 1377 <legal all> 1378 */ 1379 1380 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000028 1381 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_LSB 0 1382 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MSB 15 1383 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x000000000000ffff 1384 1385 1386 /* Description TPC_DBG_INFO_CHN2_47_32 1387 1388 PHYTX_PKT_END info 1389 1390 Field only valid when PHYTX_PKT_END_info_valid is set 1391 1392 Some per-chain TPC debug info for the second selected chain 1393 that PHY can pass back to MAC FW 1394 <legal all> 1395 */ 1396 1397 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028 1398 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_LSB 16 1399 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MSB 31 1400 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x00000000ffff0000 1401 1402 1403 /* Description TPC_DBG_INFO_CHN2_63_48 1404 1405 PHYTX_PKT_END info 1406 1407 Field only valid when PHYTX_PKT_END_info_valid is set 1408 1409 Some per-chain TPC debug info for the second selected chain 1410 that PHY can pass back to MAC FW 1411 <legal all> 1412 */ 1413 1414 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028 1415 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_LSB 32 1416 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MSB 47 1417 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff00000000 1418 1419 1420 /* Description TPC_DBG_INFO_CHN2_79_64 1421 1422 PHYTX_PKT_END info 1423 1424 Field only valid when PHYTX_PKT_END_info_valid is set 1425 1426 Some per-chain TPC debug info for the second selected chain 1427 that PHY can pass back to MAC FW 1428 <legal all> 1429 */ 1430 1431 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028 1432 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_LSB 48 1433 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MSB 63 1434 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MASK 0xffff000000000000 1435 1436 1437 /* Description PHYTX_TX_END_SW_INFO_15_0 1438 1439 PHYTX_PKT_END info 1440 1441 Field only valid when PHYTX_PKT_END_info_valid is set 1442 1443 Some PHY status data that PHY microcode can pass back to 1444 MAC FW, for any future requests, e.g. any DMA download 1445 time 1446 <legal all> 1447 */ 1448 1449 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030 1450 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0 1451 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15 1452 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff 1453 1454 1455 /* Description PHYTX_TX_END_SW_INFO_31_16 1456 1457 PHYTX_PKT_END info 1458 1459 Field only valid when PHYTX_PKT_END_info_valid is set 1460 1461 Some PHY status data that PHY microcode can pass back to 1462 MAC FW, for any future requests, e.g. any DMA download 1463 time 1464 <legal all> 1465 */ 1466 1467 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030 1468 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_LSB 16 1469 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MSB 31 1470 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 1471 1472 1473 /* Description PHYTX_TX_END_SW_INFO_47_32 1474 1475 PHYTX_PKT_END info 1476 1477 Field only valid when PHYTX_PKT_END_info_valid is set 1478 1479 Some PHY status data that PHY microcode can pass back to 1480 MAC FW, for any future requests, e.g. any DMA download 1481 time 1482 <legal all> 1483 */ 1484 1485 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030 1486 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_LSB 32 1487 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MSB 47 1488 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 1489 1490 1491 /* Description PHYTX_TX_END_SW_INFO_63_48 1492 1493 PHYTX_PKT_END info 1494 1495 Field only valid when PHYTX_PKT_END_info_valid is set 1496 1497 Some PHY status data that PHY microcode can pass back to 1498 MAC FW, for any future requests, e.g. any DMA download 1499 time 1500 <legal all> 1501 */ 1502 1503 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030 1504 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_LSB 48 1505 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MSB 63 1506 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 1507 1508 1509 /* Description BEAMFORM_MASKED_USER_BITMAP_15_0 1510 1511 Lower 16 bits of 'Beamform_masked_user_bitmap' 1512 1513 PHY indicates in this field for which users it actually 1514 did not beamform it's transmission even though this was 1515 requested 1516 1517 Bit 0: user 0, bit 1: user 1, etc. 1518 1519 When 0: No beamform issue for this user 1520 When 1: PHY could not beamform for this user, but did not 1521 terminate the transmission 1522 1523 <legal all> 1524 */ 1525 1526 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000000000000038 1527 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0 1528 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15 1529 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x000000000000ffff 1530 1531 1532 /* Description BEAMFORM_MASKED_USER_BITMAP_31_16 1533 1534 Middle 16 bits of 'Beamform_masked_user_bitmap' 1535 See description above. 1536 <legal all> 1537 */ 1538 1539 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x0000000000000038 1540 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 16 1541 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 31 1542 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x00000000ffff0000 1543 1544 1545 /* Description CBF_SEGMENT_REQUEST_MASK 1546 1547 Field only valid when brp_info_valid is set. 1548 1549 Field equal to the 'Feedback Segment Retransmission Bitmap' 1550 from the Beamform Report Poll frame OR Beamform Report Poll 1551 Trigger frame 1552 1553 Bit 0 represents segment 0 1554 Bit 1 represents segment 1 1555 Etc. 1556 1557 1'b1: Segment is requested 1558 1'b0: Segment is NOT requested 1559 1560 <legal all> 1561 */ 1562 1563 #define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000038 1564 #define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB 32 1565 #define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB 39 1566 #define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK 0x000000ff00000000 1567 1568 1569 /* Description CBF_SEGMENT_SENT_MASK 1570 1571 Field only valid when brp_info_valid is set. 1572 1573 Bit 0 represents segment 0 1574 Bit 1 represents segment 1 1575 Etc. 1576 1577 1'b1: Segment is sent 1578 1'b0: Segment is not sent 1579 1580 <legal all> 1581 */ 1582 1583 #define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000038 1584 #define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB 40 1585 #define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB 47 1586 #define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK 0x0000ff0000000000 1587 1588 1589 /* Description HIGHEST_ACHIEVED_DATA_NULL_RATIO 1590 1591 Highest DATA:NULL ratio achieved for the current FES 1592 1593 <enum 0 No_Data_Null_ratio_requirement> There was no Data:NULL 1594 ratio established. 1595 <enum 1 Data_Null_ratio_16_1> Best Data:NULL ratio was 16:1. 1596 1597 <enum 2 Data_Null_ratio_8_1> Best Data:NULL ratio was 8:1. 1598 1599 <enum 3 Data_Null_ratio_4_1> Best Data:NULL ratio was 4:1. 1600 1601 <enum 4 Data_Null_ratio_2_1> Best Data:NULL ratio was 2:1. 1602 1603 <enum 5 Data_Null_ratio_1_1> Best Data:NULL ratio was 1:1. 1604 1605 terminate FES. 1606 <enum 6 Data_Null_ratio_1_2> Best Data:NULL ratio was 1:2. 1607 1608 <enum 7 Data_Null_ratio_1_4> Best Data:NULL ratio was 1:4. 1609 1610 <enum 8 Data_Null_ratio_1_8> Best Data:NULL ratio was 1:8. 1611 1612 <enum 9 Data_Null_ratio_1_16> Best Data:NULL ratio was 1:16. 1613 1614 1615 <legal 0-9> 1616 */ 1617 1618 #define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET 0x0000000000000038 1619 #define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB 48 1620 #define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB 52 1621 #define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK 0x001f000000000000 1622 1623 1624 /* Description USE_ALT_POWER_SR 1625 1626 0: Primary/default power1: Alternate power 1627 <legal all> 1628 */ 1629 1630 #define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET 0x0000000000000038 1631 #define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB 53 1632 #define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB 53 1633 #define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK 0x0020000000000000 1634 1635 1636 /* Description STATIC_2_PWR_MODE_STATUS 1637 1638 0: Static 2 power mode disabled1: Static 2 power mode enabled 1639 1640 <legal all> 1641 */ 1642 1643 #define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000038 1644 #define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB 54 1645 #define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB 54 1646 #define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK 0x0040000000000000 1647 1648 1649 /* Description OBSS_SRG_OPPORT_TRANSMIT_STATUS 1650 1651 0: Transmit based on SRG OBSS_PD opportunity initiated1: 1652 Transmit based on non-SRG OBSS_PD opportunity initiated 1653 <legal all> 1654 */ 1655 1656 #define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000038 1657 #define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 55 1658 #define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 55 1659 #define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0080000000000000 1660 1661 1662 /* Description SRP_BASED_TRANSMIT_STATUS 1663 1664 0: non-SRP based transmit initiated1: SRP based transmit 1665 initiated 1666 <legal all> 1667 */ 1668 1669 #define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000038 1670 #define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB 56 1671 #define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB 56 1672 #define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK 0x0100000000000000 1673 1674 1675 /* Description OBSS_PD_BASED_TRANSMIT_STATUS 1676 1677 0: non-OBSS_PD based transmit initiated1: obss_pd based 1678 transmit initiated 1679 <legal all> 1680 */ 1681 1682 #define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000038 1683 #define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 57 1684 #define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 57 1685 #define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0200000000000000 1686 1687 1688 /* Description BEAMFORM_MASKED_USER_BITMAP_36_32 1689 1690 Upper 5 bits of 'Beamform_masked_user_bitmap' 1691 See description above. 1692 <legal all> 1693 */ 1694 1695 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x0000000000000038 1696 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 58 1697 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 62 1698 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x7c00000000000000 1699 1700 1701 /* Description PDG_MPDU_READY 1702 1703 Field only valid in case of SU transmissions, copied over 1704 by TXPCU from 'PCU_PPDU_SETUP_END' 1705 1706 Indicates the 'MPDU_INFO' or 'MPDU_QUEUE_OVERVIEW' ready 1707 status in PDG. 1708 <legal all> 1709 */ 1710 1711 #define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET 0x0000000000000038 1712 #define TX_FES_STATUS_END_PDG_MPDU_READY_LSB 63 1713 #define TX_FES_STATUS_END_PDG_MPDU_READY_MSB 63 1714 #define TX_FES_STATUS_END_PDG_MPDU_READY_MASK 0x8000000000000000 1715 1716 1717 /* Description PDG_MPDU_COUNT 1718 1719 Field only valid in case of SU transmissions when pdg_MPDU_ready 1720 is set, copied over by TXPCU from 'PCU_PPDU_SETUP_END' 1721 1722 Total MPDU count from 'MPDU_INFO' or 'MPDU_QUEUE_OVERVIEW' 1723 1724 <legal 0-2130> 1725 */ 1726 1727 #define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET 0x0000000000000040 1728 #define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB 0 1729 #define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB 15 1730 #define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK 0x000000000000ffff 1731 1732 1733 /* Description PDG_EST_MPDU_TX_COUNT 1734 1735 Field only valid in case of SU transmissions when pdg_MPDU_ready 1736 is set, copied over by TXPCU from 'PCU_PPDU_SETUP_END' 1737 1738 PDG estimated MPDU Tx count from 'MPDU_INFO' or 'MPDU_QUEUE_OVERVIEW' 1739 limited by timing boundaries (HWSCH, COEX, SR, etc.) 1740 <legal 0-1024> 1741 */ 1742 1743 #define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET 0x0000000000000040 1744 #define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB 16 1745 #define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB 31 1746 #define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK 0x00000000ffff0000 1747 1748 1749 /* Description PDG_OVERVIEW_LENGTH 1750 1751 Field only valid in case of SU transmissions when pdg_MPDU_ready 1752 is set, copied over by TXPCU from 'PCU_PPDU_SETUP_END' 1753 1754 PDG estimated A-MPDU length from 'MPDU_QUEUE_OVERVIEW' limited 1755 by timing boundaries (HWSCH, COEX, SR, etc.) 1756 <legal all> 1757 */ 1758 1759 #define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET 0x0000000000000040 1760 #define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB 32 1761 #define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB 55 1762 #define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK 0x00ffffff00000000 1763 1764 1765 /* Description TXOP_DURATION 1766 1767 TXOP_DURATION of HE-SIG-A calculated by PDG, to be copied 1768 from 'PCU_PPDU_SETUP_END' by TXPCU 1769 */ 1770 1771 #define TX_FES_STATUS_END_TXOP_DURATION_OFFSET 0x0000000000000040 1772 #define TX_FES_STATUS_END_TXOP_DURATION_LSB 56 1773 #define TX_FES_STATUS_END_TXOP_DURATION_MSB 62 1774 #define TX_FES_STATUS_END_TXOP_DURATION_MASK 0x7f00000000000000 1775 1776 1777 /* Description PDG_DROPPED_MPDU_WARNING 1778 1779 Warning that PDG has dropped MPDUs due to SFM FIFO full 1780 condition, to be copied from 'PCU_PPDU_SETUP_END' by TXPCU 1781 1782 */ 1783 1784 #define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000040 1785 #define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB 63 1786 #define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB 63 1787 #define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK 0x8000000000000000 1788 1789 1790 /* Description PACKET_EXTENSION_A_FACTOR 1791 1792 The "a-factor" of the trigger-based PPDU response, to be 1793 copied from 'PCU_PPDU_SETUP_END' by TXPCU 1794 1795 This affects the packet extension duration. 1796 1797 <enum 0 a_factor_4> 1798 <enum 1 a_factor_1> 1799 <enum 2 a_factor_2> 1800 <enum 3 a_factor_3> 1801 1802 <legal all> 1803 */ 1804 1805 #define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000048 1806 #define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB 0 1807 #define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB 1 1808 #define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 1809 1810 1811 /* Description PACKET_EXTENSION_PE_DISAMBIGUITY 1812 1813 The "PE-Disambiguity" of the trigger-based PPDU response, 1814 to be copied from 'PCU_PPDU_SETUP_END' by TXPCU 1815 1816 This affects the packet extension duration. 1817 1818 <legal all> 1819 */ 1820 1821 #define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000048 1822 #define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 1823 #define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 1824 #define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 1825 1826 1827 /* Description PACKET_EXTENSION 1828 1829 Packet extension size, to be copied from 'PCU_PPDU_SETUP_END' 1830 by TXPCU 1831 1832 This is valid for all PPDUs including HE-Ranging NDPs (11az) 1833 and Short-NDPs. 1834 1835 <enum 0 packet_ext_0> 1836 <enum 1 packet_ext_4> 1837 <enum 2 packet_ext_8> 1838 <enum 3 packet_ext_12> 1839 <enum 4 packet_ext_16> 1840 <enum 5 packet_ext_20> 1841 <legal 0 - 5> 1842 */ 1843 1844 #define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET 0x0000000000000048 1845 #define TX_FES_STATUS_END_PACKET_EXTENSION_LSB 3 1846 #define TX_FES_STATUS_END_PACKET_EXTENSION_MSB 5 1847 #define TX_FES_STATUS_END_PACKET_EXTENSION_MASK 0x0000000000000038 1848 1849 1850 /* Description FEC_TYPE 1851 1852 For trigger-based PPDU response, to be copied from 'PCU_PPDU_SETUP_END' 1853 by TXPCU 1854 0: BCC 1855 1: LDPC 1856 <legal all> 1857 */ 1858 1859 #define TX_FES_STATUS_END_FEC_TYPE_OFFSET 0x0000000000000048 1860 #define TX_FES_STATUS_END_FEC_TYPE_LSB 6 1861 #define TX_FES_STATUS_END_FEC_TYPE_MSB 6 1862 #define TX_FES_STATUS_END_FEC_TYPE_MASK 0x0000000000000040 1863 1864 1865 /* Description STBC 1866 1867 For trigger-based PPDU response, to be copied from 'PCU_PPDU_SETUP_END' 1868 by TXPCU 1869 1870 When set, this transmission is based on STBC rates. 1871 */ 1872 1873 #define TX_FES_STATUS_END_STBC_OFFSET 0x0000000000000048 1874 #define TX_FES_STATUS_END_STBC_LSB 7 1875 #define TX_FES_STATUS_END_STBC_MSB 7 1876 #define TX_FES_STATUS_END_STBC_MASK 0x0000000000000080 1877 1878 1879 /* Description NUM_DATA_SYMBOLS 1880 1881 The number of data symbols in the transmission, to be copied 1882 from 'PCU_PPDU_SETUP_END' by TXPCU 1883 1884 This does not include PE_LTF. Also for STBC packets this 1885 has to be an even number. This is valid for all PPDUs. 1886 */ 1887 1888 #define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000048 1889 #define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB 8 1890 #define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB 23 1891 #define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK 0x0000000000ffff00 1892 1893 1894 /* Description RU_SIZE 1895 1896 The size of the RU for this user, for trigger-based PPDU 1897 response, to be copied from 'PCU_PPDU_SETUP_END' by TXPCU 1898 1899 1900 <enum 0 RU_26> 1901 <enum 1 RU_52> 1902 <enum 2 RU_106> 1903 <enum 3 RU_242> 1904 <enum 4 RU_484> 1905 <enum 5 RU_996> 1906 <enum 6 RU_1992> 1907 <enum 7 RU_FULLBW> Set when the RU occupies the full packet 1908 bandwidth 1909 <enum 8 RU_FULLBW_240> Set when the RU occupies the full 1910 packet bandwidth 1911 <enum 9 RU_FULLBW_320> Set when the RU occupies the full 1912 packet bandwidth 1913 <enum 10 RU_MULTI_LARGE> HW will use per-user sub-band-mask 1914 to infer the actual RU-size for Multi-large-RU/SU-Puncturing 1915 1916 <enum 11 RU_78> multi small RU 1917 <enum 12 RU_132> multi small RU 1918 <legal 0-12> 1919 */ 1920 1921 #define TX_FES_STATUS_END_RU_SIZE_OFFSET 0x0000000000000048 1922 #define TX_FES_STATUS_END_RU_SIZE_LSB 24 1923 #define TX_FES_STATUS_END_RU_SIZE_MSB 27 1924 #define TX_FES_STATUS_END_RU_SIZE_MASK 0x000000000f000000 1925 1926 1927 1928 #define TX_FES_STATUS_END_RESERVED_17A_OFFSET 0x0000000000000048 1929 #define TX_FES_STATUS_END_RESERVED_17A_LSB 28 1930 #define TX_FES_STATUS_END_RESERVED_17A_MSB 31 1931 #define TX_FES_STATUS_END_RESERVED_17A_MASK 0x00000000f0000000 1932 1933 1934 /* Description NUM_LTF_SYMBOLS 1935 1936 Indicates the number of HE-LTF symbols, for trigger-based 1937 PPDU response, to be copied from 'PCU_PPDU_SETUP_END' by 1938 TXPCU 1939 1940 0: 1 symbol 1941 1: 2 symbols 1942 2: 3 symbols 1943 3: 4 symbols 1944 4: 5 symbols 1945 5: 6 symbols 1946 6: 7 symbols 1947 7: 8 symbols 1948 1949 NOTE that this encoding is different from what is in "Num_LTF_symbols" 1950 in the HE_SIG_A_MU_DL. 1951 <legal all> 1952 */ 1953 1954 #define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000048 1955 #define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB 32 1956 #define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB 34 1957 #define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 1958 1959 1960 /* Description LTF_SIZE 1961 1962 Ltf size, to be copied from 'PCU_PPDU_SETUP_END' by TXPCU 1963 1964 1965 This is valid for all PPDUs including HE-Ranging NDPs (11az) 1966 and Short-NDPs. 1967 1968 <enum 0 ltf_1x > 1969 <enum 1 ltf_2x > 1970 <enum 2 ltf_4x > 1971 <legal 0 - 2> 1972 */ 1973 1974 #define TX_FES_STATUS_END_LTF_SIZE_OFFSET 0x0000000000000048 1975 #define TX_FES_STATUS_END_LTF_SIZE_LSB 35 1976 #define TX_FES_STATUS_END_LTF_SIZE_MSB 36 1977 #define TX_FES_STATUS_END_LTF_SIZE_MASK 0x0000001800000000 1978 1979 1980 /* Description CP_SETTING 1981 1982 Field only valid when pkt type is HT, VHT or HE 1983 1984 GI setting, to be copied from 'PCU_PPDU_SETUP_END' by TXPCU 1985 1986 1987 This is valid for all PPDUs including HE-Ranging NDPs (11az) 1988 and Short-NDPs. 1989 1990 <enum 0 gi_0_8_us > Legacy normal GI 1991 <enum 1 gi_0_4_us > Legacy short GI 1992 <enum 2 gi_1_6_us > HE related GI 1993 <enum 3 gi_3_2_us > HE related GI 1994 <legal 0 - 3> 1995 */ 1996 1997 #define TX_FES_STATUS_END_CP_SETTING_OFFSET 0x0000000000000048 1998 #define TX_FES_STATUS_END_CP_SETTING_LSB 37 1999 #define TX_FES_STATUS_END_CP_SETTING_MSB 38 2000 #define TX_FES_STATUS_END_CP_SETTING_MASK 0x0000006000000000 2001 2002 2003 2004 #define TX_FES_STATUS_END_RESERVED_18A_OFFSET 0x0000000000000048 2005 #define TX_FES_STATUS_END_RESERVED_18A_LSB 39 2006 #define TX_FES_STATUS_END_RESERVED_18A_MSB 43 2007 #define TX_FES_STATUS_END_RESERVED_18A_MASK 0x00000f8000000000 2008 2009 2010 /* Description DCM 2011 2012 Field only valid in case of 11ax transmission 2013 2014 Indicates whether dual sub-carrier modulation is applied, 2015 for trigger-based PPDU response, to be copied from 'PCU_PPDU_SETUP_END' 2016 by TXPCU 2017 0: No DCM 2018 1:DCM 2019 <legal all> 2020 */ 2021 2022 #define TX_FES_STATUS_END_DCM_OFFSET 0x0000000000000048 2023 #define TX_FES_STATUS_END_DCM_LSB 44 2024 #define TX_FES_STATUS_END_DCM_MSB 44 2025 #define TX_FES_STATUS_END_DCM_MASK 0x0000100000000000 2026 2027 2028 /* Description LDPC_EXTRA_SYMBOL 2029 2030 Set to 1 if the LDPC PPDU encoding process (if an SU PPDU), 2031 or at least one LDPC user's PPDU encoding process (if an 2032 MU PPDU), results in an extra OFDM symbol (or symbols) 2033 as described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5 2034 (Encoding process for MU PPDUs). Set to 0 otherwise. 2035 2036 To be copied from 'PCU_PPDU_SETUP_END' by TXPCU 2037 <legal all> 2038 */ 2039 2040 #define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000048 2041 #define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB 45 2042 #define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB 45 2043 #define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK 0x0000200000000000 2044 2045 2046 /* Description FORCE_EXTRA_SYMBOL 2047 2048 Set to 1 to force an extra OFDM symbol (or symbols) even 2049 if none of the users' PPDU encoding process resuls in an 2050 extra OFDM symbol (or symbols). 2051 2052 To be copied from 'PCU_PPDU_SETUP_END' by TXPCU 2053 <legal all> 2054 */ 2055 2056 #define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048 2057 #define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB 46 2058 #define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB 46 2059 #define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK 0x0000400000000000 2060 2061 2062 /* Description RESERVED_18B 2063 2064 <legal 0> 2065 */ 2066 2067 #define TX_FES_STATUS_END_RESERVED_18B_OFFSET 0x0000000000000048 2068 #define TX_FES_STATUS_END_RESERVED_18B_LSB 47 2069 #define TX_FES_STATUS_END_RESERVED_18B_MSB 47 2070 #define TX_FES_STATUS_END_RESERVED_18B_MASK 0x0000800000000000 2071 2072 2073 /* Description TX_PWR_SHARED 2074 2075 Transmit Power (signed value) in units of 0.25 dBm, to be 2076 copied from 'PCU_PPDU_SETUP_END' by TXPCU 2077 <legal all> 2078 */ 2079 2080 #define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET 0x0000000000000048 2081 #define TX_FES_STATUS_END_TX_PWR_SHARED_LSB 48 2082 #define TX_FES_STATUS_END_TX_PWR_SHARED_MSB 55 2083 #define TX_FES_STATUS_END_TX_PWR_SHARED_MASK 0x00ff000000000000 2084 2085 2086 /* Description TX_PWR_UNSHARED 2087 2088 Transmit Power (signed value) in units of 0.25 dBm, to be 2089 copied from 'PCU_PPDU_SETUP_END' by TXPCU 2090 <legal all> 2091 */ 2092 2093 #define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET 0x0000000000000048 2094 #define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB 56 2095 #define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB 63 2096 #define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK 0xff00000000000000 2097 2098 2099 /* Description RANGING_ACTIVE_USER_MAP 2100 2101 Field only valid for TB Ranging transmissions 2102 2103 TXPCU sets this to the current active user bitmap, with 2104 each bit set to: 2105 1: for an active user, and 2106 0: for any user not part of the ranging. 2107 2108 */ 2109 2110 #define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_OFFSET 0x0000000000000050 2111 #define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_LSB 0 2112 #define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MSB 15 2113 #define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MASK 0x000000000000ffff 2114 2115 2116 /* Description RANGING_SENT_DUMMY_TX 2117 2118 Field only valid for TB Ranging transmissions 2119 2120 TXPCU sets this bit if some user's 'STA Info' or 'User Info' 2121 was sent out as dummy, or the whole transmission was sent 2122 out as dummy. 2123 */ 2124 2125 #define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_OFFSET 0x0000000000000050 2126 #define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_LSB 16 2127 #define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MSB 16 2128 #define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MASK 0x0000000000010000 2129 2130 2131 /* Description RANGING_FTM_FRAME_SENT 2132 2133 Field only valid for Ranging transmissions 2134 2135 TXPCU sets this bit if an FTM frame aggregated with an LMR 2136 was sent. 2137 */ 2138 2139 #define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_OFFSET 0x0000000000000050 2140 #define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_LSB 17 2141 #define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MSB 17 2142 #define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MASK 0x0000000000020000 2143 2144 2145 /* Description RESERVED_20A 2146 2147 <legal 0> 2148 */ 2149 2150 #define TX_FES_STATUS_END_RESERVED_20A_OFFSET 0x0000000000000050 2151 #define TX_FES_STATUS_END_RESERVED_20A_LSB 18 2152 #define TX_FES_STATUS_END_RESERVED_20A_MSB 23 2153 #define TX_FES_STATUS_END_RESERVED_20A_MASK 0x0000000000fc0000 2154 2155 2156 /* Description CV_CORR_STATUS 2157 2158 CV correlation status from 'PHYTX_CV_CORR_STATUS,' to be 2159 copied from 'PCU_PPDU_SETUP_END' by TXPCU 2160 <legal all> 2161 */ 2162 2163 #define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET 0x0000000000000050 2164 #define TX_FES_STATUS_END_CV_CORR_STATUS_LSB 24 2165 #define TX_FES_STATUS_END_CV_CORR_STATUS_MSB 31 2166 #define TX_FES_STATUS_END_CV_CORR_STATUS_MASK 0x00000000ff000000 2167 2168 2169 /* Description CURRENT_TX_DURATION 2170 2171 The duration of the transmission in us, copied over from 2172 PCU_PPDU_SETUP_{END, START} as the case may be 2173 <legal all> 2174 */ 2175 2176 #define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET 0x0000000000000050 2177 #define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB 32 2178 #define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB 47 2179 #define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK 0x0000ffff00000000 2180 2181 2182 /* Description RESERVED_21A 2183 2184 Bits [19:16]: num_cts2self_transmitted: 2185 2186 Number of CTS2SELF frames transmitted in this FES 2187 2188 <legal 0-15> 2189 */ 2190 2191 #define TX_FES_STATUS_END_RESERVED_21A_OFFSET 0x0000000000000050 2192 #define TX_FES_STATUS_END_RESERVED_21A_LSB 48 2193 #define TX_FES_STATUS_END_RESERVED_21A_MSB 63 2194 #define TX_FES_STATUS_END_RESERVED_21A_MASK 0xffff000000000000 2195 2196 2197 2198 #endif // TX_FES_STATUS_END 2199