1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _TCL_GSE_CMD_H_ 18 #define _TCL_GSE_CMD_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_TCL_GSE_CMD 8 23 24 25 struct tcl_gse_cmd { 26 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 27 uint32_t control_buffer_addr_31_0 : 32; // [31:0] 28 uint32_t control_buffer_addr_39_32 : 8, // [7:0] 29 gse_ctrl : 4, // [11:8] 30 gse_sel : 1, // [12:12] 31 status_destination_ring_id : 1, // [13:13] 32 swap : 1, // [14:14] 33 index_search_en : 1, // [15:15] 34 cache_set_num : 4, // [19:16] 35 reserved_1a : 12; // [31:20] 36 uint32_t tcl_cmd_type : 1, // [0:0] 37 reserved_2a : 31; // [31:1] 38 uint32_t cmd_meta_data_31_0 : 32; // [31:0] 39 uint32_t cmd_meta_data_63_32 : 32; // [31:0] 40 uint32_t reserved_5a : 32; // [31:0] 41 uint32_t reserved_6a : 32; // [31:0] 42 uint32_t reserved_7a : 20, // [19:0] 43 ring_id : 8, // [27:20] 44 looping_count : 4; // [31:28] 45 #else 46 uint32_t control_buffer_addr_31_0 : 32; // [31:0] 47 uint32_t reserved_1a : 12, // [31:20] 48 cache_set_num : 4, // [19:16] 49 index_search_en : 1, // [15:15] 50 swap : 1, // [14:14] 51 status_destination_ring_id : 1, // [13:13] 52 gse_sel : 1, // [12:12] 53 gse_ctrl : 4, // [11:8] 54 control_buffer_addr_39_32 : 8; // [7:0] 55 uint32_t reserved_2a : 31, // [31:1] 56 tcl_cmd_type : 1; // [0:0] 57 uint32_t cmd_meta_data_31_0 : 32; // [31:0] 58 uint32_t cmd_meta_data_63_32 : 32; // [31:0] 59 uint32_t reserved_5a : 32; // [31:0] 60 uint32_t reserved_6a : 32; // [31:0] 61 uint32_t looping_count : 4, // [31:28] 62 ring_id : 8, // [27:20] 63 reserved_7a : 20; // [19:0] 64 #endif 65 }; 66 67 68 /* Description CONTROL_BUFFER_ADDR_31_0 69 70 Address (lower 32 bits) of a control buffer containing additional 71 info needed for this command execution. 72 <legal all> 73 */ 74 75 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 76 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB 0 77 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB 31 78 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff 79 80 81 /* Description CONTROL_BUFFER_ADDR_39_32 82 83 Address (upper 8 bits) of a control buffer containing additional 84 info needed for this command execution. 85 <legal all> 86 */ 87 88 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 89 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB 0 90 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB 7 91 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff 92 93 94 /* Description GSE_CTRL 95 96 GSE control operations. This includes cache operations and 97 table entry statistics read/clear operation. 98 <enum 0 rd_stat> Report or Read statistics 99 <enum 1 srch_dis> Search disable. Report only Hash 100 <enum 2 Wr_bk_single> Write Back single entry 101 <enum 3 wr_bk_all> Write Back entire cache entry 102 <enum 4 inval_single> Invalidate single cache entry 103 <enum 5 inval_all> Invalidate entire cache 104 <enum 6 wr_bk_inval_single> Write back and Invalidate single 105 entry in cache 106 <enum 7 wr_bk_inval_all> write back and invalidate entire 107 cache 108 <enum 8 clr_stat_single> Clear statistics for single entry 109 110 <legal 0-8> 111 Rest of the values reserved. 112 For all single entry control operations (write back, Invalidate 113 or both)Statistics will be reported 114 */ 115 116 #define TCL_GSE_CMD_GSE_CTRL_OFFSET 0x00000004 117 #define TCL_GSE_CMD_GSE_CTRL_LSB 8 118 #define TCL_GSE_CMD_GSE_CTRL_MSB 11 119 #define TCL_GSE_CMD_GSE_CTRL_MASK 0x00000f00 120 121 122 /* Description GSE_SEL 123 124 Bit to select the ASE or FSE to do the operation mention 125 by GSE_ctrl bit 126 0: FSE select 127 1: ASE select 128 */ 129 130 #define TCL_GSE_CMD_GSE_SEL_OFFSET 0x00000004 131 #define TCL_GSE_CMD_GSE_SEL_LSB 12 132 #define TCL_GSE_CMD_GSE_SEL_MSB 12 133 #define TCL_GSE_CMD_GSE_SEL_MASK 0x00001000 134 135 136 /* Description STATUS_DESTINATION_RING_ID 137 138 The TCL status ring to which the GSE status needs to be 139 send. 140 141 <enum 0 tcl_status_0_ring> 142 <enum 1 tcl_status_1_ring> 143 144 <legal all> 145 */ 146 147 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 148 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB 13 149 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB 13 150 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK 0x00002000 151 152 153 /* Description SWAP 154 155 Bit to enable byte swapping of contents of buffer 156 <enum 0 Byte_swap_disable > 157 <enum 1 byte_swap_enable > 158 <legal all> 159 */ 160 161 #define TCL_GSE_CMD_SWAP_OFFSET 0x00000004 162 #define TCL_GSE_CMD_SWAP_LSB 14 163 #define TCL_GSE_CMD_SWAP_MSB 14 164 #define TCL_GSE_CMD_SWAP_MASK 0x00004000 165 166 167 /* Description INDEX_SEARCH_EN 168 169 When this bit is set to 1 control_buffer_addr[19:0] will 170 be considered as index of the AST or Flow table and GSE 171 commands will be executed accordingly on the entry pointed 172 by the index. 173 This feature is disabled by setting this bit to 0. 174 <enum 0 index_based_cmd_disable> 175 <enum 1 index_based_cmd_enable> 176 177 <legal all> 178 */ 179 180 #define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET 0x00000004 181 #define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB 15 182 #define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB 15 183 #define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK 0x00008000 184 185 186 /* Description CACHE_SET_NUM 187 188 Cache set number that should be used to cache the index 189 based search results, for address and flow search. This 190 value should be equal to value of cache_set_num for the 191 index that is issued in TCL_DATA_CMD during search index 192 based ASE or FSE. This field is valid for index based GSE 193 commands 194 <legal all> 195 */ 196 197 #define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET 0x00000004 198 #define TCL_GSE_CMD_CACHE_SET_NUM_LSB 16 199 #define TCL_GSE_CMD_CACHE_SET_NUM_MSB 19 200 #define TCL_GSE_CMD_CACHE_SET_NUM_MASK 0x000f0000 201 202 203 /* Description RESERVED_1A 204 205 <legal 0> 206 */ 207 208 #define TCL_GSE_CMD_RESERVED_1A_OFFSET 0x00000004 209 #define TCL_GSE_CMD_RESERVED_1A_LSB 20 210 #define TCL_GSE_CMD_RESERVED_1A_MSB 31 211 #define TCL_GSE_CMD_RESERVED_1A_MASK 0xfff00000 212 213 214 /* Description TCL_CMD_TYPE 215 216 This field is used to select the type of TCL Command decriptor 217 that is queued by SW/FW. For 'TCL_GSE_CMD' this has to 218 be 1. 219 <legal 1> 220 */ 221 222 #define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 223 #define TCL_GSE_CMD_TCL_CMD_TYPE_LSB 0 224 #define TCL_GSE_CMD_TCL_CMD_TYPE_MSB 0 225 #define TCL_GSE_CMD_TCL_CMD_TYPE_MASK 0x00000001 226 227 228 /* Description RESERVED_2A 229 230 <legal 0> 231 */ 232 233 #define TCL_GSE_CMD_RESERVED_2A_OFFSET 0x00000008 234 #define TCL_GSE_CMD_RESERVED_2A_LSB 1 235 #define TCL_GSE_CMD_RESERVED_2A_MSB 31 236 #define TCL_GSE_CMD_RESERVED_2A_MASK 0xfffffffe 237 238 239 /* Description CMD_META_DATA_31_0 240 241 Meta data to be returned in the status descriptor 242 <legal all> 243 */ 244 245 #define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET 0x0000000c 246 #define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB 0 247 #define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB 31 248 #define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK 0xffffffff 249 250 251 /* Description CMD_META_DATA_63_32 252 253 Meta data to be returned in the status descriptor 254 <legal all> 255 */ 256 257 #define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET 0x00000010 258 #define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB 0 259 #define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB 31 260 #define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK 0xffffffff 261 262 263 /* Description RESERVED_5A 264 265 <legal 0> 266 */ 267 268 #define TCL_GSE_CMD_RESERVED_5A_OFFSET 0x00000014 269 #define TCL_GSE_CMD_RESERVED_5A_LSB 0 270 #define TCL_GSE_CMD_RESERVED_5A_MSB 31 271 #define TCL_GSE_CMD_RESERVED_5A_MASK 0xffffffff 272 273 274 /* Description RESERVED_6A 275 276 <legal 0> 277 */ 278 279 #define TCL_GSE_CMD_RESERVED_6A_OFFSET 0x00000018 280 #define TCL_GSE_CMD_RESERVED_6A_LSB 0 281 #define TCL_GSE_CMD_RESERVED_6A_MSB 31 282 #define TCL_GSE_CMD_RESERVED_6A_MASK 0xffffffff 283 284 285 /* Description RESERVED_7A 286 287 <legal 0> 288 */ 289 290 #define TCL_GSE_CMD_RESERVED_7A_OFFSET 0x0000001c 291 #define TCL_GSE_CMD_RESERVED_7A_LSB 0 292 #define TCL_GSE_CMD_RESERVED_7A_MSB 19 293 #define TCL_GSE_CMD_RESERVED_7A_MASK 0x000fffff 294 295 296 /* Description RING_ID 297 298 Helps with debugging when dumping ring contents. 299 <legal all> 300 */ 301 302 #define TCL_GSE_CMD_RING_ID_OFFSET 0x0000001c 303 #define TCL_GSE_CMD_RING_ID_LSB 20 304 #define TCL_GSE_CMD_RING_ID_MSB 27 305 #define TCL_GSE_CMD_RING_ID_MASK 0x0ff00000 306 307 308 /* Description LOOPING_COUNT 309 310 A count value that indicates the number of times the producer 311 of entries into the Ring has looped around the ring. 312 At initialization time, this value is set to 0. On the first 313 loop, this value is set to 1. After the max value is reached 314 allowed by the number of bits for this field, the count 315 value continues with 0 again. 316 317 In case SW is the consumer of the ring entries, it can use 318 this field to figure out up to where the producer of entries 319 has created new entries. This eliminates the need to check 320 where the "head pointer' of the ring is located once the 321 SW starts processing an interrupt indicating that new entries 322 have been put into this ring... 323 324 Also note that SW if it wants only needs to look at the 325 LSB bit of this count value. 326 <legal all> 327 */ 328 329 #define TCL_GSE_CMD_LOOPING_COUNT_OFFSET 0x0000001c 330 #define TCL_GSE_CMD_LOOPING_COUNT_LSB 28 331 #define TCL_GSE_CMD_LOOPING_COUNT_MSB 31 332 #define TCL_GSE_CMD_LOOPING_COUNT_MASK 0xf0000000 333 334 335 336 #endif // TCL_GSE_CMD 337