1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _TCL_ENTRANCE_FROM_PPE_RING_H_ 18 #define _TCL_ENTRANCE_FROM_PPE_RING_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_TCL_ENTRANCE_FROM_PPE_RING 8 23 24 25 struct tcl_entrance_from_ppe_ring { 26 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 27 uint32_t buffer_addr_lo : 32; // [31:0] 28 uint32_t buffer_addr_hi : 8, // [7:0] 29 drop_prec : 2, // [9:8] 30 fake_mac_header : 1, // [10:10] 31 known_ind : 1, // [11:11] 32 cpu_code_valid : 1, // [12:12] 33 tunnel_term_ind : 1, // [13:13] 34 tunnel_type : 1, // [14:14] 35 wifi_qos_flag : 1, // [15:15] 36 service_code : 9, // [24:16] 37 reserved_1b : 1, // [25:25] 38 int_pri : 4, // [29:26] 39 more : 1, // [30:30] 40 reserved_1a : 1; // [31:31] 41 uint32_t opaque_lo : 32; // [31:0] 42 uint32_t opaque_hi : 32; // [31:0] 43 uint32_t src_info : 16, // [15:0] 44 dst_info : 16; // [31:16] 45 uint32_t data_length : 18, // [17:0] 46 pool_id : 6, // [23:18] 47 wifi_qos : 8; // [31:24] 48 uint32_t data_offset : 12, // [11:0] 49 l4_csum_status : 1, // [12:12] 50 l3_csum_status : 1, // [13:13] 51 hash_flag : 2, // [15:14] 52 hash_value : 16; // [31:16] 53 uint32_t dscp : 8, // [7:0] 54 valid_toggle : 1, // [8:8] 55 pppoe_flag : 1, // [9:9] 56 svlan_flag : 1, // [10:10] 57 cvlan_flag : 1, // [11:11] 58 pid : 4, // [15:12] 59 l3_offset : 8, // [23:16] 60 l4_offset : 8; // [31:24] 61 #else 62 uint32_t buffer_addr_lo : 32; // [31:0] 63 uint32_t reserved_1a : 1, // [31:31] 64 more : 1, // [30:30] 65 int_pri : 4, // [29:26] 66 reserved_1b : 1, // [25:25] 67 service_code : 9, // [24:16] 68 wifi_qos_flag : 1, // [15:15] 69 tunnel_type : 1, // [14:14] 70 tunnel_term_ind : 1, // [13:13] 71 cpu_code_valid : 1, // [12:12] 72 known_ind : 1, // [11:11] 73 fake_mac_header : 1, // [10:10] 74 drop_prec : 2, // [9:8] 75 buffer_addr_hi : 8; // [7:0] 76 uint32_t opaque_lo : 32; // [31:0] 77 uint32_t opaque_hi : 32; // [31:0] 78 uint32_t dst_info : 16, // [31:16] 79 src_info : 16; // [15:0] 80 uint32_t wifi_qos : 8, // [31:24] 81 pool_id : 6, // [23:18] 82 data_length : 18; // [17:0] 83 uint32_t hash_value : 16, // [31:16] 84 hash_flag : 2, // [15:14] 85 l3_csum_status : 1, // [13:13] 86 l4_csum_status : 1, // [12:12] 87 data_offset : 12; // [11:0] 88 uint32_t l4_offset : 8, // [31:24] 89 l3_offset : 8, // [23:16] 90 pid : 4, // [15:12] 91 cvlan_flag : 1, // [11:11] 92 svlan_flag : 1, // [10:10] 93 pppoe_flag : 1, // [9:9] 94 valid_toggle : 1, // [8:8] 95 dscp : 8; // [7:0] 96 #endif 97 }; 98 99 100 /* Description BUFFER_ADDR_LO 101 102 Consumer: TCL 103 Producer: PPE DMA/SW 104 105 Lower 32 bits of the buffer address buffer_addr_31_0. 106 107 This is the address of the starting point of the buffer 108 directly from the PPE Rx Fill descriptor. TCL needs to calculate 109 the packet data address based on DATA_OFFSET. 110 <legal all> 111 */ 112 113 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_OFFSET 0x00000000 114 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_LSB 0 115 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_MSB 31 116 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_MASK 0xffffffff 117 118 119 /* Description BUFFER_ADDR_HI 120 121 Consumer: TCL/TXDMA 122 Producer: PPE DMA/SW 123 124 Higher 8 bits of the buffer address buffer_addr_39_32 (Not 125 supported PPE but could be supported by PPE in 126 future). Also see BUFFER_ADDR_LO. 127 <legal all> 128 */ 129 130 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_OFFSET 0x00000004 131 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_LSB 0 132 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_MSB 7 133 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_MASK 0x000000ff 134 135 136 /* Description DROP_PREC 137 138 Consumer: TCL/TQM 139 Producer: Switch Core 140 141 Packet drop precedence 142 143 TCL maps DROP_PREC to field msdu_color in structure 144 'TX_MSDU_DETAILS' in 'TQM_ENTRANCE_RING' if the internal 145 parameter 'DROP_PREC_ENABLE' is set (see field DST_INFO) 146 and DROP_PREC is set to a legal value. Otherwise msdu_color 147 is set to MSDU_COLORLESS. 148 149 <enum 0 PPE_drop_prec_green> 150 <enum 1 PPE_drop_prec_yellow> 151 <enum 2 PPE_drop_prec_red> 152 <legal 0-2> 153 */ 154 155 #define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_OFFSET 0x00000004 156 #define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_LSB 8 157 #define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_MSB 9 158 #define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_MASK 0x00000300 159 160 161 /* Description FAKE_MAC_HEADER 162 163 Consumer: SW 164 Producer: Switch Core 165 166 Indicates the MAC header is fake (Not supported for direct 167 switch connect) 168 0: No fake MAC header 169 1: Fake MAC header 170 <legal 0> 171 */ 172 173 #define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_OFFSET 0x00000004 174 #define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_LSB 10 175 #define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_MSB 10 176 #define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_MASK 0x00000400 177 178 179 /* Description KNOWN_IND 180 181 Consumer: TCL 182 Producer: Switch Core 183 184 Known packet indication 185 0: packet is unknown flooding. 186 1: packet is forwarded by any known entry. 187 <legal all> 188 */ 189 190 #define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_OFFSET 0x00000004 191 #define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_LSB 11 192 #define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_MSB 11 193 #define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_MASK 0x00000800 194 195 196 /* Description CPU_CODE_VALID 197 198 Consumer: SW 199 Producer: Switch Core 200 201 Indicates validity of 'CPU_CODE' (used to indicate the reason 202 the packet is sent to the CPU) (Not supported for direct 203 switch connect) 204 0: Invalid 205 1: Valid 206 <legal 0> 207 */ 208 209 #define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_OFFSET 0x00000004 210 #define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_LSB 12 211 #define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_MSB 12 212 #define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_MASK 0x00001000 213 214 215 /* Description TUNNEL_TERM_IND 216 217 Consumer: TCL 218 Producer: Switch Core 219 220 Tunnel termination indication 221 0: packet is not decapsulated 222 1: packet is decapsulated 223 <legal all> 224 */ 225 226 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_OFFSET 0x00000004 227 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_LSB 13 228 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_MSB 13 229 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_MASK 0x00002000 230 231 232 /* Description TUNNEL_TYPE 233 234 Consumer: TCL 235 Producer: Switch Core 236 237 Tunnel Type 238 0: Layer 2 tunnel 239 1: Layer 3 tunnel 240 <legal all> 241 */ 242 243 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_OFFSET 0x00000004 244 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_LSB 14 245 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_MSB 14 246 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_MASK 0x00004000 247 248 249 /* Description WIFI_QOS_FLAG 250 251 Consumer: TCL 252 Producer: Switch Core 253 254 Wi-Fi QoS Flag 255 0: If WIFI_QOS[7] is set, WIFI_QOS[3:1] provides a 3-bit 256 HLOS_TID value and HLOS_TID_overwrite is enabled, else 257 there is no overwrite. 258 1: WIFI_QOS[5:0] provides a 6-bit "flow pointer override" 259 value by using: 260 who_classify_info_sel = WIFI_QOS[5:4], 261 HLOS_TID = WIFI_QOS[3:1], 262 flow_override = WIFI_QOS[0], 263 and HLOS_TID_overwrite and flow_override_enable are set. 264 265 266 Also see field INT_PRI for another way to enable HLOS_TID_overwrite. 267 268 <legal all> 269 */ 270 271 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_OFFSET 0x00000004 272 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_LSB 15 273 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_MSB 15 274 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_MASK 0x00008000 275 276 277 /* Description SERVICE_CODE 278 279 Consumer: TCL 280 Producer: Switch Core 281 282 Opaque service code between engines 283 0: Indicates the end of service path 284 <legal all> 285 */ 286 287 #define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_OFFSET 0x00000004 288 #define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_LSB 16 289 #define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_MSB 24 290 #define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_MASK 0x01ff0000 291 292 293 /* Description RESERVED_1B 294 295 <legal 0, 1> 296 */ 297 298 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_OFFSET 0x00000004 299 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_LSB 25 300 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_MSB 25 301 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_MASK 0x02000000 302 303 304 /* Description INT_PRI 305 306 Consumer: TCL 307 Producer: Switch Core 308 309 Internal/User Priority 310 311 TCL maps INT_PRI to HLOS_TID using an internal mapping 312 table if the internal parameter 'USE_PPE_INT_PRI_FOR_TID' 313 is set (see field DST_INFO) and WIFI_QOS_FLAG is unset and 314 WIFI_QOS[7] is unset. 315 <legal all> 316 */ 317 318 #define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_OFFSET 0x00000004 319 #define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_LSB 26 320 #define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_MSB 29 321 #define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_MASK 0x3c000000 322 323 324 /* Description MORE 325 326 Consumer: TCL 327 Producer: PPE DMA 328 329 0: The last segment of packet 330 1: More segments to follow, indicating scatter/gather 331 <legal all> 332 */ 333 334 #define TCL_ENTRANCE_FROM_PPE_RING_MORE_OFFSET 0x00000004 335 #define TCL_ENTRANCE_FROM_PPE_RING_MORE_LSB 30 336 #define TCL_ENTRANCE_FROM_PPE_RING_MORE_MSB 30 337 #define TCL_ENTRANCE_FROM_PPE_RING_MORE_MASK 0x40000000 338 339 340 /* Description RESERVED_1A 341 342 <legal 0> 343 */ 344 345 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_OFFSET 0x00000004 346 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_LSB 31 347 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_MSB 31 348 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_MASK 0x80000000 349 350 351 /* Description OPAQUE_LO 352 353 Consumer: TCL/WBM/SW 354 Producer: PPE DMA/SW 355 356 Lower 32 bits of opaque SW value 357 358 OPAQUE_LO[19:0] are used for Sw_buffer_cookie with OPAQUE_LO[31:20] 359 ignored, for direct switch connect. 360 <legal all> 361 */ 362 363 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_OFFSET 0x00000008 364 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_LSB 0 365 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_MSB 31 366 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_MASK 0xffffffff 367 368 369 /* Description OPAQUE_HI 370 371 Consumer: SW 372 Producer: PPE DMA/SW 373 374 Higher 32 bits of opaque SW value, ignored completely for 375 direct switch connect 376 <legal all> 377 */ 378 379 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_OFFSET 0x0000000c 380 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_LSB 0 381 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_MSB 31 382 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_MASK 0xffffffff 383 384 385 /* Description SRC_INFO 386 387 Consumer: TCL 388 Producer: Switch Core 389 390 Source port: SRC_INFO[15:12] = 'b0010, SRC_INFO[11:0] is 391 the PORT_ID. 392 See DST_INFO for PORT_ID values. 393 <legal 8192-8447> 394 */ 395 396 #define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_OFFSET 0x00000010 397 #define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_LSB 0 398 #define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_MSB 15 399 #define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_MASK 0x0000ffff 400 401 402 /* Description DST_INFO 403 404 Consumer: TCL 405 Producer: Switch Core 406 407 Destination port or next hop information 408 409 DST_INFO[15:12] = 'b0000 indicates invalid information. 410 If DST_INFO[15:12] = 'b0001, DST_INFO[11:0] is the next 411 hop index (Not supported for direct switch connect). 412 If DST_INFO[15:12] = 'b0010, DST_INFO[11:0] is the PORT_ID, 413 which TCL can process. 414 If DST_INFO[15:12] = 'b0011, DST_INFO[11:0] is the destination 415 port bitmap (Not supported for direct switch connect). 416 417 PORT_ID: 418 0-31 indicates a physical Ethernet port. 419 32-63 indicates a link aggregation group (LAG) of ports (Not 420 supported for direct switch connect). 421 64-255 indicates a virtual port, which TCL maps 422 to Bank_id, PMAC_ID, vdev_id, To_FW and Search_index. 423 TCL also maps this to internal parameters 'USE_PPE_INT_PRI_FOR_TID' 424 and 'DROP_PREC_ENABLE' (see fields INT_PRI and DROP_PREC). 425 426 Other values are reserved. 427 <legal 0-8447,12288-16383> 428 */ 429 430 #define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_OFFSET 0x00000010 431 #define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_LSB 16 432 #define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_MSB 31 433 #define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_MASK 0xffff0000 434 435 436 /* Description DATA_LENGTH 437 438 Consumer: TCL/TXDMA 439 Producer: PPE DMA 440 441 Length of valid packet data in the current buffer in bytes 442 (Bits [17:16] not supported PPE and bits [17:14] 443 not supported) 444 <legal all> 445 */ 446 447 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_OFFSET 0x00000014 448 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_LSB 0 449 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_MSB 17 450 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_MASK 0x0003ffff 451 452 453 /* Description POOL_ID 454 455 Consumer: TCL/SW 456 Producer: PPE DMA/SW 457 458 To be used for hardware buffer management 459 460 SW must ensure 1:1 mapping between PPE Rx Fill and PPE Rx 461 completion descriptors. 462 <legal all> 463 */ 464 465 #define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_OFFSET 0x00000014 466 #define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_LSB 18 467 #define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_MSB 23 468 #define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_MASK 0x00fc0000 469 470 471 /* Description WIFI_QOS 472 473 Consumer: TCL 474 Producer: Switch Core 475 476 Wi-Fi QoS Value 477 478 TCL maps as follows: 479 who_classify_info_sel = WIFI_QOS[5:4] if WIFI_QOS_FLAG set 480 481 HLOS_TID = WIFI_QOS[3:1] if HLOS_TID_overwrite enabled 482 flow_override = WIFI_QOS [0] if WIFI_QOS_FLAG set 483 flow_override_enable = WIFI_QOS_FLAG 484 HLOS_TID_overwrite = WIFI_QOS_FLAG || WIFI_QOS[7] 485 486 WIFI_QOS[6] is ignored by TCL. 487 488 Also see field INT_PRI for another way to enable HLOS_TID_overwrite. 489 490 <legal all> 491 */ 492 493 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_OFFSET 0x00000014 494 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_LSB 24 495 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_MSB 31 496 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_MASK 0xff000000 497 498 499 /* Description DATA_OFFSET 500 501 Consumer: TCL 502 Producer: PPE DMA 503 504 Offset to the packet data from the buffer address 505 <legal all> 506 */ 507 508 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_OFFSET 0x00000018 509 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_LSB 0 510 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_MSB 11 511 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_MASK 0x00000fff 512 513 514 /* Description L4_CSUM_STATUS 515 516 Consumer: TCL 517 Producer: PPE DMA/Switch Core 518 519 Layer 4 checksum verification result 520 0: Unknown or invalid 521 1: Valid 522 The default value is 0. Only when PPE DMA performs the checksum 523 calculation and the result is correct, is this bit set. 524 525 <legal all> 526 */ 527 528 #define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_OFFSET 0x00000018 529 #define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_LSB 12 530 #define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_MSB 12 531 #define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_MASK 0x00001000 532 533 534 /* Description L3_CSUM_STATUS 535 536 Consumer: TCL 537 Producer: PPE DMA/Switch Core 538 539 Layer 3 checksum verification result 540 0: Unknown or invalid 541 1: Valid 542 The default value is 0. Only when PPE DMA performs the checksum 543 calculation and the result is correct, is this bit set. 544 545 <legal all> 546 */ 547 548 #define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_OFFSET 0x00000018 549 #define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_LSB 13 550 #define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_MSB 13 551 #define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_MASK 0x00002000 552 553 554 /* Description HASH_FLAG 555 556 Consumer: SW 557 Producer: Switch Core 558 559 Hash type 560 00: Hash invalid 561 01: 5-tuple hash 562 10: 3-tuple hash 563 11: Reserved 564 <legal 0-2> 565 */ 566 567 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_OFFSET 0x00000018 568 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_LSB 14 569 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_MSB 15 570 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_MASK 0x0000c000 571 572 573 /* Description HASH_VALUE 574 575 Consumer: SW 576 Producer: Switch Core 577 578 Hash value 579 <legal all> 580 */ 581 582 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_OFFSET 0x00000018 583 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_LSB 16 584 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_MSB 31 585 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_MASK 0xffff0000 586 587 588 /* Description DSCP 589 590 Consumer: TCL 591 Producer: PPE DMA/Switch Core 592 593 Differential Services Code Point value 594 <legal all> 595 */ 596 597 #define TCL_ENTRANCE_FROM_PPE_RING_DSCP_OFFSET 0x0000001c 598 #define TCL_ENTRANCE_FROM_PPE_RING_DSCP_LSB 0 599 #define TCL_ENTRANCE_FROM_PPE_RING_DSCP_MSB 7 600 #define TCL_ENTRANCE_FROM_PPE_RING_DSCP_MASK 0x000000ff 601 602 603 /* Description VALID_TOGGLE 604 605 Consumer: TCL 606 Producer: PPE DMA 607 608 Toggle bit to indicate the validity of the descriptor 609 The value is toggled when the producer pointer wraps around. 610 611 <legal all> 612 */ 613 614 #define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_OFFSET 0x0000001c 615 #define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_LSB 8 616 #define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_MSB 8 617 #define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_MASK 0x00000100 618 619 620 /* Description PPPOE_FLAG 621 622 Consumer: TCL 623 Producer: Switch Core 624 625 Indicates a PPPoE packet 626 0: No PPPoE header 627 1: PPPoE header exists 628 <legal all> 629 */ 630 631 #define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_OFFSET 0x0000001c 632 #define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_LSB 9 633 #define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_MSB 9 634 #define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_MASK 0x00000200 635 636 637 /* Description SVLAN_FLAG 638 639 Consumer: TCL 640 Producer: PPE DMA/Switch Core 641 642 Indicates the existence of S-VLAN tag 643 0: No S-VLAN 644 1: S-VLAN exists, including priority 645 <legal all> 646 */ 647 648 #define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_OFFSET 0x0000001c 649 #define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_LSB 10 650 #define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_MSB 10 651 #define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_MASK 0x00000400 652 653 654 /* Description CVLAN_FLAG 655 656 Consumer: TCL 657 Producer: PPE DMA/Switch Core 658 659 Indicates the existence of C-VLAN tag 660 0: No C-VLAN 661 1: C-VLAN exists, including priority 662 <legal all> 663 */ 664 665 #define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_OFFSET 0x0000001c 666 #define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_LSB 11 667 #define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_MSB 11 668 #define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_MASK 0x00000800 669 670 671 /* Description PID 672 673 Consumer: TCL 674 Producer: Switch Core 675 676 Protocol ID, indicating the protocol type of the packet 677 0: IPv4 (no supported L4) 678 1: TCP over IPv4 679 2: UDP over IPv4 680 3: UDP-Lite over IPv4 681 4: IPv6 (no supported L4) 682 5: TCP over IPv6 683 6: UDP over IPv6 684 7: UDP-Lite over IPv6 685 8: Non-IP 686 Other values are reserved 687 <legal 0-8> 688 */ 689 690 #define TCL_ENTRANCE_FROM_PPE_RING_PID_OFFSET 0x0000001c 691 #define TCL_ENTRANCE_FROM_PPE_RING_PID_LSB 12 692 #define TCL_ENTRANCE_FROM_PPE_RING_PID_MSB 15 693 #define TCL_ENTRANCE_FROM_PPE_RING_PID_MASK 0x0000f000 694 695 696 /* Description L3_OFFSET 697 698 Consumer: TCL 699 Producer: PPE DMA 700 701 Layer 3 header offset from DATA_OFFSET 702 <legal all> 703 */ 704 705 #define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_OFFSET 0x0000001c 706 #define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_LSB 16 707 #define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_MSB 23 708 #define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_MASK 0x00ff0000 709 710 711 /* Description L4_OFFSET 712 713 Consumer: TCL 714 Producer: PPE DMA 715 716 Layer 4 header offset from DATA_OFFSET 717 <legal all> 718 */ 719 720 #define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_OFFSET 0x0000001c 721 #define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_LSB 24 722 #define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_MSB 31 723 #define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_MASK 0xff000000 724 725 726 727 #endif // TCL_ENTRANCE_FROM_PPE_RING 728