1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ 18 #define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1 23 24 25 struct rx_rxpcu_classification_overview { 26 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 27 uint32_t filter_pass_mpdus : 1, // [0:0] 28 filter_pass_mpdus_fcs_ok : 1, // [1:1] 29 monitor_direct_mpdus : 1, // [2:2] 30 monitor_direct_mpdus_fcs_ok : 1, // [3:3] 31 monitor_other_mpdus : 1, // [4:4] 32 monitor_other_mpdus_fcs_ok : 1, // [5:5] 33 phyrx_abort_received : 1, // [6:6] 34 filter_pass_monitor_ovrd_mpdus : 1, // [7:7] 35 filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, // [8:8] 36 reserved_0 : 7, // [15:9] 37 phy_ppdu_id : 16; // [31:16] 38 #else 39 uint32_t phy_ppdu_id : 16, // [31:16] 40 reserved_0 : 7, // [15:9] 41 filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, // [8:8] 42 filter_pass_monitor_ovrd_mpdus : 1, // [7:7] 43 phyrx_abort_received : 1, // [6:6] 44 monitor_other_mpdus_fcs_ok : 1, // [5:5] 45 monitor_other_mpdus : 1, // [4:4] 46 monitor_direct_mpdus_fcs_ok : 1, // [3:3] 47 monitor_direct_mpdus : 1, // [2:2] 48 filter_pass_mpdus_fcs_ok : 1, // [1:1] 49 filter_pass_mpdus : 1; // [0:0] 50 #endif 51 }; 52 53 54 /* Description FILTER_PASS_MPDUS 55 56 When set, at least one Filter Pass MPDU has been received. 57 FCS might or might not have been passing. 58 59 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 60 this field is the "OR of all the users. 61 <legal all> 62 */ 63 64 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_OFFSET 0x00000000 65 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_LSB 0 66 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MSB 0 67 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MASK 0x00000001 68 69 70 /* Description FILTER_PASS_MPDUS_FCS_OK 71 72 When set, at least one Filter Pass MPDU has been received 73 that has a correct FCS. 74 75 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 76 this field is the "OR of all the users. 77 78 <legal all> 79 */ 80 81 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 82 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_LSB 1 83 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MSB 1 84 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 85 86 87 /* Description MONITOR_DIRECT_MPDUS 88 89 When set, at least one Monitor Direct MPDU has been received. 90 FCS might or might not have been passing 91 92 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 93 this field is the "OR of all the users. 94 <legal all> 95 */ 96 97 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 98 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_LSB 2 99 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MSB 2 100 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MASK 0x00000004 101 102 103 /* Description MONITOR_DIRECT_MPDUS_FCS_OK 104 105 When set, at least one Monitor Direct MPDU has been received 106 that has a correct FCS. 107 108 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 109 this field is the "OR of all the users. 110 111 <legal all> 112 */ 113 114 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 115 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 116 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 117 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 118 119 120 /* Description MONITOR_OTHER_MPDUS 121 122 When set, at least one Monitor Direct MPDU has been received. 123 FCS might or might not have been passing. 124 125 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 126 this field is the "OR of all the users. 127 <legal all> 128 */ 129 130 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 131 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_LSB 4 132 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MSB 4 133 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MASK 0x00000010 134 135 136 /* Description MONITOR_OTHER_MPDUS_FCS_OK 137 138 When set, at least one Monitor Direct MPDU has been received 139 that has a correct FCS. 140 141 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 142 this field is the "OR of all the users. 143 <legal all> 144 */ 145 146 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 147 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 148 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 149 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 150 151 152 /* Description PHYRX_ABORT_RECEIVED 153 154 When set, PPDU reception was aborted by the PHY 155 <legal all> 156 */ 157 158 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 159 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_LSB 6 160 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MSB 6 161 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MASK 0x00000040 162 163 164 /* Description FILTER_PASS_MONITOR_OVRD_MPDUS 165 166 When set, at least one 'Filter Pass Monitor Override' MPDU 167 has been received. FCS might or might not have been passing. 168 169 170 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 171 this field is the "OR of all the users. 172 <legal all> 173 */ 174 175 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 176 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 177 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 178 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 179 180 181 /* Description FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK 182 183 When set, at least one 'Filter Pass Monitor Override' MPDU 184 has been received that has a correct FCS. 185 186 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 187 this field is the "OR of all the users. 188 189 <legal all> 190 */ 191 192 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 193 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 194 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 195 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 196 197 198 /* Description RESERVED_0 199 200 <legal 0> 201 */ 202 203 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_OFFSET 0x00000000 204 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_LSB 9 205 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MSB 15 206 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MASK 0x0000fe00 207 208 209 /* Description PHY_PPDU_ID 210 211 A ppdu counter value that PHY increments for every PPDU 212 received. The counter value wraps around 213 <legal all> 214 */ 215 216 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_OFFSET 0x00000000 217 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_LSB 16 218 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MSB 31 219 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MASK 0xffff0000 220 221 222 223 #endif // RX_RXPCU_CLASSIFICATION_OVERVIEW 224