1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_PPDU_START_H_ 18 #define _RX_PPDU_START_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_RX_PPDU_START 6 23 24 #define NUM_OF_QWORDS_RX_PPDU_START 3 25 26 27 struct rx_ppdu_start { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t phy_ppdu_id : 16, // [15:0] 30 preamble_time_to_rxframe : 8, // [23:16] 31 reserved_0a : 8; // [31:24] 32 uint32_t sw_phy_meta_data : 32; // [31:0] 33 uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 34 uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 35 uint32_t rxframe_assert_timestamp : 32; // [31:0] 36 uint32_t tlv64_padding : 32; // [31:0] 37 #else 38 uint32_t reserved_0a : 8, // [31:24] 39 preamble_time_to_rxframe : 8, // [23:16] 40 phy_ppdu_id : 16; // [15:0] 41 uint32_t sw_phy_meta_data : 32; // [31:0] 42 uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 43 uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 44 uint32_t rxframe_assert_timestamp : 32; // [31:0] 45 uint32_t tlv64_padding : 32; // [31:0] 46 #endif 47 }; 48 49 50 /* Description PHY_PPDU_ID 51 52 A ppdu counter value that PHY increments for every PPDU 53 received. The counter value wraps around 54 <legal all> 55 */ 56 57 #define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 58 #define RX_PPDU_START_PHY_PPDU_ID_LSB 0 59 #define RX_PPDU_START_PHY_PPDU_ID_MSB 15 60 #define RX_PPDU_START_PHY_PPDU_ID_MASK 0x000000000000ffff 61 62 63 /* Description PREAMBLE_TIME_TO_RXFRAME 64 65 The amount of time (in us) of the frame being put on the 66 medium, and PHY raising rx_frame 67 68 From 'PHYRX_RSSI_LEGACY. Preamble_time_to_rx_frame' 69 70 <legal all> 71 */ 72 73 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000000 74 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 75 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 76 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x0000000000ff0000 77 78 79 /* Description RESERVED_0A 80 81 Reserved 82 <legal 0> 83 */ 84 85 #define RX_PPDU_START_RESERVED_0A_OFFSET 0x0000000000000000 86 #define RX_PPDU_START_RESERVED_0A_LSB 24 87 #define RX_PPDU_START_RESERVED_0A_MSB 31 88 #define RX_PPDU_START_RESERVED_0A_MASK 0x00000000ff000000 89 90 91 /* Description SW_PHY_META_DATA 92 93 SW programmed Meta data provided by the PHY. 94 95 Can be used for SW to indicate the channel the device is 96 on. 97 98 From 'PHYRX_RSSI_LEGACY.Sw_phy_meta_data' 99 */ 100 101 #define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000000 102 #define RX_PPDU_START_SW_PHY_META_DATA_LSB 32 103 #define RX_PPDU_START_SW_PHY_META_DATA_MSB 63 104 #define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff00000000 105 106 107 /* Description PPDU_START_TIMESTAMP_31_0 108 109 Timestamp that indicates when the PPDU that contained this 110 MPDU started on the medium, lower 32 bits. 111 112 The timestamp is captured by the PHY and given to the MAC 113 in 'PHYRX_RSSI_LEGACY.ppdu_start_timestamp_*.' 114 <legal all> 115 */ 116 117 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 118 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 119 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 120 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff 121 122 123 /* Description PPDU_START_TIMESTAMP_63_32 124 125 Timestamp that indicates when the PPDU that contained this 126 MPDU started on the medium, upper 32 bits. 127 128 The timestamp is captured by the PHY and given to the MAC 129 in 'PHYRX_RSSI_LEGACY.ppdu_start_timestamp_*.' 130 <legal all> 131 */ 132 133 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 134 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 135 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 136 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 137 138 139 /* Description RXFRAME_ASSERT_TIMESTAMP 140 141 MAC timer Timestamp that indicates when PHY asserted the 142 'rx_frame' signal for the reception of this PPDU 143 <legal all> 144 */ 145 146 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x0000000000000010 147 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 148 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 149 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0x00000000ffffffff 150 151 152 /* Description TLV64_PADDING 153 154 Automatic DWORD padding inserted while converting TLV32 155 to TLV64 for 64 bit ARCH 156 <legal 0> 157 */ 158 159 #define RX_PPDU_START_TLV64_PADDING_OFFSET 0x0000000000000010 160 #define RX_PPDU_START_TLV64_PADDING_LSB 32 161 #define RX_PPDU_START_TLV64_PADDING_MSB 63 162 #define RX_PPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 163 164 165 166 #endif // RX_PPDU_START 167