1 /*
2  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef _RX_MSDU_START_H_
18 #define _RX_MSDU_START_H_
19 #if !defined(__ASSEMBLER__)
20 #endif
21 
22 #define NUM_OF_DWORDS_RX_MSDU_START 10
23 
24 #define NUM_OF_QWORDS_RX_MSDU_START 5
25 
26 
27 struct rx_msdu_start {
28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
29              uint32_t rxpcu_mpdu_filter_in_category                           :  2, // [1:0]
30                       sw_frame_group_id                                       :  7, // [8:2]
31                       reserved_0                                              :  7, // [15:9]
32                       phy_ppdu_id                                             : 16; // [31:16]
33              uint32_t msdu_length                                             : 14, // [13:0]
34                       stbc                                                    :  1, // [14:14]
35                       ipsec_esp                                               :  1, // [15:15]
36                       l3_offset                                               :  7, // [22:16]
37                       ipsec_ah                                                :  1, // [23:23]
38                       l4_offset                                               :  8; // [31:24]
39              uint32_t msdu_number                                             :  8, // [7:0]
40                       decap_format                                            :  2, // [9:8]
41                       ipv4_proto                                              :  1, // [10:10]
42                       ipv6_proto                                              :  1, // [11:11]
43                       tcp_proto                                               :  1, // [12:12]
44                       udp_proto                                               :  1, // [13:13]
45                       ip_frag                                                 :  1, // [14:14]
46                       tcp_only_ack                                            :  1, // [15:15]
47                       da_is_bcast_mcast                                       :  1, // [16:16]
48                       toeplitz_hash_sel                                       :  2, // [18:17]
49                       ip_fixed_header_valid                                   :  1, // [19:19]
50                       ip_extn_header_valid                                    :  1, // [20:20]
51                       tcp_udp_header_valid                                    :  1, // [21:21]
52                       mesh_control_present                                    :  1, // [22:22]
53                       ldpc                                                    :  1, // [23:23]
54                       ip4_protocol_ip6_next_header                            :  8; // [31:24]
55              uint32_t toeplitz_hash_2_or_4                                    : 32; // [31:0]
56              uint32_t flow_id_toeplitz                                        : 32; // [31:0]
57              uint32_t user_rssi                                               :  8, // [7:0]
58                       pkt_type                                                :  4, // [11:8]
59                       sgi                                                     :  2, // [13:12]
60                       rate_mcs                                                :  4, // [17:14]
61                       receive_bandwidth                                       :  3, // [20:18]
62                       reception_type                                          :  3, // [23:21]
63                       mimo_ss_bitmap                                          :  8; // [31:24]
64              uint32_t ppdu_start_timestamp_31_0                               : 32; // [31:0]
65              uint32_t ppdu_start_timestamp_63_32                              : 32; // [31:0]
66              uint32_t sw_phy_meta_data                                        : 32; // [31:0]
67              uint32_t vlan_ctag_ci                                            : 16, // [15:0]
68                       vlan_stag_ci                                            : 16; // [31:16]
69 #else
70              uint32_t phy_ppdu_id                                             : 16, // [31:16]
71                       reserved_0                                              :  7, // [15:9]
72                       sw_frame_group_id                                       :  7, // [8:2]
73                       rxpcu_mpdu_filter_in_category                           :  2; // [1:0]
74              uint32_t l4_offset                                               :  8, // [31:24]
75                       ipsec_ah                                                :  1, // [23:23]
76                       l3_offset                                               :  7, // [22:16]
77                       ipsec_esp                                               :  1, // [15:15]
78                       stbc                                                    :  1, // [14:14]
79                       msdu_length                                             : 14; // [13:0]
80              uint32_t ip4_protocol_ip6_next_header                            :  8, // [31:24]
81                       ldpc                                                    :  1, // [23:23]
82                       mesh_control_present                                    :  1, // [22:22]
83                       tcp_udp_header_valid                                    :  1, // [21:21]
84                       ip_extn_header_valid                                    :  1, // [20:20]
85                       ip_fixed_header_valid                                   :  1, // [19:19]
86                       toeplitz_hash_sel                                       :  2, // [18:17]
87                       da_is_bcast_mcast                                       :  1, // [16:16]
88                       tcp_only_ack                                            :  1, // [15:15]
89                       ip_frag                                                 :  1, // [14:14]
90                       udp_proto                                               :  1, // [13:13]
91                       tcp_proto                                               :  1, // [12:12]
92                       ipv6_proto                                              :  1, // [11:11]
93                       ipv4_proto                                              :  1, // [10:10]
94                       decap_format                                            :  2, // [9:8]
95                       msdu_number                                             :  8; // [7:0]
96              uint32_t toeplitz_hash_2_or_4                                    : 32; // [31:0]
97              uint32_t flow_id_toeplitz                                        : 32; // [31:0]
98              uint32_t mimo_ss_bitmap                                          :  8, // [31:24]
99                       reception_type                                          :  3, // [23:21]
100                       receive_bandwidth                                       :  3, // [20:18]
101                       rate_mcs                                                :  4, // [17:14]
102                       sgi                                                     :  2, // [13:12]
103                       pkt_type                                                :  4, // [11:8]
104                       user_rssi                                               :  8; // [7:0]
105              uint32_t ppdu_start_timestamp_31_0                               : 32; // [31:0]
106              uint32_t ppdu_start_timestamp_63_32                              : 32; // [31:0]
107              uint32_t sw_phy_meta_data                                        : 32; // [31:0]
108              uint32_t vlan_stag_ci                                            : 16, // [31:16]
109                       vlan_ctag_ci                                            : 16; // [15:0]
110 #endif
111 };
112 
113 
114 /* Description		RXPCU_MPDU_FILTER_IN_CATEGORY
115 
116 			Field indicates what the reason was that this MPDU frame
117 			 was allowed to come into the receive path by RXPCU
118 			<enum 0 rxpcu_filter_pass> This MPDU passed the normal frame
119 			 filter programming of rxpcu
120 			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
121 			 regular frame filter and would have been dropped, were
122 			it not for the frame fitting into the 'monitor_client' category.
123 
124 			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
125 			regular frame filter and also did not pass the rxpcu_monitor_client
126 			 filter. It would have been dropped accept that it did pass
127 			 the 'monitor_other' category.
128 			<enum 3 rxpcu_filter_pass_monitor_ovrd> This MPDU passed
129 			 the normal frame filter programming of RXPCU but additionally
130 			 fit into the 'monitor_override_client' category.
131 			<legal 0-3>
132 */
133 
134 #define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                          0x0000000000000000
135 #define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                             0
136 #define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                             1
137 #define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                            0x0000000000000003
138 
139 
140 /* Description		SW_FRAME_GROUP_ID
141 
142 			SW processes frames based on certain classifications. This
143 			 field indicates to what sw classification this MPDU is
144 			mapped.
145 			The classification is given in priority order
146 
147 			<enum 0 sw_frame_group_NDP_frame>
148 
149 			<enum 1 sw_frame_group_Multicast_data>
150 			<enum 2 sw_frame_group_Unicast_data>
151 			<enum 3 sw_frame_group_Null_data > This includes mpdus of
152 			 type Data Null.
153 			<enum 38 sw_frame_group_QoS_Null_data> This includes QoS
154 			 Null frames except in UL MU or TB PPDUs.
155 			<enum 39 sw_frame_group_QoS_Null_data_TB> This includes
156 			QoS Null frames in UL MU or TB PPDUs.
157 
158 			<enum 4 sw_frame_group_mgmt_0000 >
159 			<enum 5 sw_frame_group_mgmt_0001 >
160 			<enum 6 sw_frame_group_mgmt_0010 >
161 			<enum 7 sw_frame_group_mgmt_0011 >
162 			<enum 8 sw_frame_group_mgmt_0100 >
163 			<enum 9 sw_frame_group_mgmt_0101 >
164 			<enum 10 sw_frame_group_mgmt_0110 >
165 			<enum 11 sw_frame_group_mgmt_0111 >
166 			<enum 12 sw_frame_group_mgmt_1000 >
167 			<enum 13 sw_frame_group_mgmt_1001 >
168 			<enum 14 sw_frame_group_mgmt_1010 >
169 			<enum 15 sw_frame_group_mgmt_1011 >
170 			<enum 16 sw_frame_group_mgmt_1100 >
171 			<enum 17 sw_frame_group_mgmt_1101 >
172 			<enum 18 sw_frame_group_mgmt_1110 >
173 			<enum 19 sw_frame_group_mgmt_1111 >
174 
175 			<enum 20 sw_frame_group_ctrl_0000 >
176 			<enum 21 sw_frame_group_ctrl_0001 >
177 			<enum 22 sw_frame_group_ctrl_0010 >
178 			<enum 23 sw_frame_group_ctrl_0011 >
179 			<enum 24 sw_frame_group_ctrl_0100 >
180 			<enum 25 sw_frame_group_ctrl_0101 >
181 			<enum 26 sw_frame_group_ctrl_0110 >
182 			<enum 27 sw_frame_group_ctrl_0111 >
183 			<enum 28 sw_frame_group_ctrl_1000 >
184 			<enum 29 sw_frame_group_ctrl_1001 >
185 			<enum 30 sw_frame_group_ctrl_1010 >
186 			<enum 31 sw_frame_group_ctrl_1011 >
187 			<enum 32 sw_frame_group_ctrl_1100 >
188 			<enum 33 sw_frame_group_ctrl_1101 >
189 			<enum 34 sw_frame_group_ctrl_1110 >
190 			<enum 35 sw_frame_group_ctrl_1111 >
191 
192 			<enum 36 sw_frame_group_unsupported> This covers type 3
193 			and protocol version != 0
194 
195 			<enum 37 sw_frame_group_phy_error> PHY reported an error
196 
197 
198 			<legal 0-39>
199 */
200 
201 #define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET                                      0x0000000000000000
202 #define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB                                         2
203 #define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB                                         8
204 #define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK                                        0x00000000000001fc
205 
206 
207 /* Description		RESERVED_0
208 
209 			<legal 0>
210 */
211 
212 #define RX_MSDU_START_RESERVED_0_OFFSET                                             0x0000000000000000
213 #define RX_MSDU_START_RESERVED_0_LSB                                                9
214 #define RX_MSDU_START_RESERVED_0_MSB                                                15
215 #define RX_MSDU_START_RESERVED_0_MASK                                               0x000000000000fe00
216 
217 
218 /* Description		PHY_PPDU_ID
219 
220 			A ppdu counter value that PHY increments for every PPDU
221 			received. The counter value wraps around
222 			<legal all>
223 */
224 
225 #define RX_MSDU_START_PHY_PPDU_ID_OFFSET                                            0x0000000000000000
226 #define RX_MSDU_START_PHY_PPDU_ID_LSB                                               16
227 #define RX_MSDU_START_PHY_PPDU_ID_MSB                                               31
228 #define RX_MSDU_START_PHY_PPDU_ID_MASK                                              0x00000000ffff0000
229 
230 
231 /* Description		MSDU_LENGTH
232 
233 			MSDU length in bytes after decapsulation.
234 
235 			This field is still valid for MPDU frames without A-MSDU.
236 			 It still represents MSDU length after decapsulation
237 */
238 
239 #define RX_MSDU_START_MSDU_LENGTH_OFFSET                                            0x0000000000000000
240 #define RX_MSDU_START_MSDU_LENGTH_LSB                                               32
241 #define RX_MSDU_START_MSDU_LENGTH_MSB                                               45
242 #define RX_MSDU_START_MSDU_LENGTH_MASK                                              0x00003fff00000000
243 
244 
245 /* Description		STBC
246 
247 			When set, use STBC transmission rates
248 */
249 
250 #define RX_MSDU_START_STBC_OFFSET                                                   0x0000000000000000
251 #define RX_MSDU_START_STBC_LSB                                                      46
252 #define RX_MSDU_START_STBC_MSB                                                      46
253 #define RX_MSDU_START_STBC_MASK                                                     0x0000400000000000
254 
255 
256 /* Description		IPSEC_ESP
257 
258 			Set if IPv4/v6 packet is using IPsec ESP
259 */
260 
261 #define RX_MSDU_START_IPSEC_ESP_OFFSET                                              0x0000000000000000
262 #define RX_MSDU_START_IPSEC_ESP_LSB                                                 47
263 #define RX_MSDU_START_IPSEC_ESP_MSB                                                 47
264 #define RX_MSDU_START_IPSEC_ESP_MASK                                                0x0000800000000000
265 
266 
267 /* Description		L3_OFFSET
268 
269 			Depending upon mode bit, this field either indicates the
270 			 L3 offset in bytes from the start of the RX_HEADER or the
271 			 IP offset in bytes from the start of the packet after decapsulation.
272 			 The latter is only valid if ipv4_proto or ipv6_proto is
273 			 set.
274 */
275 
276 #define RX_MSDU_START_L3_OFFSET_OFFSET                                              0x0000000000000000
277 #define RX_MSDU_START_L3_OFFSET_LSB                                                 48
278 #define RX_MSDU_START_L3_OFFSET_MSB                                                 54
279 #define RX_MSDU_START_L3_OFFSET_MASK                                                0x007f000000000000
280 
281 
282 /* Description		IPSEC_AH
283 
284 			Set if IPv4/v6 packet is using IPsec AH
285 */
286 
287 #define RX_MSDU_START_IPSEC_AH_OFFSET                                               0x0000000000000000
288 #define RX_MSDU_START_IPSEC_AH_LSB                                                  55
289 #define RX_MSDU_START_IPSEC_AH_MSB                                                  55
290 #define RX_MSDU_START_IPSEC_AH_MASK                                                 0x0080000000000000
291 
292 
293 /* Description		L4_OFFSET
294 
295 			Depending upon mode bit, this field either indicates the
296 			 L4 offset nin bytes from the start of RX_HEADER(only valid
297 			 if either ipv4_proto or ipv6_proto is set to 1) or indicates
298 			 the offset in bytes to the start of TCP or UDP header from
299 			 the start of the IP header after decapsulation(Only valid
300 			 if tcp_proto or udp_proto is set).  The value 0 indicates
301 			 that the offset is longer than 127 bytes.
302 */
303 
304 #define RX_MSDU_START_L4_OFFSET_OFFSET                                              0x0000000000000000
305 #define RX_MSDU_START_L4_OFFSET_LSB                                                 56
306 #define RX_MSDU_START_L4_OFFSET_MSB                                                 63
307 #define RX_MSDU_START_L4_OFFSET_MASK                                                0xff00000000000000
308 
309 
310 /* Description		MSDU_NUMBER
311 
312 			Indicates the MSDU number within a MPDU.  This value is
313 			reset to zero at the start of each MPDU.  If the number
314 			of MSDU exceeds 255 this number will wrap using modulo 256.
315 
316 */
317 
318 #define RX_MSDU_START_MSDU_NUMBER_OFFSET                                            0x0000000000000008
319 #define RX_MSDU_START_MSDU_NUMBER_LSB                                               0
320 #define RX_MSDU_START_MSDU_NUMBER_MSB                                               7
321 #define RX_MSDU_START_MSDU_NUMBER_MASK                                              0x00000000000000ff
322 
323 
324 /* Description		DECAP_FORMAT
325 
326 			Indicates the format after decapsulation:
327 
328 			<enum 0 RAW> No encapsulation
329 			<enum 1 Native_WiFi>
330 			<enum 2 Ethernet> Ethernet 2 (DIX)  or 802.3 (uses SNAP/LLC)
331 
332 			<enum 3 802_3> Indicate Ethernet
333 
334 			<legal all>
335 */
336 
337 #define RX_MSDU_START_DECAP_FORMAT_OFFSET                                           0x0000000000000008
338 #define RX_MSDU_START_DECAP_FORMAT_LSB                                              8
339 #define RX_MSDU_START_DECAP_FORMAT_MSB                                              9
340 #define RX_MSDU_START_DECAP_FORMAT_MASK                                             0x0000000000000300
341 
342 
343 /* Description		IPV4_PROTO
344 
345 			Set if L2 layer indicates IPv4 protocol.
346 */
347 
348 #define RX_MSDU_START_IPV4_PROTO_OFFSET                                             0x0000000000000008
349 #define RX_MSDU_START_IPV4_PROTO_LSB                                                10
350 #define RX_MSDU_START_IPV4_PROTO_MSB                                                10
351 #define RX_MSDU_START_IPV4_PROTO_MASK                                               0x0000000000000400
352 
353 
354 /* Description		IPV6_PROTO
355 
356 			Set if L2 layer indicates IPv6 protocol.
357 */
358 
359 #define RX_MSDU_START_IPV6_PROTO_OFFSET                                             0x0000000000000008
360 #define RX_MSDU_START_IPV6_PROTO_LSB                                                11
361 #define RX_MSDU_START_IPV6_PROTO_MSB                                                11
362 #define RX_MSDU_START_IPV6_PROTO_MASK                                               0x0000000000000800
363 
364 
365 /* Description		TCP_PROTO
366 
367 			Set if the ipv4_proto or ipv6_proto are set and the IP protocol
368 			 indicates TCP.
369 */
370 
371 #define RX_MSDU_START_TCP_PROTO_OFFSET                                              0x0000000000000008
372 #define RX_MSDU_START_TCP_PROTO_LSB                                                 12
373 #define RX_MSDU_START_TCP_PROTO_MSB                                                 12
374 #define RX_MSDU_START_TCP_PROTO_MASK                                                0x0000000000001000
375 
376 
377 /* Description		UDP_PROTO
378 
379 			Set if the ipv4_proto or ipv6_proto are set and the IP protocol
380 			 indicates UDP.
381 */
382 
383 #define RX_MSDU_START_UDP_PROTO_OFFSET                                              0x0000000000000008
384 #define RX_MSDU_START_UDP_PROTO_LSB                                                 13
385 #define RX_MSDU_START_UDP_PROTO_MSB                                                 13
386 #define RX_MSDU_START_UDP_PROTO_MASK                                                0x0000000000002000
387 
388 
389 /* Description		IP_FRAG
390 
391 			Indicates that either the IP More frag bit is set or IP
392 			frag number is non-zero.  If set indicates that this is
393 			a fragmented IP packet.
394 */
395 
396 #define RX_MSDU_START_IP_FRAG_OFFSET                                                0x0000000000000008
397 #define RX_MSDU_START_IP_FRAG_LSB                                                   14
398 #define RX_MSDU_START_IP_FRAG_MSB                                                   14
399 #define RX_MSDU_START_IP_FRAG_MASK                                                  0x0000000000004000
400 
401 
402 /* Description		TCP_ONLY_ACK
403 
404 			Set if only the TCP Ack bit is set in the TCP flags and
405 			if the TCP payload is 0.
406 */
407 
408 #define RX_MSDU_START_TCP_ONLY_ACK_OFFSET                                           0x0000000000000008
409 #define RX_MSDU_START_TCP_ONLY_ACK_LSB                                              15
410 #define RX_MSDU_START_TCP_ONLY_ACK_MSB                                              15
411 #define RX_MSDU_START_TCP_ONLY_ACK_MASK                                             0x0000000000008000
412 
413 
414 /* Description		DA_IS_BCAST_MCAST
415 
416 			The destination address is broadcast or multicast.
417 */
418 
419 #define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET                                      0x0000000000000008
420 #define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB                                         16
421 #define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB                                         16
422 #define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK                                        0x0000000000010000
423 
424 
425 /* Description		TOEPLITZ_HASH_SEL
426 
427 			Actual choosen Hash.
428 
429 			0 -> Toeplitz hash of 2-tuple (IP source address, IP destination
430 			 address)1 -> Toeplitz hash of 4-tuple (IP source address,
431 			IP destination address, L4 (TCP/UDP) source port, L4 (TCP/UDP)
432 			destination port)
433 			2 -> Toeplitz of flow_id
434 			3 -> "Zero" is used
435 			<legal all>
436 */
437 
438 #define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET                                      0x0000000000000008
439 #define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB                                         17
440 #define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB                                         18
441 #define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK                                        0x0000000000060000
442 
443 
444 /* Description		IP_FIXED_HEADER_VALID
445 
446 			Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed
447 			fully within first 256 bytes of the packet
448 */
449 
450 #define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET                                  0x0000000000000008
451 #define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB                                     19
452 #define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB                                     19
453 #define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK                                    0x0000000000080000
454 
455 
456 /* Description		IP_EXTN_HEADER_VALID
457 
458 			IPv6/IPv6 header, including IPv4 options and recognizable
459 			 extension headers parsed fully within first 256 bytes of
460 			 the packet
461 */
462 
463 #define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET                                   0x0000000000000008
464 #define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB                                      20
465 #define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB                                      20
466 #define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK                                     0x0000000000100000
467 
468 
469 /* Description		TCP_UDP_HEADER_VALID
470 
471 			Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP
472 			header parsed fully within first 256 bytes of the packet
473 
474 */
475 
476 #define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET                                   0x0000000000000008
477 #define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB                                      21
478 #define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB                                      21
479 #define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK                                     0x0000000000200000
480 
481 
482 /* Description		MESH_CONTROL_PRESENT
483 
484 			When set, this MSDU includes the 'Mesh Control' field
485 			<legal all>
486 */
487 
488 #define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET                                   0x0000000000000008
489 #define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB                                      22
490 #define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB                                      22
491 #define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK                                     0x0000000000400000
492 
493 
494 /* Description		LDPC
495 
496 			When set, indicates that LDPC coding was used.
497 			<legal all>
498 */
499 
500 #define RX_MSDU_START_LDPC_OFFSET                                                   0x0000000000000008
501 #define RX_MSDU_START_LDPC_LSB                                                      23
502 #define RX_MSDU_START_LDPC_MSB                                                      23
503 #define RX_MSDU_START_LDPC_MASK                                                     0x0000000000800000
504 
505 
506 /* Description		IP4_PROTOCOL_IP6_NEXT_HEADER
507 
508 			For IPv4 this is the 8 bit protocol field (when ipv4_proto
509 			 is set).  For IPv6 this is the 8 bit next_header field (when
510 			 ipv6_proto is set).
511 */
512 
513 #define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET                           0x0000000000000008
514 #define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB                              24
515 #define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB                              31
516 #define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK                             0x00000000ff000000
517 
518 
519 /* Description		TOEPLITZ_HASH_2_OR_4
520 
521 			Controlled by multiple RxOLE registers for TCP/UDP over
522 			IPv4/IPv6 - Either, Toeplitz hash computed over 2-tuple
523 			IPv4 or IPv6 src/dest addresses is reported; or, Toeplitz
524 			 hash computed over 4-tuple IPv4 or IPv6 src/dest addresses
525 			 and src/dest ports is reported. The Flow_id_toeplitz hash
526 			 can also be reported here. Usually the hash reported here
527 			 is the one used for hash-based REO routing (see use_flow_id_toeplitz_clfy
528 			 in 'RXPT_CLASSIFY_INFO').
529 
530 			Optionally the 3-tuple Toeplitz hash over IPv4
531 			or IPv6 src/dest addresses and L4 protocol can be reported
532 			 here.
533 */
534 
535 #define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET                                   0x0000000000000008
536 #define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB                                      32
537 #define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB                                      63
538 #define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK                                     0xffffffff00000000
539 
540 
541 /* Description		FLOW_ID_TOEPLITZ
542 
543 			Toeplitz hash of 5-tuple
544 			{IP source address, IP destination address, IP source port,
545 			IP destination port, L4 protocol}  in case of non-IPSec.
546 
547 			In case of IPSec - Toeplitz hash of 4-tuple
548 			{IP source address, IP destination address, SPI, L4 protocol}
549 
550 			Optionally the 3-tuple Toeplitz hash over IPv4
551 			or IPv6 src/dest addresses and L4 protocol can be reported
552 			 here.
553 
554 			The relevant Toeplitz key registers are provided in RxOLE's
555 			 instance of common parser module. These registers are separate
556 			 from the Toeplitz keys used by ASE/FSE modules inside RxOLE.The
557 			 actual value will be passed on from common parser module
558 			 to RxOLE in one of the WHO_* TLVs.
559 			<legal all>
560 */
561 
562 #define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET                                       0x0000000000000010
563 #define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB                                          0
564 #define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB                                          31
565 #define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK                                         0x00000000ffffffff
566 
567 
568 /* Description		USER_RSSI
569 
570 			RSSI for this user
571 			<legal all>
572 */
573 
574 #define RX_MSDU_START_USER_RSSI_OFFSET                                              0x0000000000000010
575 #define RX_MSDU_START_USER_RSSI_LSB                                                 32
576 #define RX_MSDU_START_USER_RSSI_MSB                                                 39
577 #define RX_MSDU_START_USER_RSSI_MASK                                                0x000000ff00000000
578 
579 
580 /* Description		PKT_TYPE
581 
582 			Packet type:
583 			<enum 0 dot11a>802.11a PPDU type
584 			<enum 1 dot11b>802.11b PPDU type
585 			<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
586 			<enum 3 dot11ac>802.11ac PPDU type
587 			<enum 4 dot11ax>802.11ax PPDU type
588 			<enum 5 dot11ba>802.11ba (WUR) PPDU type
589 			<enum 6 dot11be>802.11be PPDU type
590 			<enum 7 dot11az>802.11az (ranging) PPDU type
591 			<enum 8 dot11n_gf>802.11n Green Field PPDU type (unsupported
592 			 & aborted)
593 */
594 
595 #define RX_MSDU_START_PKT_TYPE_OFFSET                                               0x0000000000000010
596 #define RX_MSDU_START_PKT_TYPE_LSB                                                  40
597 #define RX_MSDU_START_PKT_TYPE_MSB                                                  43
598 #define RX_MSDU_START_PKT_TYPE_MASK                                                 0x00000f0000000000
599 
600 
601 /* Description		SGI
602 
603 			Field only valid when pkt type is HT, VHT or HE.
604 
605 			<enum 0     0_8_us_sgi > Legacy normal GI. Can also be used
606 			 for HE
607 			<enum 1     0_4_us_sgi > Legacy short GI. Can also be used
608 			 for HE
609 			<enum 2     1_6_us_sgi > HE related GI
610 			<enum 3     3_2_us_sgi > HE related GI
611 			<legal 0 - 3>
612 */
613 
614 #define RX_MSDU_START_SGI_OFFSET                                                    0x0000000000000010
615 #define RX_MSDU_START_SGI_LSB                                                       44
616 #define RX_MSDU_START_SGI_MSB                                                       45
617 #define RX_MSDU_START_SGI_MASK                                                      0x0000300000000000
618 
619 
620 /* Description		RATE_MCS
621 
622 			For details, refer to  MCS_TYPE description
623 			Note: This is "rate" in case of 11a/11b
624 
625 			<legal all>
626 */
627 
628 #define RX_MSDU_START_RATE_MCS_OFFSET                                               0x0000000000000010
629 #define RX_MSDU_START_RATE_MCS_LSB                                                  46
630 #define RX_MSDU_START_RATE_MCS_MSB                                                  49
631 #define RX_MSDU_START_RATE_MCS_MASK                                                 0x0003c00000000000
632 
633 
634 /* Description		RECEIVE_BANDWIDTH
635 
636 			Full receive Bandwidth
637 
638 			<enum 0 20_mhz>20 Mhz BW
639 			<enum 1 40_mhz>40 Mhz BW
640 			<enum 2 80_mhz>80 Mhz BW
641 			<enum 3 160_mhz>160 Mhz BW
642 			<enum 4 320_mhz>320 Mhz BW
643 			<enum 5 240_mhz>240 Mhz BW
644 */
645 
646 #define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET                                      0x0000000000000010
647 #define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB                                         50
648 #define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB                                         52
649 #define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK                                        0x001c000000000000
650 
651 
652 /* Description		RECEPTION_TYPE
653 
654 			Indicates what type of reception this is.
655 			<enum 0     reception_type_SU > Basic SU reception (not
656 			part of OFDMA or MIMO)
657 			<enum 1     reception_type_MU_MIMO > This is related to
658 			DL type of reception
659 			<enum 2     reception_type_MU_OFDMA >  This is related to
660 			 DL type of reception
661 			<enum 3     reception_type_MU_OFDMA_MIMO >  This is related
662 			 to DL type of reception
663 			<enum 4     reception_type_UL_MU_MIMO > This is related
664 			to UL type of reception
665 			<enum 5     reception_type_UL_MU_OFDMA >  This is related
666 			 to UL type of reception
667 			<enum 6     reception_type_UL_MU_OFDMA_MIMO >  This is related
668 			 to UL type of reception
669 
670 			<legal 0-6>
671 */
672 
673 #define RX_MSDU_START_RECEPTION_TYPE_OFFSET                                         0x0000000000000010
674 #define RX_MSDU_START_RECEPTION_TYPE_LSB                                            53
675 #define RX_MSDU_START_RECEPTION_TYPE_MSB                                            55
676 #define RX_MSDU_START_RECEPTION_TYPE_MASK                                           0x00e0000000000000
677 
678 
679 /* Description		MIMO_SS_BITMAP
680 
681 			Field only valid when Reception_type for the MPDU from this
682 			 STA is some form of MIMO reception
683 
684 			Bitmap, with each bit indicating if the related spatial
685 			stream is used for this STA
686 			LSB related to SS 0
687 
688 			0: spatial stream not used for this reception
689 			1: spatial stream used for this reception
690 
691 			<legal all>
692 */
693 
694 #define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET                                         0x0000000000000010
695 #define RX_MSDU_START_MIMO_SS_BITMAP_LSB                                            56
696 #define RX_MSDU_START_MIMO_SS_BITMAP_MSB                                            63
697 #define RX_MSDU_START_MIMO_SS_BITMAP_MASK                                           0xff00000000000000
698 
699 
700 /* Description		PPDU_START_TIMESTAMP_31_0
701 
702 			Timestamp that indicates when the PPDU that contained this
703 			 MPDU started on the medium, lower 32 bits
704 			<legal all>
705 */
706 
707 #define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET                              0x0000000000000018
708 #define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB                                 0
709 #define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB                                 31
710 #define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK                                0x00000000ffffffff
711 
712 
713 /* Description		PPDU_START_TIMESTAMP_63_32
714 
715 			Timestamp that indicates when the PPDU that contained this
716 			 MPDU started on the medium, upper 32 bits
717 			<legal all>
718 */
719 
720 #define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET                             0x0000000000000018
721 #define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB                                32
722 #define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB                                63
723 #define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK                               0xffffffff00000000
724 
725 
726 /* Description		SW_PHY_META_DATA
727 
728 			SW programmed Meta data provided by the PHY.
729 
730 			Can be used for SW to indicate the channel the device is
731 			 on.
732 			<legal all>
733 */
734 
735 #define RX_MSDU_START_SW_PHY_META_DATA_OFFSET                                       0x0000000000000020
736 #define RX_MSDU_START_SW_PHY_META_DATA_LSB                                          0
737 #define RX_MSDU_START_SW_PHY_META_DATA_MSB                                          31
738 #define RX_MSDU_START_SW_PHY_META_DATA_MASK                                         0x00000000ffffffff
739 
740 
741 /* Description		VLAN_CTAG_CI
742 
743 			2 bytes of C-VLAN Tag Control Information from WHO_L2_LLC
744 
745 */
746 
747 #define RX_MSDU_START_VLAN_CTAG_CI_OFFSET                                           0x0000000000000020
748 #define RX_MSDU_START_VLAN_CTAG_CI_LSB                                              32
749 #define RX_MSDU_START_VLAN_CTAG_CI_MSB                                              47
750 #define RX_MSDU_START_VLAN_CTAG_CI_MASK                                             0x0000ffff00000000
751 
752 
753 /* Description		VLAN_STAG_CI
754 
755 			2 bytes of S-VLAN Tag Control Information from WHO_L2_LLC
756 			 in case of double VLAN
757 */
758 
759 #define RX_MSDU_START_VLAN_STAG_CI_OFFSET                                           0x0000000000000020
760 #define RX_MSDU_START_VLAN_STAG_CI_LSB                                              48
761 #define RX_MSDU_START_VLAN_STAG_CI_MSB                                              63
762 #define RX_MSDU_START_VLAN_STAG_CI_MASK                                             0xffff000000000000
763 
764 
765 
766 #endif   // RX_MSDU_START
767