1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_FRAME_1K_BITMAP_ACK_H_ 18 #define _RX_FRAME_1K_BITMAP_ACK_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 38 23 24 #define NUM_OF_QWORDS_RX_FRAME_1K_BITMAP_ACK 19 25 26 27 struct rx_frame_1k_bitmap_ack { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t reserved_0a : 5, // [4:0] 30 ba_bitmap_size : 2, // [6:5] 31 reserved_0b : 3, // [9:7] 32 ba_tid : 4, // [13:10] 33 sta_full_aid : 13, // [26:14] 34 reserved_0c : 5; // [31:27] 35 uint32_t addr1_31_0 : 32; // [31:0] 36 uint32_t addr1_47_32 : 16, // [15:0] 37 addr2_15_0 : 16; // [31:16] 38 uint32_t addr2_47_16 : 32; // [31:0] 39 uint32_t ba_ts_ctrl : 16, // [15:0] 40 ba_ts_seq : 16; // [31:16] 41 uint32_t ba_ts_bitmap_31_0 : 32; // [31:0] 42 uint32_t ba_ts_bitmap_63_32 : 32; // [31:0] 43 uint32_t ba_ts_bitmap_95_64 : 32; // [31:0] 44 uint32_t ba_ts_bitmap_127_96 : 32; // [31:0] 45 uint32_t ba_ts_bitmap_159_128 : 32; // [31:0] 46 uint32_t ba_ts_bitmap_191_160 : 32; // [31:0] 47 uint32_t ba_ts_bitmap_223_192 : 32; // [31:0] 48 uint32_t ba_ts_bitmap_255_224 : 32; // [31:0] 49 uint32_t ba_ts_bitmap_287_256 : 32; // [31:0] 50 uint32_t ba_ts_bitmap_319_288 : 32; // [31:0] 51 uint32_t ba_ts_bitmap_351_320 : 32; // [31:0] 52 uint32_t ba_ts_bitmap_383_352 : 32; // [31:0] 53 uint32_t ba_ts_bitmap_415_384 : 32; // [31:0] 54 uint32_t ba_ts_bitmap_447_416 : 32; // [31:0] 55 uint32_t ba_ts_bitmap_479_448 : 32; // [31:0] 56 uint32_t ba_ts_bitmap_511_480 : 32; // [31:0] 57 uint32_t ba_ts_bitmap_543_512 : 32; // [31:0] 58 uint32_t ba_ts_bitmap_575_544 : 32; // [31:0] 59 uint32_t ba_ts_bitmap_607_576 : 32; // [31:0] 60 uint32_t ba_ts_bitmap_639_608 : 32; // [31:0] 61 uint32_t ba_ts_bitmap_671_640 : 32; // [31:0] 62 uint32_t ba_ts_bitmap_703_672 : 32; // [31:0] 63 uint32_t ba_ts_bitmap_735_704 : 32; // [31:0] 64 uint32_t ba_ts_bitmap_767_736 : 32; // [31:0] 65 uint32_t ba_ts_bitmap_799_768 : 32; // [31:0] 66 uint32_t ba_ts_bitmap_831_800 : 32; // [31:0] 67 uint32_t ba_ts_bitmap_863_832 : 32; // [31:0] 68 uint32_t ba_ts_bitmap_895_864 : 32; // [31:0] 69 uint32_t ba_ts_bitmap_927_896 : 32; // [31:0] 70 uint32_t ba_ts_bitmap_959_928 : 32; // [31:0] 71 uint32_t ba_ts_bitmap_991_960 : 32; // [31:0] 72 uint32_t ba_ts_bitmap_1023_992 : 32; // [31:0] 73 uint32_t tlv64_padding : 32; // [31:0] 74 #else 75 uint32_t reserved_0c : 5, // [31:27] 76 sta_full_aid : 13, // [26:14] 77 ba_tid : 4, // [13:10] 78 reserved_0b : 3, // [9:7] 79 ba_bitmap_size : 2, // [6:5] 80 reserved_0a : 5; // [4:0] 81 uint32_t addr1_31_0 : 32; // [31:0] 82 uint32_t addr2_15_0 : 16, // [31:16] 83 addr1_47_32 : 16; // [15:0] 84 uint32_t addr2_47_16 : 32; // [31:0] 85 uint32_t ba_ts_seq : 16, // [31:16] 86 ba_ts_ctrl : 16; // [15:0] 87 uint32_t ba_ts_bitmap_31_0 : 32; // [31:0] 88 uint32_t ba_ts_bitmap_63_32 : 32; // [31:0] 89 uint32_t ba_ts_bitmap_95_64 : 32; // [31:0] 90 uint32_t ba_ts_bitmap_127_96 : 32; // [31:0] 91 uint32_t ba_ts_bitmap_159_128 : 32; // [31:0] 92 uint32_t ba_ts_bitmap_191_160 : 32; // [31:0] 93 uint32_t ba_ts_bitmap_223_192 : 32; // [31:0] 94 uint32_t ba_ts_bitmap_255_224 : 32; // [31:0] 95 uint32_t ba_ts_bitmap_287_256 : 32; // [31:0] 96 uint32_t ba_ts_bitmap_319_288 : 32; // [31:0] 97 uint32_t ba_ts_bitmap_351_320 : 32; // [31:0] 98 uint32_t ba_ts_bitmap_383_352 : 32; // [31:0] 99 uint32_t ba_ts_bitmap_415_384 : 32; // [31:0] 100 uint32_t ba_ts_bitmap_447_416 : 32; // [31:0] 101 uint32_t ba_ts_bitmap_479_448 : 32; // [31:0] 102 uint32_t ba_ts_bitmap_511_480 : 32; // [31:0] 103 uint32_t ba_ts_bitmap_543_512 : 32; // [31:0] 104 uint32_t ba_ts_bitmap_575_544 : 32; // [31:0] 105 uint32_t ba_ts_bitmap_607_576 : 32; // [31:0] 106 uint32_t ba_ts_bitmap_639_608 : 32; // [31:0] 107 uint32_t ba_ts_bitmap_671_640 : 32; // [31:0] 108 uint32_t ba_ts_bitmap_703_672 : 32; // [31:0] 109 uint32_t ba_ts_bitmap_735_704 : 32; // [31:0] 110 uint32_t ba_ts_bitmap_767_736 : 32; // [31:0] 111 uint32_t ba_ts_bitmap_799_768 : 32; // [31:0] 112 uint32_t ba_ts_bitmap_831_800 : 32; // [31:0] 113 uint32_t ba_ts_bitmap_863_832 : 32; // [31:0] 114 uint32_t ba_ts_bitmap_895_864 : 32; // [31:0] 115 uint32_t ba_ts_bitmap_927_896 : 32; // [31:0] 116 uint32_t ba_ts_bitmap_959_928 : 32; // [31:0] 117 uint32_t ba_ts_bitmap_991_960 : 32; // [31:0] 118 uint32_t ba_ts_bitmap_1023_992 : 32; // [31:0] 119 uint32_t tlv64_padding : 32; // [31:0] 120 #endif 121 }; 122 123 124 /* Description RESERVED_0A 125 126 <legal 0> 127 */ 128 129 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 130 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB 0 131 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB 4 132 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK 0x000000000000001f 133 134 135 /* Description BA_BITMAP_SIZE 136 137 <enum 0 BA_bitmap_512 > Bitmap size set to window of 512 138 139 <enum 1 BA_bitmap_1024 > Bitmap size set to window of 1024 140 141 142 <legal 0-1> 143 */ 144 145 #define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 146 #define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 147 #define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 148 #define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 149 150 151 /* Description RESERVED_0B 152 153 <legal 0> 154 */ 155 156 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 157 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB 7 158 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB 9 159 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK 0x0000000000000380 160 161 162 /* Description BA_TID 163 164 The tid for the BA 165 */ 166 167 #define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 168 #define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB 10 169 #define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB 13 170 #define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 171 172 173 /* Description STA_FULL_AID 174 175 The full AID of this station. 176 */ 177 178 #define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 179 #define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB 14 180 #define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB 26 181 #define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 182 183 184 /* Description RESERVED_0C 185 186 <legal 0> 187 */ 188 189 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET 0x0000000000000000 190 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB 27 191 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB 31 192 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK 0x00000000f8000000 193 194 195 /* Description ADDR1_31_0 196 197 lower 32 bits of addr1 of the received frame 198 */ 199 200 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000000 201 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB 32 202 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB 63 203 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff00000000 204 205 206 /* Description ADDR1_47_32 207 208 upper 16 bits of addr1 of the received frame 209 */ 210 211 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 212 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB 0 213 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB 15 214 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK 0x000000000000ffff 215 216 217 /* Description ADDR2_15_0 218 219 lower 16 bits of addr2 of the received frame 220 */ 221 222 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 223 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB 16 224 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB 31 225 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK 0x00000000ffff0000 226 227 228 /* Description ADDR2_47_16 229 230 upper 32 bits of addr2 of the received frame 231 */ 232 233 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000008 234 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB 32 235 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB 63 236 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff00000000 237 238 239 /* Description BA_TS_CTRL 240 241 Transmit BA control 242 RXPCU assumes the C-BA format, NOT M-BA format. 243 In case TXPCU is responding with M-BA, TXPCU will ignore 244 this field. TXPCU will generate it 245 */ 246 247 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 248 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB 0 249 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB 15 250 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK 0x000000000000ffff 251 252 253 /* Description BA_TS_SEQ 254 255 Transmit BA sequence number. 256 */ 257 258 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 259 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB 16 260 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB 31 261 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK 0x00000000ffff0000 262 263 264 /* Description BA_TS_BITMAP_31_0 265 266 Transmit BA bitmap[31:0] 267 */ 268 269 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000010 270 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 32 271 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 63 272 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff00000000 273 274 275 /* Description BA_TS_BITMAP_63_32 276 277 Transmit BA bitmap[63:32] 278 */ 279 280 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 281 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 282 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 283 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0x00000000ffffffff 284 285 286 /* Description BA_TS_BITMAP_95_64 287 288 Transmit BA bitmap[95:64] 289 */ 290 291 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000018 292 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 32 293 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 63 294 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff00000000 295 296 297 /* Description BA_TS_BITMAP_127_96 298 299 Transmit BA bitmap[127:96] 300 */ 301 302 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 303 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 304 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 305 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0x00000000ffffffff 306 307 308 /* Description BA_TS_BITMAP_159_128 309 310 Transmit BA bitmap[159:128] 311 */ 312 313 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000020 314 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 32 315 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 63 316 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff00000000 317 318 319 /* Description BA_TS_BITMAP_191_160 320 321 Transmit BA bitmap[191:160] 322 */ 323 324 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 325 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 326 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 327 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0x00000000ffffffff 328 329 330 /* Description BA_TS_BITMAP_223_192 331 332 Transmit BA bitmap[223:192] 333 */ 334 335 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000028 336 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 32 337 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 63 338 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff00000000 339 340 341 /* Description BA_TS_BITMAP_255_224 342 343 Transmit BA bitmap[255:224] 344 */ 345 346 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 347 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 348 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 349 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0x00000000ffffffff 350 351 352 /* Description BA_TS_BITMAP_287_256 353 354 Transmit BA bitmap[287:256] 355 */ 356 357 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET 0x0000000000000030 358 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB 32 359 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB 63 360 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK 0xffffffff00000000 361 362 363 /* Description BA_TS_BITMAP_319_288 364 365 Transmit BA bitmap[319:288] 366 */ 367 368 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET 0x0000000000000038 369 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB 0 370 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB 31 371 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK 0x00000000ffffffff 372 373 374 /* Description BA_TS_BITMAP_351_320 375 376 Transmit BA bitmap[351:320] 377 */ 378 379 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET 0x0000000000000038 380 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB 32 381 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB 63 382 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK 0xffffffff00000000 383 384 385 /* Description BA_TS_BITMAP_383_352 386 387 Transmit BA bitmap[383:352] 388 */ 389 390 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET 0x0000000000000040 391 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB 0 392 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB 31 393 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK 0x00000000ffffffff 394 395 396 /* Description BA_TS_BITMAP_415_384 397 398 Transmit BA bitmap[415:384] 399 */ 400 401 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET 0x0000000000000040 402 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB 32 403 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB 63 404 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK 0xffffffff00000000 405 406 407 /* Description BA_TS_BITMAP_447_416 408 409 Transmit BA bitmap[447:416] 410 */ 411 412 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET 0x0000000000000048 413 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB 0 414 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB 31 415 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK 0x00000000ffffffff 416 417 418 /* Description BA_TS_BITMAP_479_448 419 420 Transmit BA bitmap[479:448] 421 */ 422 423 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET 0x0000000000000048 424 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB 32 425 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB 63 426 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK 0xffffffff00000000 427 428 429 /* Description BA_TS_BITMAP_511_480 430 431 Transmit BA bitmap[511:480] 432 */ 433 434 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET 0x0000000000000050 435 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB 0 436 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB 31 437 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK 0x00000000ffffffff 438 439 440 /* Description BA_TS_BITMAP_543_512 441 442 Transmit BA bitmap[543:512] 443 */ 444 445 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET 0x0000000000000050 446 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB 32 447 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB 63 448 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK 0xffffffff00000000 449 450 451 /* Description BA_TS_BITMAP_575_544 452 453 Transmit BA bitmap[575:544] 454 */ 455 456 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET 0x0000000000000058 457 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB 0 458 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB 31 459 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK 0x00000000ffffffff 460 461 462 /* Description BA_TS_BITMAP_607_576 463 464 Transmit BA bitmap[607:576] 465 */ 466 467 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET 0x0000000000000058 468 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB 32 469 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB 63 470 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK 0xffffffff00000000 471 472 473 /* Description BA_TS_BITMAP_639_608 474 475 Transmit BA bitmap[639:608] 476 */ 477 478 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET 0x0000000000000060 479 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB 0 480 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB 31 481 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK 0x00000000ffffffff 482 483 484 /* Description BA_TS_BITMAP_671_640 485 486 Transmit BA bitmap[671:640] 487 */ 488 489 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET 0x0000000000000060 490 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB 32 491 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB 63 492 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK 0xffffffff00000000 493 494 495 /* Description BA_TS_BITMAP_703_672 496 497 Transmit BA bitmap[703:672] 498 */ 499 500 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET 0x0000000000000068 501 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB 0 502 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB 31 503 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK 0x00000000ffffffff 504 505 506 /* Description BA_TS_BITMAP_735_704 507 508 Transmit BA bitmap[735:704] 509 */ 510 511 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET 0x0000000000000068 512 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB 32 513 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB 63 514 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK 0xffffffff00000000 515 516 517 /* Description BA_TS_BITMAP_767_736 518 519 Transmit BA bitmap[767:736] 520 */ 521 522 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET 0x0000000000000070 523 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB 0 524 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB 31 525 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK 0x00000000ffffffff 526 527 528 /* Description BA_TS_BITMAP_799_768 529 530 Transmit BA bitmap[799:768] 531 */ 532 533 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET 0x0000000000000070 534 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB 32 535 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB 63 536 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK 0xffffffff00000000 537 538 539 /* Description BA_TS_BITMAP_831_800 540 541 Transmit BA bitmap[831:800] 542 */ 543 544 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET 0x0000000000000078 545 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB 0 546 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB 31 547 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK 0x00000000ffffffff 548 549 550 /* Description BA_TS_BITMAP_863_832 551 552 Transmit BA bitmap[863:832] 553 */ 554 555 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET 0x0000000000000078 556 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB 32 557 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB 63 558 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK 0xffffffff00000000 559 560 561 /* Description BA_TS_BITMAP_895_864 562 563 Transmit BA bitmap[895:864] 564 */ 565 566 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET 0x0000000000000080 567 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB 0 568 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB 31 569 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK 0x00000000ffffffff 570 571 572 /* Description BA_TS_BITMAP_927_896 573 574 Transmit BA bitmap[927:896] 575 */ 576 577 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET 0x0000000000000080 578 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB 32 579 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB 63 580 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK 0xffffffff00000000 581 582 583 /* Description BA_TS_BITMAP_959_928 584 585 Transmit BA bitmap[959:928] 586 */ 587 588 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET 0x0000000000000088 589 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB 0 590 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB 31 591 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK 0x00000000ffffffff 592 593 594 /* Description BA_TS_BITMAP_991_960 595 596 Transmit BA bitmap[991:960] 597 */ 598 599 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET 0x0000000000000088 600 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB 32 601 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB 63 602 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK 0xffffffff00000000 603 604 605 /* Description BA_TS_BITMAP_1023_992 606 607 Transmit BA bitmap[1023:992] 608 */ 609 610 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET 0x0000000000000090 611 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB 0 612 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB 31 613 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK 0x00000000ffffffff 614 615 616 /* Description TLV64_PADDING 617 618 Automatic DWORD padding inserted while converting TLV32 619 to TLV64 for 64 bit ARCH 620 <legal 0> 621 */ 622 623 #define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_OFFSET 0x0000000000000090 624 #define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_LSB 32 625 #define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MSB 63 626 #define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MASK 0xffffffff00000000 627 628 629 630 #endif // RX_FRAME_1K_BITMAP_ACK 631