1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _REO_UNBLOCK_CACHE_H_ 18 #define _REO_UNBLOCK_CACHE_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "uniform_reo_cmd_header.h" 23 #define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 10 24 25 #define NUM_OF_QWORDS_REO_UNBLOCK_CACHE 5 26 27 28 struct reo_unblock_cache { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct uniform_reo_cmd_header cmd_header; 31 uint32_t unblock_type : 1, // [0:0] 32 cache_block_resource_index : 2, // [2:1] 33 reserved_1a : 29; // [31:3] 34 uint32_t reserved_2a : 32; // [31:0] 35 uint32_t reserved_3a : 32; // [31:0] 36 uint32_t reserved_4a : 32; // [31:0] 37 uint32_t reserved_5a : 32; // [31:0] 38 uint32_t reserved_6a : 32; // [31:0] 39 uint32_t reserved_7a : 32; // [31:0] 40 uint32_t reserved_8a : 32; // [31:0] 41 uint32_t tlv64_padding : 32; // [31:0] 42 #else 43 struct uniform_reo_cmd_header cmd_header; 44 uint32_t reserved_1a : 29, // [31:3] 45 cache_block_resource_index : 2, // [2:1] 46 unblock_type : 1; // [0:0] 47 uint32_t reserved_2a : 32; // [31:0] 48 uint32_t reserved_3a : 32; // [31:0] 49 uint32_t reserved_4a : 32; // [31:0] 50 uint32_t reserved_5a : 32; // [31:0] 51 uint32_t reserved_6a : 32; // [31:0] 52 uint32_t reserved_7a : 32; // [31:0] 53 uint32_t reserved_8a : 32; // [31:0] 54 uint32_t tlv64_padding : 32; // [31:0] 55 #endif 56 }; 57 58 59 /* Description CMD_HEADER 60 61 Consumer: REO 62 Producer: SW 63 64 Details for command execution tracking purposes. 65 */ 66 67 68 /* Description REO_CMD_NUMBER 69 70 Consumer: REO/SW/DEBUG 71 Producer: SW 72 73 This number can be used by SW to track, identify and link 74 the created commands with the command statusses 75 76 77 <legal all> 78 */ 79 80 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 81 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 82 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 83 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 84 85 86 /* Description REO_STATUS_REQUIRED 87 88 Consumer: REO 89 Producer: SW 90 91 <enum 0 NoStatus> REO does not need to generate a status 92 TLV for the execution of this command 93 <enum 1 StatusRequired> REO shall generate a status TLV 94 for the execution of this command 95 96 <legal all> 97 */ 98 99 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 100 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 101 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 102 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 103 104 105 /* Description RESERVED_0A 106 107 <legal 0> 108 */ 109 110 #define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 111 #define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 112 #define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 113 #define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 114 115 116 /* Description UNBLOCK_TYPE 117 118 Unblock type 119 120 <enum 0 unblock_resource_index> Unblock a block resource, 121 whose index is given in field 'cache_block_resource_index'. 122 123 If the indicated blocking resource is not in use (=> not 124 blocking an address at the moment), the command status 125 will indicate an error. 126 127 <enum 1 unblock_cache> The entire cache usage is unblocked. 128 129 If the entire cache is not in a blocked mode at the moment 130 this command is received, the command status will indicate 131 an error. 132 Note that unlocking the "entire cache" has no changes to 133 the current settings of the blocking resource settings 134 135 <legal all> 136 */ 137 138 #define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_OFFSET 0x0000000000000000 139 #define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_LSB 32 140 #define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MSB 32 141 #define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MASK 0x0000000100000000 142 143 144 /* Description CACHE_BLOCK_RESOURCE_INDEX 145 146 Field not valid when field Unblock_type is set to unblock_cache. 147 148 149 Indicates which of the four blocking resources in REO should 150 be released from blocking a (descriptor) address. 151 <legal all> 152 */ 153 154 #define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000000 155 #define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 33 156 #define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 34 157 #define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000600000000 158 159 160 /* Description RESERVED_1A 161 162 <legal 0> 163 */ 164 165 #define REO_UNBLOCK_CACHE_RESERVED_1A_OFFSET 0x0000000000000000 166 #define REO_UNBLOCK_CACHE_RESERVED_1A_LSB 35 167 #define REO_UNBLOCK_CACHE_RESERVED_1A_MSB 63 168 #define REO_UNBLOCK_CACHE_RESERVED_1A_MASK 0xfffffff800000000 169 170 171 /* Description RESERVED_2A 172 173 <legal 0> 174 */ 175 176 #define REO_UNBLOCK_CACHE_RESERVED_2A_OFFSET 0x0000000000000008 177 #define REO_UNBLOCK_CACHE_RESERVED_2A_LSB 0 178 #define REO_UNBLOCK_CACHE_RESERVED_2A_MSB 31 179 #define REO_UNBLOCK_CACHE_RESERVED_2A_MASK 0x00000000ffffffff 180 181 182 /* Description RESERVED_3A 183 184 <legal 0> 185 */ 186 187 #define REO_UNBLOCK_CACHE_RESERVED_3A_OFFSET 0x0000000000000008 188 #define REO_UNBLOCK_CACHE_RESERVED_3A_LSB 32 189 #define REO_UNBLOCK_CACHE_RESERVED_3A_MSB 63 190 #define REO_UNBLOCK_CACHE_RESERVED_3A_MASK 0xffffffff00000000 191 192 193 /* Description RESERVED_4A 194 195 <legal 0> 196 */ 197 198 #define REO_UNBLOCK_CACHE_RESERVED_4A_OFFSET 0x0000000000000010 199 #define REO_UNBLOCK_CACHE_RESERVED_4A_LSB 0 200 #define REO_UNBLOCK_CACHE_RESERVED_4A_MSB 31 201 #define REO_UNBLOCK_CACHE_RESERVED_4A_MASK 0x00000000ffffffff 202 203 204 /* Description RESERVED_5A 205 206 <legal 0> 207 */ 208 209 #define REO_UNBLOCK_CACHE_RESERVED_5A_OFFSET 0x0000000000000010 210 #define REO_UNBLOCK_CACHE_RESERVED_5A_LSB 32 211 #define REO_UNBLOCK_CACHE_RESERVED_5A_MSB 63 212 #define REO_UNBLOCK_CACHE_RESERVED_5A_MASK 0xffffffff00000000 213 214 215 /* Description RESERVED_6A 216 217 <legal 0> 218 */ 219 220 #define REO_UNBLOCK_CACHE_RESERVED_6A_OFFSET 0x0000000000000018 221 #define REO_UNBLOCK_CACHE_RESERVED_6A_LSB 0 222 #define REO_UNBLOCK_CACHE_RESERVED_6A_MSB 31 223 #define REO_UNBLOCK_CACHE_RESERVED_6A_MASK 0x00000000ffffffff 224 225 226 /* Description RESERVED_7A 227 228 <legal 0> 229 */ 230 231 #define REO_UNBLOCK_CACHE_RESERVED_7A_OFFSET 0x0000000000000018 232 #define REO_UNBLOCK_CACHE_RESERVED_7A_LSB 32 233 #define REO_UNBLOCK_CACHE_RESERVED_7A_MSB 63 234 #define REO_UNBLOCK_CACHE_RESERVED_7A_MASK 0xffffffff00000000 235 236 237 /* Description RESERVED_8A 238 239 <legal 0> 240 */ 241 242 #define REO_UNBLOCK_CACHE_RESERVED_8A_OFFSET 0x0000000000000020 243 #define REO_UNBLOCK_CACHE_RESERVED_8A_LSB 0 244 #define REO_UNBLOCK_CACHE_RESERVED_8A_MSB 31 245 #define REO_UNBLOCK_CACHE_RESERVED_8A_MASK 0x00000000ffffffff 246 247 248 /* Description TLV64_PADDING 249 250 Automatic DWORD padding inserted while converting TLV32 251 to TLV64 for 64 bit ARCH 252 <legal 0> 253 */ 254 255 #define REO_UNBLOCK_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020 256 #define REO_UNBLOCK_CACHE_TLV64_PADDING_LSB 32 257 #define REO_UNBLOCK_CACHE_TLV64_PADDING_MSB 63 258 #define REO_UNBLOCK_CACHE_TLV64_PADDING_MASK 0xffffffff00000000 259 260 261 262 #endif // REO_UNBLOCK_CACHE 263