1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _REO_FLUSH_CACHE_STATUS_H_ 18 #define _REO_FLUSH_CACHE_STATUS_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "uniform_reo_status_header.h" 23 #define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 26 24 25 #define NUM_OF_QWORDS_REO_FLUSH_CACHE_STATUS 13 26 27 28 struct reo_flush_cache_status { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct uniform_reo_status_header status_header; 31 uint32_t error_detected : 1, // [0:0] 32 block_error_details : 2, // [2:1] 33 reserved_2a : 5, // [7:3] 34 cache_controller_flush_status_hit : 1, // [8:8] 35 cache_controller_flush_status_desc_type : 3, // [11:9] 36 cache_controller_flush_status_client_id : 4, // [15:12] 37 cache_controller_flush_status_error : 2, // [17:16] 38 cache_controller_flush_count : 8, // [25:18] 39 flush_queue_1k_desc : 1, // [26:26] 40 reserved_2b : 5; // [31:27] 41 uint32_t reserved_3a : 32; // [31:0] 42 uint32_t reserved_4a : 32; // [31:0] 43 uint32_t reserved_5a : 32; // [31:0] 44 uint32_t reserved_6a : 32; // [31:0] 45 uint32_t reserved_7a : 32; // [31:0] 46 uint32_t reserved_8a : 32; // [31:0] 47 uint32_t reserved_9a : 32; // [31:0] 48 uint32_t reserved_10a : 32; // [31:0] 49 uint32_t reserved_11a : 32; // [31:0] 50 uint32_t reserved_12a : 32; // [31:0] 51 uint32_t reserved_13a : 32; // [31:0] 52 uint32_t reserved_14a : 32; // [31:0] 53 uint32_t reserved_15a : 32; // [31:0] 54 uint32_t reserved_16a : 32; // [31:0] 55 uint32_t reserved_17a : 32; // [31:0] 56 uint32_t reserved_18a : 32; // [31:0] 57 uint32_t reserved_19a : 32; // [31:0] 58 uint32_t reserved_20a : 32; // [31:0] 59 uint32_t reserved_21a : 32; // [31:0] 60 uint32_t reserved_22a : 32; // [31:0] 61 uint32_t reserved_23a : 32; // [31:0] 62 uint32_t reserved_24a : 32; // [31:0] 63 uint32_t reserved_25a : 28, // [27:0] 64 looping_count : 4; // [31:28] 65 #else 66 struct uniform_reo_status_header status_header; 67 uint32_t reserved_2b : 5, // [31:27] 68 flush_queue_1k_desc : 1, // [26:26] 69 cache_controller_flush_count : 8, // [25:18] 70 cache_controller_flush_status_error : 2, // [17:16] 71 cache_controller_flush_status_client_id : 4, // [15:12] 72 cache_controller_flush_status_desc_type : 3, // [11:9] 73 cache_controller_flush_status_hit : 1, // [8:8] 74 reserved_2a : 5, // [7:3] 75 block_error_details : 2, // [2:1] 76 error_detected : 1; // [0:0] 77 uint32_t reserved_3a : 32; // [31:0] 78 uint32_t reserved_4a : 32; // [31:0] 79 uint32_t reserved_5a : 32; // [31:0] 80 uint32_t reserved_6a : 32; // [31:0] 81 uint32_t reserved_7a : 32; // [31:0] 82 uint32_t reserved_8a : 32; // [31:0] 83 uint32_t reserved_9a : 32; // [31:0] 84 uint32_t reserved_10a : 32; // [31:0] 85 uint32_t reserved_11a : 32; // [31:0] 86 uint32_t reserved_12a : 32; // [31:0] 87 uint32_t reserved_13a : 32; // [31:0] 88 uint32_t reserved_14a : 32; // [31:0] 89 uint32_t reserved_15a : 32; // [31:0] 90 uint32_t reserved_16a : 32; // [31:0] 91 uint32_t reserved_17a : 32; // [31:0] 92 uint32_t reserved_18a : 32; // [31:0] 93 uint32_t reserved_19a : 32; // [31:0] 94 uint32_t reserved_20a : 32; // [31:0] 95 uint32_t reserved_21a : 32; // [31:0] 96 uint32_t reserved_22a : 32; // [31:0] 97 uint32_t reserved_23a : 32; // [31:0] 98 uint32_t reserved_24a : 32; // [31:0] 99 uint32_t looping_count : 4, // [31:28] 100 reserved_25a : 28; // [27:0] 101 #endif 102 }; 103 104 105 /* Description STATUS_HEADER 106 107 Consumer: SW 108 Producer: REO 109 110 Details that can link this status with the original command. 111 It also contains info on how long REO took to execute this 112 command. 113 */ 114 115 116 /* Description REO_STATUS_NUMBER 117 118 Consumer: SW , DEBUG 119 Producer: REO 120 121 The value in this field is equal to value of the 'REO_CMD_Number' 122 field the REO command 123 124 This field helps to correlate the statuses with the REO 125 commands. 126 127 <legal all> 128 */ 129 130 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 131 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 132 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 133 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 134 135 136 /* Description CMD_EXECUTION_TIME 137 138 Consumer: DEBUG 139 Producer: REO 140 141 The amount of time REO took to excecute the command. Note 142 that this time does not include the duration of the command 143 waiting in the command ring, before the execution started. 144 145 146 In us. 147 148 <legal all> 149 */ 150 151 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 152 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 153 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 154 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 155 156 157 /* Description REO_CMD_EXECUTION_STATUS 158 159 Consumer: DEBUG 160 Producer: REO 161 162 Execution status of the command. 163 164 <enum 0 reo_successful_execution> Command has successfully 165 be executed 166 <enum 1 reo_blocked_execution> Command could not be executed 167 as the queue or cache was blocked 168 <enum 2 reo_failed_execution> Command has encountered problems 169 when executing, like the queue descriptor not being valid. 170 None of the status fields in the entire STATUS TLV are valid. 171 172 <enum 3 reo_resource_blocked> Command is NOT executed because 173 one or more descriptors were blocked. This is SW programming 174 mistake. 175 None of the status fields in the entire STATUS TLV are valid. 176 177 178 <legal 0-3> 179 */ 180 181 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 182 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 183 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 184 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 185 186 187 /* Description RESERVED_0A 188 189 <legal 0> 190 */ 191 192 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 193 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 194 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 195 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 196 197 198 /* Description TIMESTAMP 199 200 Timestamp at the moment that this status report is written. 201 202 203 <legal all> 204 */ 205 206 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 207 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 208 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 209 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 210 211 212 /* Description ERROR_DETECTED 213 214 Status for blocking resource handling 215 216 0: No error has been detected while executing this command 217 218 1: an error in the blocking resource management was detected 219 220 See field 'Block_error_details' 221 */ 222 223 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 224 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB 0 225 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB 0 226 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 227 228 229 /* Description BLOCK_ERROR_DETAILS 230 231 Field only valid when 'Error_detected' is set. 232 0: no blocking related error found 233 1: blocking resource was already in use 234 2: resource that was asked to be unblocked, was not blocked 235 236 <legal 0-2> 237 */ 238 239 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET 0x0000000000000008 240 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB 1 241 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB 2 242 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK 0x0000000000000006 243 244 245 /* Description RESERVED_2A 246 247 <legal 0> 248 */ 249 250 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 251 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB 3 252 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB 7 253 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK 0x00000000000000f8 254 255 256 /* Description CACHE_CONTROLLER_FLUSH_STATUS_HIT 257 258 The status that the cache controller returned for executing 259 the flush command 260 261 descriptor hit 262 1 = hit 263 0 = miss 264 <legal all> 265 */ 266 267 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x0000000000000008 268 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8 269 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB 8 270 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x0000000000000100 271 272 273 /* Description CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE 274 275 The status that the cache controller returned for executing 276 the flush command 277 Descriptor type 278 FLOW_QUEUE_DESCRIPTOR 3'd0 279 MPDU_LINK_DESCRIPTOR 3'd4 280 <legal all> 281 */ 282 283 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x0000000000000008 284 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9 285 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB 11 286 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x0000000000000e00 287 288 289 /* Description CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID 290 291 The status that the cache controller returned for executing 292 the flush command 293 294 client ID 295 Module who made flush the request 296 297 In REO, this is always set to 0 298 <legal 0> 299 */ 300 301 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x0000000000000008 302 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12 303 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB 15 304 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x000000000000f000 305 306 307 /* Description CACHE_CONTROLLER_FLUSH_STATUS_ERROR 308 309 The status that the cache controller returned for executing 310 the flush command 311 312 Error condition 313 2'b00: No error found 314 2'b01: HW IF still busy 315 2'b10: Line is currently locked. Used for the one line flush 316 command. 317 2'b11: At least one line is currently still locked. Used 318 for the cache flush command. 319 320 <legal all> 321 */ 322 323 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x0000000000000008 324 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16 325 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB 17 326 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x0000000000030000 327 328 329 /* Description CACHE_CONTROLLER_FLUSH_COUNT 330 331 The number of lines that were actually flushed out. 332 <legal all> 333 */ 334 335 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x0000000000000008 336 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18 337 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB 25 338 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x0000000003fc0000 339 340 341 /* Description FLUSH_QUEUE_1K_DESC 342 343 When set, REO has flushed the 'RX_REO_QUEUE_1K' descriptor 344 after flushing the 'RX_REO_QUEUE' descriptor. 345 <legal all> 346 */ 347 348 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008 349 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB 26 350 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB 26 351 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK 0x0000000004000000 352 353 354 /* Description RESERVED_2B 355 356 <legal 0> 357 */ 358 359 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET 0x0000000000000008 360 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB 27 361 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB 31 362 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK 0x00000000f8000000 363 364 365 /* Description RESERVED_3A 366 367 <legal 0> 368 */ 369 370 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 371 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB 32 372 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB 63 373 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 374 375 376 /* Description RESERVED_4A 377 378 <legal 0> 379 */ 380 381 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 382 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB 0 383 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB 31 384 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff 385 386 387 /* Description RESERVED_5A 388 389 <legal 0> 390 */ 391 392 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 393 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB 32 394 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB 63 395 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 396 397 398 /* Description RESERVED_6A 399 400 <legal 0> 401 */ 402 403 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 404 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB 0 405 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB 31 406 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff 407 408 409 /* Description RESERVED_7A 410 411 <legal 0> 412 */ 413 414 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 415 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB 32 416 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB 63 417 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 418 419 420 /* Description RESERVED_8A 421 422 <legal 0> 423 */ 424 425 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 426 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB 0 427 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB 31 428 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff 429 430 431 /* Description RESERVED_9A 432 433 <legal 0> 434 */ 435 436 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 437 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB 32 438 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB 63 439 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 440 441 442 /* Description RESERVED_10A 443 444 <legal 0> 445 */ 446 447 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 448 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB 0 449 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB 31 450 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 451 452 453 /* Description RESERVED_11A 454 455 <legal 0> 456 */ 457 458 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 459 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB 32 460 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB 63 461 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 462 463 464 /* Description RESERVED_12A 465 466 <legal 0> 467 */ 468 469 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 470 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB 0 471 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB 31 472 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 473 474 475 /* Description RESERVED_13A 476 477 <legal 0> 478 */ 479 480 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 481 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB 32 482 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB 63 483 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 484 485 486 /* Description RESERVED_14A 487 488 <legal 0> 489 */ 490 491 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 492 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB 0 493 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB 31 494 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 495 496 497 /* Description RESERVED_15A 498 499 <legal 0> 500 */ 501 502 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 503 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB 32 504 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB 63 505 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 506 507 508 /* Description RESERVED_16A 509 510 <legal 0> 511 */ 512 513 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 514 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB 0 515 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB 31 516 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 517 518 519 /* Description RESERVED_17A 520 521 <legal 0> 522 */ 523 524 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 525 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB 32 526 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB 63 527 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 528 529 530 /* Description RESERVED_18A 531 532 <legal 0> 533 */ 534 535 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 536 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB 0 537 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB 31 538 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 539 540 541 /* Description RESERVED_19A 542 543 <legal 0> 544 */ 545 546 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 547 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB 32 548 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB 63 549 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 550 551 552 /* Description RESERVED_20A 553 554 <legal 0> 555 */ 556 557 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 558 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB 0 559 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB 31 560 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 561 562 563 /* Description RESERVED_21A 564 565 <legal 0> 566 */ 567 568 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 569 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB 32 570 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB 63 571 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 572 573 574 /* Description RESERVED_22A 575 576 <legal 0> 577 */ 578 579 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 580 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB 0 581 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB 31 582 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 583 584 585 /* Description RESERVED_23A 586 587 <legal 0> 588 */ 589 590 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 591 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB 32 592 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB 63 593 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 594 595 596 /* Description RESERVED_24A 597 598 <legal 0> 599 */ 600 601 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 602 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB 0 603 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB 31 604 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 605 606 607 /* Description RESERVED_25A 608 609 <legal 0> 610 */ 611 612 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 613 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB 32 614 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB 59 615 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 616 617 618 /* Description LOOPING_COUNT 619 620 A count value that indicates the number of times the producer 621 of entries into this Ring has looped around the ring. 622 At initialization time, this value is set to 0. On the first 623 loop, this value is set to 1. After the max value is reached 624 allowed by the number of bits for this field, the count 625 value continues with 0 again. 626 627 In case SW is the consumer of the ring entries, it can use 628 this field to figure out up to where the producer of entries 629 has created new entries. This eliminates the need to check 630 where the "head pointer' of the ring is located once the 631 SW starts processing an interrupt indicating that new entries 632 have been put into this ring... 633 634 Also note that SW if it wants only needs to look at the 635 LSB bit of this count value. 636 <legal all> 637 */ 638 639 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 640 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB 60 641 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB 63 642 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 643 644 645 646 #endif // REO_FLUSH_CACHE_STATUS 647