1 /*
2  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef _MON_DESTINATION_RING_H_
18 #define _MON_DESTINATION_RING_H_
19 #if !defined(__ASSEMBLER__)
20 #endif
21 
22 #define NUM_OF_DWORDS_MON_DESTINATION_RING 4
23 
24 
25 struct mon_destination_ring {
26 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
27              uint32_t stat_buf_virt_addr_31_0                                 : 32; // [31:0]
28              uint32_t stat_buf_virt_addr_63_32                                : 32; // [31:0]
29              uint32_t ppdu_id                                                 : 32; // [31:0]
30              uint32_t end_offset                                              : 12, // [11:0]
31                       reserved_3a                                             :  4, // [15:12]
32                       end_reason                                              :  2, // [17:16]
33                       initiator                                               :  1, // [18:18]
34                       empty_descriptor                                        :  1, // [19:19]
35                       ring_id                                                 :  8, // [27:20]
36                       looping_count                                           :  4; // [31:28]
37 #else
38              uint32_t stat_buf_virt_addr_31_0                                 : 32; // [31:0]
39              uint32_t stat_buf_virt_addr_63_32                                : 32; // [31:0]
40              uint32_t ppdu_id                                                 : 32; // [31:0]
41              uint32_t looping_count                                           :  4, // [31:28]
42                       ring_id                                                 :  8, // [27:20]
43                       empty_descriptor                                        :  1, // [19:19]
44                       initiator                                               :  1, // [18:18]
45                       end_reason                                              :  2, // [17:16]
46                       reserved_3a                                             :  4, // [15:12]
47                       end_offset                                              : 12; // [11:0]
48 #endif
49 };
50 
51 
52 /* Description		STAT_BUF_VIRT_ADDR_31_0
53 
54 			Lower 32 bits of the 64-bit virtual address of the status
55 			 buffer
56 			<legal all>
57 */
58 
59 #define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET                         0x00000000
60 #define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB                            0
61 #define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB                            31
62 #define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK                           0xffffffff
63 
64 
65 /* Description		STAT_BUF_VIRT_ADDR_63_32
66 
67 			Upper 32 bits of the 64-bit virtual address of the status
68 			 buffer
69 			<legal all>
70 */
71 
72 #define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET                        0x00000004
73 #define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB                           0
74 #define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB                           31
75 #define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK                          0xffffffff
76 
77 
78 /* Description		PPDU_ID
79 
80 			TXMON fills this with the schedule_id from 'TX_FES_SETUP'
81 			when Initiator = 1.
82 			TXMON fills this with the Phy_ppdu_id from 'RX_RESPONSE_REQUIRED_INFO'
83 			when Initiator = 0.
84 			RXMON fills this with the Phy_ppdu_id from 'RX_PPDU_START.'
85 
86 			<legal all>
87 */
88 
89 #define MON_DESTINATION_RING_PPDU_ID_OFFSET                                         0x00000008
90 #define MON_DESTINATION_RING_PPDU_ID_LSB                                            0
91 #define MON_DESTINATION_RING_PPDU_ID_MSB                                            31
92 #define MON_DESTINATION_RING_PPDU_ID_MASK                                           0xffffffff
93 
94 
95 /* Description		END_OFFSET
96 
97 			The offset (in units of 4 bytes) into the status buffer
98 			where DMA ended, i.e. offset to the last TLV + last TLV
99 			size MINUS 1.
100 
101 			In case of a 'TX_FLUSH' or 'RX_FLUSH,' this reflects the
102 			 offset at which flush occurred.
103 			<legal all>
104 */
105 
106 #define MON_DESTINATION_RING_END_OFFSET_OFFSET                                      0x0000000c
107 #define MON_DESTINATION_RING_END_OFFSET_LSB                                         0
108 #define MON_DESTINATION_RING_END_OFFSET_MSB                                         11
109 #define MON_DESTINATION_RING_END_OFFSET_MASK                                        0x00000fff
110 
111 
112 /* Description		RESERVED_3A
113 
114 			<legal 0>
115 */
116 
117 #define MON_DESTINATION_RING_RESERVED_3A_OFFSET                                     0x0000000c
118 #define MON_DESTINATION_RING_RESERVED_3A_LSB                                        12
119 #define MON_DESTINATION_RING_RESERVED_3A_MSB                                        15
120 #define MON_DESTINATION_RING_RESERVED_3A_MASK                                       0x0000f000
121 
122 
123 /* Description		END_REASON
124 
125 			<enum 0 MON_status_buffer_full> The status buffer was fully
126 			 written.
127 			<enum 1 MON_flush_detected> A 'TX_FLUSH' or 'RX_FLUSH' was
128 			 received. This is implicitly the end of the Tx FES or Rx
129 			 PPDU. The status buffer data can be discarded by SW.
130 			<enum 2 MON_end_of_PPDU> A 'TX_FES_STATUS_END' or 'RX_PPDU_END'
131 			was received indicating the end of the Tx FES or Rx PPDU.
132 
133 			<enum 3 MON_PPDU_truncated> The PPDU got truncated due to
134 			 a system-level error.
135 			<legal all>
136 */
137 
138 #define MON_DESTINATION_RING_END_REASON_OFFSET                                      0x0000000c
139 #define MON_DESTINATION_RING_END_REASON_LSB                                         16
140 #define MON_DESTINATION_RING_END_REASON_MSB                                         17
141 #define MON_DESTINATION_RING_END_REASON_MASK                                        0x00030000
142 
143 
144 /* Description		INITIATOR
145 
146 			1: This descriptor belongs to a TX FES (TXOP initiator)
147 			0: This descriptor belongs to a response TX (TXOP responder)
148 
149 			<legal all>
150 */
151 
152 #define MON_DESTINATION_RING_INITIATOR_OFFSET                                       0x0000000c
153 #define MON_DESTINATION_RING_INITIATOR_LSB                                          18
154 #define MON_DESTINATION_RING_INITIATOR_MSB                                          18
155 #define MON_DESTINATION_RING_INITIATOR_MASK                                         0x00040000
156 
157 
158 /* Description		EMPTY_DESCRIPTOR
159 
160 			0: This descriptor is written on a flush or the end of a
161 			 PPDU or the end of status buffer
162 			1: This descriptor is written to indicate drop information
163 			 (see 'MON_DESTINATION_RING_WITH_DROP' structure)
164 			<legal 0>
165 */
166 
167 #define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET                                0x0000000c
168 #define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB                                   19
169 #define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB                                   19
170 #define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK                                  0x00080000
171 
172 
173 /* Description		RING_ID
174 
175 			Consumer: SW/REO/DEBUG
176 			Producer: SRNG (of TXMON/RXMON)
177 
178 			For debugging.
179 			This field is filled in by the SRNG module.
180 			It help to identify the ring that is being looked
181 			<legal 0>
182 */
183 
184 #define MON_DESTINATION_RING_RING_ID_OFFSET                                         0x0000000c
185 #define MON_DESTINATION_RING_RING_ID_LSB                                            20
186 #define MON_DESTINATION_RING_RING_ID_MSB                                            27
187 #define MON_DESTINATION_RING_RING_ID_MASK                                           0x0ff00000
188 
189 
190 /* Description		LOOPING_COUNT
191 
192 			Consumer: SW/DEBUG
193 			Producer: SRNG (of TXMON/RXMON)
194 
195 			For debugging.
196 			This field is filled in by the SRNG module.
197 
198 			A count value that indicates the number of times the producer
199 			 of entries into this Ring has looped around the ring.
200 			At initialization time, this value is set to 0. On the first
201 			 loop, this value is set to 1. After the max value is reached
202 			 allowed by the number of bits for this field, the count
203 			 value continues with 0 again.
204 
205 			In case SW is the consumer of the ring entries, it can use
206 			 this field to figure out up to where the producer of entries
207 			 has created new entries. This eliminates the need to check
208 			 where the "head pointer' of the ring is located once the
209 			 SW starts processing an interrupt indicating that new entries
210 			 have been put into this ring...
211 
212 			Also note that SW if it wants only needs to look at the
213 			LSB bit of this count value.
214 			<legal all>
215 */
216 
217 #define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET                                   0x0000000c
218 #define MON_DESTINATION_RING_LOOPING_COUNT_LSB                                      28
219 #define MON_DESTINATION_RING_LOOPING_COUNT_MSB                                      31
220 #define MON_DESTINATION_RING_LOOPING_COUNT_MASK                                     0xf0000000
221 
222 
223 
224 #endif   // MON_DESTINATION_RING
225